K4S280832E-TC750 [SAMSUNG]
Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54;
| 型号： | K4S280832E-TC750 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
128Mb E-die SDRAM Specification
Revision 1.4
February 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
Revision History
Revision 1.0 (November, 2002)
- First release.
Revision 1.1 (April, 2003)
- x4/x8/x16 Merged spec.
Revision 1.2 (May, 2003)
- Delete -TC(L)7C
Revision 1.3 (January, 2004)
- Modified ICC4 current from 110mA -> 140mA at x16
- Modified tSH from 0.8ns -> 1.0ns at 166MHz.
Revision 1.4 (February, 2004)
- Corrected typo.
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
The K4S280432E / K4S280832E / K4S281632E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x
8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
Orgainization
32M x 4
Max Freq.
133MHz
133MHz
166MHz
Interface
LVTTL
Package
K4S280432E-TC(L)75
K4S280832E-TC(L)75
K4S281632E-TC(L)60/75
54pin TSOP
54pin TSOP
54pin TSOP
16M x 8
LVTTL
8M x 16
LVTTL
Organization
Row Address
Column Address
32Mx4
16Mx8
8Mx16
A0~A11
A0~A11
A0~A11
A0-A9, A11
A0-A9
A0-A8
Row & Column address configuration
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
Package Physical Dimension
0~8°C
0.25
0.010
TYP
#54
#28
#1
#27
+0.075
-0.035
+0.003
-0.001
0.125
0.005
22.62
MAX
0.891
22.22
± 0.10
0.21 ± 0.05
± 0.10
1.00
0.039
1.20
0.047
MAX
± 0.004
± 0.002
0.875
± 0.004
0.008
0.10
MAX
0.004
+0.10
0.05
0.002
MIN
0.30
0.80
0.0315
0.71
-0.05
(
)
+0.004
0.028
0.012
-0.002
54Pin TSOP Package Dimension
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
PIN CONFIGURATION (Top view)
x8
VDD
x4
VDD
x4
VSS
N.C
VSSQ
N.C
DQ3
VDDQ
N.C
N.C
VSSQ
N.C
x8
VSS
x16
x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
1
2
3
4
5
6
7
8
9
10
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
N.C
VDDQ
N.C
DQ0
VSSQ
N.C
N.C
VDDQ
N.C
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
DQ1 11
DQ2
VDDQ
N.C
VSSQ
N.C
VDD
N.C
WE 16
CAS 17
RAS 18
CS 19
12
13
14
15
VDDQ
DQ8
VSS
VSS
VSS
N.C/RFU N.C/RFU N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
BA0 20
BA1 21
A10/AP A10/AP A10/AP 22
A0
A1
A2
A3
VDD
A0
A1
A2
A3
VDD
A0 23
A1 24
A2 25
A3 26
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
A4
VSS
A4
VSS
A4
VSS
VDD
27
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Input Function
Active on the positive going edge to sample all inputs.
CLK
CS
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,
A0 ~ A11
Address
Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)
DQ0 ~ N
Data input/output
VDD/VSS
VDDQ/VSSQ
Power supply/ground
Data output power/ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
No connection
/reserved for future use
N.C/RFU
This pin is recommended to be left No Connection on the device.
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
Max
3.6
Unit
V
Note
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VDD+0.3
0.8
V
1
VIL
V
2
VOH
-
-
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
V
ILI
-10
-
10
uA
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Notes :
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Symbol
CCLK
CIN
Min
2.5
2.5
2.5
4.0
Max
3.5
3.8
3.8
6.0
Unit
pF
Note
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
pF
CADD
COUT
pF
(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15)
pF
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
DC CHARACTERISTICS (x4, x8)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
-75
Parameter
Symbol
Test Condition
Unit
mA
mA
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
90
1
ICC2P CKE ≤ VIL(max), tCC = 10ns
2
2
Precharge standby current in
power-down mode
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N
20
10
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS
Input signals are stable
ICC3P CKE ≤ VIL(max), tCC = 10ns
5
5
Active standby current in
power-down mode
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC3N
30
25
mA
mA
mA
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3NS
Operating current
(Burst mode)
IO = 0 mA
ICC4
110
1
Page burst
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
200
2
mA
mA
uA
2
3
4
C
L
Self refresh current
800
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S2804(08)32E-TC
4. K4S2804(08)32E-TL
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
DC CHARACTERISTICS (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit
mA
mA
Note
-60
-75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
130
100
1
ICC2P CKE ≤ VIL(max), tCC = 10ns
2
2
Precharge standby current in
power-down mode
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N
20
10
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS
Input signals are stable
ICC3P CKE ≤ VIL(max), tCC = 10ns
5
5
Active standby current in
power-down mode
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC3N
30
25
mA
mA
mA
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3NS
Operating current
(Burst mode)
IO = 0 mA
ICC4
150
220
140
200
1
Page burst
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
mA
mA
uA
2
3
4
C
L
2
Self refresh current
800
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S281632E-TC
4. K4S281632E-TL
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
50pF
50pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
- 60 (x16 only)
Parameter
Symbol
Unit
Note
- 75
15
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
12
18
18
42
ns
ns
1
1
1
1
20
Row precharge time
20
ns
tRAS(min)
tRAS(max)
tRC(min)
45
ns
Row active time
100
us
Row cycle time
60
65
ns
1
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + tRP
1
1
1
2
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- 60 (x16 only)
- 75
Parameter
Symbol
tCC
Unit
ns
Note
1
Min
Max
Min
7.5
10
Max
CAS latency=3
6
-
CLK cycle
time
1000
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
5
-
5.4
6
CLK to valid
output delay
tSAC
ns
1,2
2
2.5
-
3
Output data
hold time
tOH
ns
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
1.0
1
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
5
-
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Measure in linear
region : 1.2V ~ 1.8V
Output rise time
trh
1.37
4.37
Volts/ns
Volts/ns
Volts/ns
Volts/ns
3
Measure in linear
region : 1.2V ~ 1.8V
Output fall time
Output rise time
Output fall time
tfh
trh
tfh
1.30
2.8
3.8
5.6
5.0
3
Measure in linear
region : 1.2V ~ 1.8V
3.9
2.9
1,2
1,2
Measure in linear
region : 1.2V ~ 1.8V
2.0
Notes :
1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
66MHz and 100MHz/133MHz Pull-up
0.5 1.5 2.5
IBIS SPECIFICATION
0
1
2
3
3.5
IOH Characteristics (Pull-up)
0
-100
-200
-300
-400
-500
-600
100MHz
133MHz
Min
100MHz
133MHz
Max
I (mA)
-2.4
66MHz
Min
Voltage
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
I (mA)
I (mA)
-27.3
-74.1
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
-0.7
-7.5
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93.0
Voltage
IOH Min (100MHz/133MHz)
IOH Min (66MHz)
IOH Max (66 and 100MHz/133MHz)
66MHz and 100MHz/133MHz Pull-down
IOL Characteristics (Pull-down)
250
200
150
100
50
100MHz
133MHz
Min
100MHz
133MHz
Max
66MHz
Min
Voltage
(V)
0.0
I (mA)
0.0
I (mA)
0.0
I (mA)
0.0
0.4
27.5
70.2
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
0.65
0.85
1.0
1.4
1.5
1.65
1.8
1.95
3.0
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
80.3
81.4
0
3.45
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (100MHz/133MHz)
IOL Min (66MHz)
IOL Max (100MHz/133MHz)
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
Minimum VDD clamp current
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
I (mA)
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
20
15
10
5
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
-2 -1
VSS Clamp @ CLK, CKE, CS, DQM & DQ
-3
0
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0
-10
-20
-30
-40
-50
-60
0.0
0.0
0.0
Voltage
I (mA)
Rev. 1.4 February. 2004
CMOS SDRAM
SDRAM 128Mb E-die (x4, x8, x16)
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
A0 ~ A9,
A11,
Command
Mode register set
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Register
Refresh
H
X
H
L
L
L
L
L
X
OP code
1,2
3
Auto refresh
H
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
L
H
H
H
X
X
3
Bank active & row addr.
X
X
V
V
Row address
L
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
4
4,5
4
Column
L
H
L
H
address
H
L
Write &
column address
Column
address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
4,5
6
Burst stop
Precharge
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
X
H
L
Entry
H
Precharge power down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No operation command
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.4 February. 2004
相关型号：
K4S280832E-TL7C0
Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
SAMSUNG
©2020 ICPDF网 联系我们和版权申明