K4S281633D-RL1L [SAMSUNG]
Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, CSP-54;
| 型号： | K4S281633D-RL1L |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, CSP-54 动态存储器 |
| 文件： | 总8页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S281633D-R(B)L/N/P
CMOS SDRAM
8Mx16
Mobile SDRAM
54CSP
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
Revision 1.3
December 2002
Rev. 1.3 Dec. 2002
K4S281633D-R(B)L/N/P
CMOS SDRAM
2M x 16Bit x 4 Banks SDRAM in 54CSP
FEATURES
GENERAL DESCRIPTION
• 3.0V & 3.3V power supply.
The K4S281633D is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG¢s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation..
• DQM for masking.
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
• Auto refresh.
133MHz(CL=3)
105MHz(CL=2)
• 64ms refresh period (4K cycle).
K4S281633D-R(B)L/N/P75
54 CSP
• Commercial Temperature Operation (-25°C ~ 70°C).
Extended Temperature Operation (-25°C ~ 85°C).
Industrial Temperature Operation (-40°C ~ 85°C).
• 54balls CSP( -RXXX -Pb, -BXXX -Pb Free).
LVCMOS
Pb
K4S281633D-R(B)L/N/P1H 105MHz(CL=2)
(Pb Free)
*1
K4S281633D-R(B)L/N/P1L 105MHz(CL=3)
-R(B)L : Low Power, Operating Temperature : -25°C~70°C.
-R(B)N : Low Power, Operating Temperature : -25°C~85°C.
-R(B)P : Low Power, Operating Temperature : -40°C ~ 85°C.
Note :
FUNCTIONAL BLOCK DIAGRAM
1. In case of 40MHz Frequency, CL1 can be supported.
LWE
Data Input Register
LDQM
Bank Select
2M x 16
2M x 16
DQi
2M x 16
CLK
ADD
2M x 16
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
LDQM UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 Dec. 2002
K4S281633D-R(B)L/N/P
CMOS SDRAM
Package Dimension and Pin Configuration
*1
*2
< Bottom View >
< Top View >
E
1
54Ball(6x9) CSP
9
8
7
6
5
4
3
2
1
1
2
3
7
8
9
A
B
C
D
E
F
A
B
C
D
E
F
VSS
DQ15
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
VDDQ
VSSQ
VDDQ
VSSQ
VDD
DQ0
DQ2
DQ4
DQ6
VDD
DQ1
DQ3
DQ5
DQ14 DQ13
DQ12 DQ11
DQ10
DQ8
DQ9
NC
LDQM DQ7
UDQM CLK
CAS
BA0
A0
RAS
BA1
A1
WE
CS
G
H
J
G
H
J
NC
A8
A11
A7
A6
A10
VDD
VSS
A5
A4
A3
A2
E
E/2
Pin Name
CLK
Pin Function
System Clock
Chip Select
*2: Top View
CS
CKE
Clock Enable
A0 ~ A11
BA0 ~ BA1
RAS
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
A
A1
Max. 0.20
CAS
Encapsulant
z
b
WE
L(U)DQM
DQ0 ~ 15
VDD/VSS
VDDQ/VSSQ
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
*1: Bottom View
*2
< Top View >
#A1 Ball Origin Indicator
[Unit:mm]
Symbol
Min
Typ
0.95
0.35
8.00
6.40
8.00
6.40
0.80
0.45
-
Max
A
0.90
1.00
A
1
0.30
0.40
E
-
-
E
-
-
1
D
-
-
-
D
-
1
e
-
0.40
-
-
b
z
0.50
0.10
Rev. 1.3 Dec. 2002
K4S281633D-R(B)L/N/P
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Notes :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS = 0V, TA =Commercial, Extended, Industrial Temperature)
Parameter
Supply voltage
Symbol
VDD
VDDQ
VIH
Min
2.7
2.7
2.2
-0.3
2.4
-
Typ
3.0
3.0
3.0
0
Max
Unit
V
Note
3.6
3.6
V
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Notes:
VDDQ+0.3
V
1
VIL
0.5
-
V
2
VOH
VOL
ILI
-
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
1. VIH (max) = 5.3V AC. The overshoot voltage duration is£ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V£ VIN £ VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V £ VOUT £ VDDQ.
CAPACITANCE(VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
CCLK
CIN
Min
2.0
2.0
2.0
3.5
Max
4.0
4.0
4.0
6.0
Unit
Note
Clock
pF
pF
pF
pF
RAS, CAS, WE, CS, CKE, DQM
Address
CADD
COUT
DQ0 ~ DQ15
Rev. 1.3 Dec. 2002
K4S281633D-R(B)L/N/P
CMOS SDRAM
DC CHARACTERISTICS
Recommended operating conditions(Voltage referenced to VSS = 0V, TA =Commercial, Extended, Industrial Temperature)
Version
Parameter
Symbol
Test Condition
Unit
mA
mA
Note
-75
-1H
-1L
Burst length = 1
tRC ³ tRC(min)
IO = 0 mA
Operating Current
(One Bank Active)
ICC1
80
75
75
1
ICC2P
CKE £ VIL(max), tCC = 10ns
0.5
0.5
Precharge Standby Current
in power-down mode
ICC2PS CKE & CLK£ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC2N
12
10
Input signals are changed one time during 20ns
Precharge Standby Current
in non power-down mode
mA
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC2NS
Input signals are stable
ICC3P
CKE £ VIL(max), tCC = 10ns
7
7
Active Standby Current
in power-down mode
ICC3PS CKE & CLK£ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC3N
23
20
mA
mA
Active Standby Current
in non power-down mode
(One Bank Active)
Input signals are changed one time during 20ns
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC3NS
Input signals are stable
IO = 0 mA
Operating Current
(Burst Mode)
Page burst
4Banks Activated
tCCD = 2CLKs
ICC4
130
170
130
110
155
mA
1
Refresh Current
ICC5
ICC6
tRC ³ tRC(min)
170
500
mA
uA
2
3
4
5
-R(B)L
-R(B)N
-R(B)P
Self Refresh Current
CKE £ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S281633D-R(B)L**
4. K4S281633D-R(B)N**
5. K4S281633D-R(B)P**
6. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.3 Dec. 2002
K4S281633D-R(B)L/N/P
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 2.7V ~ 3.6V, TA =Commercial, Extended, Industrial Temperature)
Parameter
AC input levels (Vih/Vil)
Value
Unit
V
2.4 / 0.4
Input timing measurement reference level
Input rise and fall time
0.5 x VDDQ
tr/tf = 1/1
0.5 x VDDQ
See Fig. 2
V
ns
V
Output timing measurement reference level
Output load condition
VDDQ
Vtt = 0.5 x VDDQ
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
30pF
Output
Output
Z0 = 50W
30pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
-1L
Note
- 75
15
-1H
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP (min)
19
19
24
24
60
ns
ns
1
1
1
1
19
19
Row precharge time
19
19
ns
tRAS (min)
tRAS(max)
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
45
50
ns
Row active time
100
us
Row cycle time
65
70
84
ns
1
2,3
3
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2
CLK
-
tRDL + tRP
1
1
1
2
1
CLK
CLK
CLK
2
2
Col. address to col. address delay
4
CAS latency=3
Number of valid output data
ea
5
CAS latency=2
CAS latency=1
-
0
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.3 Dec. 2002
K4S281633D-R(B)L/N/P
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- 75
-1H
-1L
Parameter
Symbol
Unit
Note
Min
7.5
9.5
-
Max
Min
9.5
9.5
-
Max
Min
9.5
12
Max
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
CLK cycle time
tCC
1000
1000
1000
ns
1
25
5.4
7
7
7
-
7
8
CLK to valid output delay
Output data hold time
tSAC
tOH
ns
ns
1,2
2
-
20
2.5
2.5
-
2.5
2.5
-
2.5
2.5
2.5
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
2.0
1.0
1
3
ns
ns
ns
ns
ns
3
3
3
3
2
3
3
tSS
tSH
tSLZ
2.5
1.5
1
2.5
1.5
1
Input hold time
CLK to output in Low-Z
CAS latency=3
CAS latency=2
CAS latency=1
5.4
7
7
7
-
7
8
CLK to output in Hi-Z
tSHZ
ns
-
20
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Note :
1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is
potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product con-
tained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Rev. 1.3 Dec. 2002
K4S281633D-R(B)L/N/P
CMOS SDRAM
SIMPLIFIED TRUTH TABLE(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
A 11,
A9 ~ A0
COMMAND
Mode Register Set
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Register
Refresh
H
X
H
L
L
L
L
L
X
OP CODE
1, 2
3
Auto Refresh
H
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
L
H
H
H
X
X
3
Bank Active & Row Addr.
X
X
V
V
Row Address
Column
Address
(A0~A8)
Read &
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4, 5
4
L
H
L
H
Column Address
Column
Address
(A0~A8)
Write &
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
Column Address
H
4, 5
6
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No Operation Command
Notes :
1. OP Code : Operand Code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev. 1.3 Dec. 2002
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