K4S510832B-KL75 [SAMSUNG]
Synchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54;
| 型号： | K4S510832B-KL75 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 动态存储器 光电二极管 |
| 文件： | 总11页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S510832B
CMOS SDRAM
DDP 512Mbit SDRAM
16M x 8bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.2
April 2001
This is to advise Samsung customers that in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM
products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers,
work stations or desk top personal computers (hereinagter " Prohibited Computer Use"). Applications such as mobile, including cell phones,
telecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook computers, are,
however, permissible. "Multi-Die Plastic" is defined as two or more DRAM die encapsulated within a single plastic leaded package.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
Revision 0.0 (Nov., 2000)
Revision 0.1 (Mar., 2001)
•
Redefined DC Characteristics
Revision 0.2 (April, 2001)
•
Add comment for "IMPORTANT REMINDER OF THESE PRODUCT RESTRICTIONS"
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
16M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
The K4S510832B is 536,870,912 bits synchronous high data rate
Dynamic RAM organized as 4 x 16,785,216 words by 8 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
• Auto & self refresh
K4S510832B-KC/L75
K4S510832B-KC/L1H
K4S510832B-KC/L1L
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
• 64ms refresh period (8K Cycle)
54pin
LVTTL
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
2 x 8M x 8
2 x 8M x 8
2 x 8M x 8
2 x 8M x 8
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKEn
CS n
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
PIN CONFIGURATION (Top view)
VDD
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
1
2
3
4
5
6
7
8
VSS
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
VSS
CKE1
DQM
CLK
CKE0
A12
A11
A9
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VDD
CS1
WE
CAS
RAS
CS0
BA0
BA1
A10/AP
A0
A8
A7
A6
A5
A4
VSS
A1
A2
A3
VDD
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitcH)
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CS 0~1
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE0~1
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
A0 ~ A12
BA0 ~ BA1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
DQ0 ~7
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
VDD/VSS
Power supply/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VDDQ/VSSQ
Data output power/ground
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
2
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
3.6
Unit
V
Note
3.3
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
3.0
VDD+0.3
0.8
V
1
VIL
0
-
V
2
VOH
-
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
V
ILI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Symbol
CCLK
CIN
Min
5.0
5.0
5.0
2.5
8.0
Max
9.0
Unit
pF
Note
Clock
RAS, CAS, WE, DQM
Address
10.0
10.0
5.5
pF
CADD
Ccs
pF
CS0~1, CKE0~1
DQ0 ~ DQ7
pF
COUT
14.0
pF
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
-1H -1L
Parameter
Symbol
Test Condition
Unit
mA
Note
-75
Burst length = 1
tRC ³ tRC(min)
IO = 0 mA
Operating current
ICC1
135 125 125
1
(One bank active)
ICC2P
4
4
CKE £ VIL(max), tCC = 10ns
Precharge standby current in
power-down mode
mA
ICC2PS
CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2N
30
25
Precharge standby current in
non power-down mode
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC2NS
ICC3P
8
8
Active Standby current
in power-down mode
CKE £ VIL(max), tCC = 10ns
mA
mA
mA
ICC3PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC3N
45
40
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 20ns
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC3NS
Input signals are stable
IO = 0 mA
Page burst
4banks activated.
tCCD = 2CLKs
Operating current
(Burst mode)
ICC4
170 145 145
mA
1
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
CKE £ 0.2V
235 225 225
mA
mA
mA
2
3
4
C
L
6
4
Self refresh current
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S560832B-KC**
4. K4S560832B-KL**
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50W
50pF
50pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-75
-1H
-1L
20
20
20
50
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
15
20
20
45
20
ns
ns
1
1
1
1
20
Row precharge time
20
ns
tRAS(min)
tRAS(max)
tRC(min)
50
ns
Row active time
100
us
Row cycle time
65
70
70
ns
1
2,5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + 20 ns
1
1
1
2
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-75
-1H
-1L
Parameter
Symbol
tCC
Unit
ns
Note
1
Min
7.5
-
Max
Min
10
Max
Min
10
Max
CAS latency=3
CLK cycle time
1000
1000
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
10
12
5.4
-
6
6
6
7
CLK to valid
output delay
tSAC
ns
1,2
2
3
-
3
3
3
3
2
1
1
3
3
3
3
2
1
1
Output data
hold time
tOH
ns
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
tSH
Input hold time
CLK to output in Low-Z
tSLZ
CAS latency=3
CAS latency=2
5.4
-
6
6
6
7
CLK to output
in Hi-Z
tSHZ
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Measure in linear
region : 1.2V ~1.8V
Output rise time
trh
1.37
4.37
Volts/ns
Volts/ns
Volts/ns
Volts/ns
3
Measure in linear
region : 1.2V ~1.8V
Output fall time
Output rise time
Output fall time
tfh
trh
tfh
1.30
2.8
3.8
5.6
5.0
3
Measure in linear
region : 1.2V ~1.8V
3.9
2.9
1,2
1,2
Measure in linear
region : 1.2V ~1.8V
2.0
Notes :
1. Rise time specification based on 0pF + 50 Ohms to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ohms to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
66MHz, 100MHz and 133MHz Pull-up
0.5 1.5 2.5
IBIS SPECIFICATION
0
1
2
3
3.5
IOH Characteristics (Pull-up)
0
-100
-200
-300
-400
-500
-600
100MHz/
133MHz
Min
100MHz/
133MHz
Max
66MHz
Min
Voltage
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
I (mA)
I (mA)
-2.4
-27.3
I (mA)
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
-74.1
-0.7
-7.5
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93.0
Voltage
IOH Min (100MHz/133MHz)
IOH Min (66MHz)
IOH Max (66 and 100MHz/133MHz)
66MHz, 100MHz and 133MHz Pull-down
IOL Characteristics (Pull-down)
250
200
150
100
50
100MHz/
133MHz
Min
100MHz/
133MHz
Max
66MHz
Min
Voltage
(V)
0
I (mA)
0.0
I (mA)
0.0
I (mA)
0.0
0.4
0.65
0.85
1
1.4
1.5
1.65
1.8
1.95
3
27.5
41.8
51.6
58.0
70.2
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
70.7
72.9
75.4
77.0
77.6
80.3
0
3.45
81.4
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (100MHz/133MHz)
IOL Min (66MHz)
IOL Max (100MHz/133MHz)
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
Minimum VDD clamp current
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
I (mA)
0.0
0.0
20
15
10
5
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
-2 -1
VSS Clamp @ CLK, CKE, CS, DQM & DQ
-3
0
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0
-10
-20
-30
-40
-50
-60
0.0
0.0
0.0
Voltage
I (mA)
Rev.0.2 April 2001
K4S510832B
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
A11,A12,
A9 ~ A0
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA0,1
A10/AP
Note
Register
Refresh
Mode register set
Auto refresh
H
X
H
L
L
L
L
L
X
OP code
1,2
3
H
L
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Column
address
(A0 ~ A9 )
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
L
L
H
H
L
L
H
L
Column
address
(A0 ~ A9 )
Write &
column address
H
X
X
V
H
X
L
4,5
6
Burst Stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
Bank selection
All banks
V
X
X
H
H
L
X
V
X
X
H
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
V
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev.0.2 April 2001
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