K4S510832D-UCL75 [SAMSUNG]
Synchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, ROHS COMPLIANT, TSOP2-54;
| 型号： | K4S510832D-UCL75 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, ROHS COMPLIANT, TSOP2-54 动态存储器 光电二极管 |
| 文件： | 总16页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
512Mb D-die SDRAM Specification
54 TSOP-II
with Lead-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.11 August 2008
1 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
Table of Contents
1.0 Features....................................................................................................................................... 4
2.0 General Description.................................................................................................................... 4
3.0 Ordering Information.................................................................................................................. 4
4.0 Package Physical Dimension ................................................................................................... 5
5.0 Functional Block Diagram.......................................................................................................... 6
6.0 Pin Configuration (Top view)..................................................................................................... 7
7.0 Pin Function Description ........................................................................................................... 7
8.0 Absolute Maximum Ratings........................................................................................................8
9.0 DC Operating Conditions........................................................................................................... 8
10.0 Capacitance............................................................................................................................... 8
11.0 DC Characteristics (x4) ............................................................................................................9
12.0 DC Characteristics (x8) ..........................................................................................................10
13.0 DC Characteristics (x16) ........................................................................................................11
14.0 AC Operating Test Conditions ...............................................................................................12
15.0 Operating AC Parameter ........................................................................................................12
16.0 AC Characteristics ..................................................................................................................13
17.0 DQ Buffer Output Drive Characteristics ...............................................................................13
18.0 IBIS Specification ................................................................................................................... 14
19.0 Simplified Truth Table ............................................................................................................16
Rev. 1.11 August 2008
2 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
Revision History
Revision
0.0
Month
Year
2005
2005
2008
2008
History
May
November
March
- First release
- Revision 1.0
1.0
1.1
- Added Package pin out lead width
- Corrected font format
1.11
August
Rev. 1.11 August 2008
3 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks SDRAM
1.0 Features
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• 54pin TSOP II Lead-Free package
• RoHS compliant
2.0 General Description
The K4S510432D / K4S510832D / K4S511632D is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x
33,554,432 words by 4 bits / 4 x 16,777,216 words by 8 bits / 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG's high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
3.0 Ordering Information
Part No.
Orgainization
128Mb x 4 (CL=3)
64Mb x 8 (CL=3)
32Mb x 16 (CL=3)
Max Freq.
133MHz
133MHz
133MHz
Interface
Package
K4S510432D-UC(L)75
K4S510832D-UC(L)75
K4S511632D-UC(L)75
54pin TSOP(II)
Lead-Free
LVTTL
Organization
Row Address
Column Address
128Mx4
64Mx8
32Mx16
A0~A12
A0~A12
A0~A12
A0-A9, A11, A12
A0-A9, A11
A0-A9
Row & Column address configuration
Rev. 1.11 August 2008
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K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
4.0 Package Physical Dimension
Unit : mm
#54
#28
#1
#27
(1.50)
+0.075
0.125
22.22 ± 0.10
- 0.035
(10°)
0.10 MAX
[
(10°)
0.80TYP
0.075 MAX
[
(0.71)
[0.80 ± 0.08]
Detail A
Detail B
Detail B
0.25TYP
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
Detail A
(0° ∼ 8°)
+0.10
- 0.05
+0.10
0.35
- 0.05
0.30
54Pin TSOP(II) Package Dimension
Rev. 1.11 August 2008
5 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
5.0 Functional Block Diagram
LWE
Data Input Register
LDQM
Bank Select
32Mx4 / 16Mx8 / 8Mx16
32Mx4 / 16Mx8 / 8Mx16
32Mx4 / 16Mx8 / 8Mx16
32Mx4 / 16Mx8 / 8Mx16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
Timing Register
LDQM
L(U)DQM
CLK
CKE
CS
RAS
CAS
WE
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.11 August 2008
6 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
6.0 Pin Configuration (Top view)
x8
x4
x4
x8
x16
x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
VDD
DQ0
VDDQ
N.C
VDD
N.C
1
VSS
N.C
VSSQ
N.C
DQ3
VDDQ
N.C
N.C
VSSQ
N.C
DQ2
VDDQ
N.C
VSS
N.C/RFU
DQM
CLK
CKE
A12
A11
A9
VSS
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
2
DQ7
VSSQ
N.C
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
N.C
3
4
DQ1
VSSQ
N.C
DQ0
VSSQ
N.C
5
DQ6
VDDQ
N.C
6
7
DQ2
VDDQ
N.C
N.C
8
DQ5
VSSQ
N.C
VDDQ
N.C
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ3
VSSQ
N.C
DQ1
VSSQ
N.C
DQ4
VDDQ
N.C
VDDQ
DQ8
VDD
N.C
VDD
N.C
VSS
VSS
LDQM
WE
N.C/RFU N.C/RFU
WE
WE
DQM
CLK
CKE
A12
A11
A9
UDQM
CLK
CKE
A12
A11
A9
CAS
RAS
CS
CAS
RAS
CS
CAS
RAS
CS
BA0
BA0
BA1
BA0
BA1
BA1
A10/AP A10/AP A10/AP
A8
A8
A8
A0
A1
A0
A1
A0
A1
A7
A7
A7
A6
A6
A6
A2
A2
A2
A5
A5
A5
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
A3
A3
A3
A4
A4
A4
VDD
VDD
VDD
VSS
VSS
VSS
7.0 Pin Function Description
Pin
Name
System clock
Input Function
Active on the positive going edge to sample all inputs.
CLK
CS
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12,
Column address : (x4 : CA0 ~ CA9,CA11,CA12), (x8 : CA0 ~ CA9,CA11), (x16 : CA0 ~ CA9)
A0 ~ A12
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
CAS
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)
Power and ground for the input buffers and the core logic.
DQ0 ~ N
VDD/VSS
Data input/output
Power supply/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VDDQ/VSSQ
Data output power/ground
No connection
/reserved for future use
N.C/RFU
This pin is recommended to be left No Connection on the device.
Rev. 1.11 August 2008
7 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
8.0 Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
V
Voltage on VDD supply relative to VSS
Storage temperature
VDD, VDDQ
TSTG
PD
V
°C
W
Power dissipation
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
9.0 DC Operating Conditions
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
Min
3.0
Typ
3.3
Max
3.6
Unit
V
Note
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VIH
VIL
2.0
-0.3
2.4
-
3.0
VDD+0.3
V
V
1
0
-
0.8
-
2
VOH
VOL
ILI
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
Notes :
3. Any input 0V ≤ VIN ≤ VDDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
10.0 Capacitance
Pin
Symbol
CCLK
CIN
Min
2.5
2.5
2.5
4.0
Max
3.5
3.8
3.8
6.0
Unit
pF
pF
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15)
CADD
COUT
pF
pF
Rev. 1.11 August 2008
8 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
11.0 DC Characteristics (x4)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit
Note
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
85
mA
1
CKE ≤ VIL(max), tCC = 10ns
ICC2P
2
2
Precharge standby current in
power-down mode
mA
mA
mA
CKE & CLK ≤ VIL(max), tCC = ∞
ICC2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC2N
20
10
Precharge standby current in
non power-down mode
ICC2NS
CKE ≤ VIL(max), tCC = 10ns
6
6
ICC3P
Active standby current in
power-down mode
CKE & CLK ≤ VIL(max), tCC = ∞
ICC3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
IO = 0 mA
Page burst
tRC ≥ tRC(min)
ICC3N
30
25
90
mA
mA
mA
Active standby current in
non power-down mode
(One bank active)
ICC3NS
Operating current
(Burst mode)
Refresh current
ICC4
ICC5
1
200
6
3
mA
mA
mA
2
3
4
C
L
Self refresh current
ICC6
CKE ≤ 0.2V
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S510432D-UC
4. K4S510432D-UL
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
Rev. 1.11 August 2008
9 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
12.0 DC Characteristics (x8)
Version
Parameter
Symbol
Test Condition
Unit
Note
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
90
mA
1
CKE ≤ VIL(max), tCC = 10ns
ICC2P
2
2
Precharge standby current in
power-down mode
mA
mA
mA
CKE & CLK ≤ VIL(max), tCC = ∞
ICC2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC2N
20
10
Precharge standby current in
non power-down mode
ICC2NS
CKE ≤ VIL(max), tCC = 10ns
6
6
ICC3P
Active standby current in
power-down mode
CKE & CLK ≤ VIL(max), tCC = ∞
ICC3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤VIL(max), tCC = ∞
Input signals are stable
ICC3N
30
25
mA
mA
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
100
mA
1
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
200
6
3
mA
mA
mA
2
3
4
C
L
Self refresh current
CKE ≤ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S510832D-UC
4. K4S510832D-UL
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
Rev. 1.11 August 2008
10 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
13.0 DC Characteristics (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit
Note
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
100
mA
1
CKE ≤ VIL(max), tCC = 10ns
ICC2P
2
2
Precharge standby current in
power-down mode
mA
mA
mA
CKE & CLK ≤ VIL(max), tCC = ∞
ICC2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC2N
20
10
Precharge standby current in
non power-down mode
ICC2NS
CKE ≤ VIL(max), tCC = 10ns
6
6
ICC3P
Active standby current in
power-down mode
CKE & CLK ≤ VIL(max), tCC = ∞
ICC3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3N
30
25
mA
mA
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
130
mA
1
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
200
6
3
mA
mA
mA
2
3
4
C
L
Self refresh current
CKE ≤ 0.2V
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S511632D-UC
4. K4S511632D-UL
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
Rev. 1.11 August 2008
11 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
14.0 AC Operating Test Conditions
Parameter
Value
Unit
AC input levels (VIH/VIL)
2.4/0.4
V
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
1.4
tr/tf = 1/1
1.4
V
ns
V
See Fig. 2
3.3V
VTT = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
Z0 = 50Ω
Output
Output
VOL (DC) = 0.4V, IOL = 2mA
50pF
50pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
(AC operating conditions unless otherwise noted)
15.0 Operating AC Parameter
Version
Parameter
Symbol
Unit
Note
75
Row active to row active delay
RAS to CAS delay
Row precharge time
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
15
20
20
45
100
65
2
ns
ns
ns
ns
us
ns
CLK
ns
CLK
CLK
1
1
1
1
Row active time
Row cycle time
1
2, 5
5
2
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2 CLK + tRP
1
1
Col. address to col. address delay
tCCD(min)
CAS latency = 3
CAS latency = 2
1
2
1
CLK
3
Number of valid output data
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
6. tRC = tRFC, tRDL = tWR
Rev. 1.11 August 2008
12 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
16.0 AC Characteristics
(AC operating conditions unless otherwise noted)
75
Parameter
Symbol
Unit
ns
Note
1
Min
7.5
10
Max
CAS latency=3
CLK cycle time
tCC
tSAC
tOH
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
5.4
6
CLK to valid
output delay
ns
1, 2
2
3
3
Output data
hold time
ns
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
tCH
tCL
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
tSH
tSLZ
CAS latency=3
CAS latency=2
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. tSS applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time.
tSH applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time.
17.0 DQ Buffer Output Drive Characteristics
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Measure in linear
region : 1.2V ~ 1.8V
Output rise time
trh
1.37
4.37
Volts/ns
3
Measure in linear
Output fall time
Output rise time
Output fall time
tfh
trh
tfh
1.30
2.8
3.8
5.6
5.0
Volts/ns
Volts/ns
Volts/ns
3
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
3.9
2.9
1,2
1,2
Measure in linear
region : 1.2V ~ 1.8V
2.0
Notes :
1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS
.
Rev. 1.11 August 2008
13 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
18.0 IBIS Specification
IOH Characteristics (Pull-up)
133MHz Pull-up
1.5
0
0.5
1
2
2.5
3
3.5
0
-100
-200
-300
-400
-500
-600
133MHz
133Mhz
Max
Voltage
Min
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
I (mA)
I (mA)
-2.4
-27.3
-74.1
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
Voltage
IOH Min (133MHz)
IOH Max (133MHz)
133MHz Pull-down
IOL Characteristics (Pull-down)
250
200
150
100
50
133MHz
133MHz
Max
Voltage
Min
(V)
I (mA)
0.0
I (mA)
0.0
0.0
0.4
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
70.2
0.65
0.85
1.0
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
1.4
1.5
1.65
1.8
1.95
3.0
3.45
0
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (133MHz)
IOL Max (133MHz)
Rev. 1.11 August 2008
14 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
Minimum VDD clamp current
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
I (mA)
0.0
20
15
10
5
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
-2 -1
VSS Clamp @ CLK, CKE, CS, DQM & DQ
-3
0
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0
-10
-20
-30
-40
-50
-60
0.0
0.0
0.0
Voltage
I (mA)
Rev. 1.11 August 2008
15 of 16
K4S510432D
K4S510832D
K4S511632D
Synchronous DRAM
19.0 Simplified Truth Table
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
A0 ~ A9
Command
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
Note
A11, A12
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
L
L
L
X
X
OP code
X
1,2
3
3
3
3
H
Entry
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
Exit
L
H
H
H
X
X
X
X
X
X
Bank active & row addr.
Read &
column address
V
V
Row address
L
H
L
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
4
4,5
4
4,5
6
Column
L
H
L
H
address
Write &
column address
Column
address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
Burst stop
Precharge
X
Bank selection
All banks
V
X
L
H
X
H
L
X
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No operation command
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.11 August 2008
16 of 16
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