K4S560832E-NL75_技术文档

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

256Mb E-die SDRAM Specification

54pin sTSOP-II

Revision 1.1

February. 2004

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

Revision History

Revision 1.0 (August. 2003)

- First release.

Revision 1.1 (February. 2004)

- Deleted x16 for data book.

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks SDRAM

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock.

• Burst read single-bit write operation

• DQM (x4,x8)

• Auto & self refresh

• 64ms refresh period (8K Cycle)

GENERAL DESCRIPTION

The K4S560432E / K4S560832E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by

4bits / 4 x 8,388,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows pre-

cise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, pro-

grammable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high

performance memory system applications.

Ordering Information

Part No.

Orgainization

64M x 4

Max Freq.

133MHz

Interface

LVTTL

Package

K4S560432E-NC(L)75

K4S560832E-NC(L)75

54pin sTSOP

32M x 8

LVTTL

Organization

Row Address

Column Address

64Mx4

32Mx8

A0~A12

A0-A9, A11

A0-A9

Row & Column address configuration

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

Package Physical Dimension

54pin sTSOP(II)-300

Units : Millimeters

(2-R 0.30)

(2-R 0.15)

#54

#28

(∅ 2.00 Dp0~0.05 BTM)

(1.00)

(14°)

#1

#27

+0.075

-0.035

0.125

14.40MAX

(14.20)

14.00±0.10

(14°)

0.10 MAX

+0.075

-0.035

0.25TYP

(0.50)

0.50TYP

0.20

0.50±0.05

(14°)

[

]

0.07 MAX

NOTE

1. (

0×~8×

) IS REFERENCE

2. [

] IS ASS’Y OUT QUALITY

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

FUNCTIONAL BLOCK DIAGRAM

LWE

Data Input Register

LDQM

Bank Select

16M x 4 / 8M x 8 / 4M x 16

DQi

CLK

ADD

Column Decoder

Latency & Burst Length

LCKE

Programming Register

LWCBR

LRAS

LCBR

LWE

LCAS

LDQM

Timing Register

CLK

CKE

CS

RAS

CAS

WE

L(U)DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

PIN CONFIGURATION (Top view)

x4

VSS

NC

x8

VSS

DQ7

VSSQ

NC

x8 x4

VDD

DQ0

VDDQ

NC

VDD

NC

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

2

VSSQ

NC

VDDQ

NC

3

4

DQ3

VDDQ

NC

DQ6

VDDQ

NC

DQ1

VSSQ

NC

DQ0

VSSQ

NC

5

6

7

NC

DQ5

VSSQ

NC

DQ2

VDDQ

NC

8

VSSQ

NC

VDDQ

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

54 PIN sTSOP(II)

DQ2

VDDQ

NC

DQ4

VDDQ

NC

DQ3

VSSQ

NC

DQ1

VSSQ

NC

300mil x 551mil

(7.62mm x 14.00mm)

(0.5 mm pin pitch)

VSS

NC

VSS

NC

VDD

NC

VDD

NC

DQM

CLK

CKE

A12

A11

A9

DQM

CLK

CKE

A12

A11

A9

WE

CAS

RAS

CS

CAS

RAS

CS

BA0

BA1

AP/A10

A0

BA0

BA1

AP/A10

A0

A8

22

23

A7

A6

A1

24

25

26

27

A5

A2

A4

A3

VSS

VDD

PIN FUNCTION DESCRIPTION

Name

System clock

Input Function

Active on the positive going edge to sample all inputs.

CLK

CS

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE

Clock enable

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12,

A0 ~ A12

Address

Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9)

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

BA0 ~ BA1

RAS

Bank select address

Row address strobe

Column address strobe

Write enable

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

WE

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQM

Data input/output mask

Data inputs/outputs are multiplexed on the same pins.

(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7)

DQ0 ~ N

Data input/output

VDD/VSS

VDDQ/VSSQ

Power supply/ground

Data output power/ground

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

No connection

/reserved for future use

N.C/RFU

This pin is recommended to be left No Connection on the device.

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

1

Unit

V

°C

W

Power dissipation

PD

Short circuit current

IOS

50

mA

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

2.0

-0.3

2.4

-

Typ

Max

3.6

Unit

V

Note

3.3

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

3.0

VDD+0.3

0.8

V

1

VIL

0

-

V

2

VOH

-

V

IOH = -2mA

IOL = 2mA

3

VOL

-

0.4

V

ILI

-10

-

10

uA

1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.

Notes :

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Symbol

CCLK

CIN

Min

2.5

4.0

Max

3.5

3.8

6.0

Unit

pF

Note

Clock

RAS, CAS, WE, CS, CKE, DQM

Address

pF

CADD

COUT

pF

(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7)

pF

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

DC CHARACTERISTICS (x4, x8)

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Version

75

Parameter

Symbol

Test Condition

Unit

mA

Note

Burst length = 1

tRC ≥ tRC(min)

IO = 0 mA

Operating current

(One bank active)

ICC1

80

1

ICC2P CKE ≤ VIL(max), tCC = 10ns

2

Precharge standby current in

power-down mode

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC2N

20

10

Input signals are changed one time during 20ns

Precharge standby current in

non power-down mode

mA

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

ICC2NS

Input signals are stable

ICC3P CKE ≤ VIL(max), tCC = 10ns

6

Active standby current in

power-down mode

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC3N

25

mA

Active standby current in

non power-down mode

(One bank active)

Input signals are changed one time during 20ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

ICC3NS

Input signals are stable

IO = 0 mA

Page burst

4banks Activated.

tCCD = 2CLKs

Operating current

(Burst mode)

ICC4

100

mA

1

Refresh current

ICC5

ICC6

tRC ≥ tRC(min)

CKE ≤ 0.2V

180

3

mA

2

3

4

C

L

Self refresh current

1.5

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S5604(08)32E-NC75

4. K4S5604(08)32E-NL75

5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter

AC input levels (Vih/Vil)

Value

2.4/0.4

1.4

Unit

V

Input timing measurement reference level

Input rise and fall time

V

tr/tf = 1/1

1.4

ns

V

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200Ω

50Ω

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Z0 = 50Ω

Output

50pF

870Ω

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

75

15

20

45

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

ns

1

Row precharge time

ns

tRAS(min)

tRAS(max)

tRC(min)

ns

Row active time

us

Row cycle time

65

ns

1

2

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

tRDL(min)

tDAL(min)

tCDL(min)

tBDL(min)

tCCD(min)

2

CLK

-

2 CLK + tRP

1

2

1

CLK

2

3

Col. address to col. address delay

CAS latency=3

CAS latency=2

Number of valid output data

ea

4

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

75

Parameter

Symbol

tCC

Unit

ns

Note

1

Min

7.5

10

Max

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

CLK cycle time

1000

5.4

6

CLK to valid

output delay

tSAC

ns

1,2

2

3

Output data

hold time

tOH

ns

3

CLK high pulse width

CLK low pulse width

Input setup time

tCH

tCL

2.5

1.5

0.8

1

ns

3

2

tSS

tSH

tSLZ

Input hold time

CLK to output in Low-Z

CAS latency=3

CAS latency=2

5.4

6

CLK to output in Hi-Z

tSHZ

ns

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Notes

Measure in linear

region : 1.2V ~ 1.8V

Output rise time

trh

1.37

4.37

Volts/ns

3

Measure in linear

region : 1.2V ~ 1.8V

Output fall time

Output rise time

Output fall time

tfh

trh

tfh

1.30

2.8

3.8

5.6

5.0

3

Measure in linear

region : 1.2V ~ 1.8V

3.9

2.9

1,2

Measure in linear

region : 1.2V ~ 1.8V

2.0

Notes :

1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.

2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.

3. Measured into 50pF only, use these values to characterize to.

4. All measurements done with respect to VSS.

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

66MHz and 100MHz/133MHz Pull-up

0.5 1.5 2.5

IBIS SPECIFICATION

0

1

2

3

3.5

IOH Characteristics (Pull-up)

0

-100

-200

-300

-400

-500

-600

100MHz

133MHz

Min

100MHz

133MHz

Max

I (mA)

-2.4

66MHz

Min

Voltage

(V)

3.45

3.3

3.0

2.6

2.4

2.0

1.8

1.65

1.5

1.4

1.0

0.0

I (mA)

-27.3

-74.1

0.0

-21.1

-34.1

-58.7

-67.3

-73.0

-77.9

-80.8

-88.6

-93.0

-0.7

-7.5

-129.2

-153.3

-197.0

-226.2

-248.0

-269.7

-284.3

-344.5

-502.4

-13.3

-27.5

-35.5

-41.1

-47.9

-52.4

-72.5

-93.0

Voltage

IOH Min (100MHz)

I^OHMin (66MHz)

I^OHMax (66 and 100MHz)

66MHz and 100MHz/133MHz Pull-down

IOL Characteristics (Pull-down)

250

200

150

100

50

100MHz

133MHz

Min

100MHz

133MHz

Max

66MHz

Min

Voltage

(V)

0.0

I (mA)

0.0

I (mA)

0.0

I (mA)

0.0

0.4

27.5

70.2

17.7

26.9

33.3

37.6

46.6

48.0

49.5

50.7

51.5

54.2

54.9

0.65

0.85

1.0

1.4

1.5

1.65

1.8

1.95

3.0

41.8

51.6

58.0

70.7

72.9

75.4

77.0

77.6

107.5

133.8

151.2

187.7

194.4

202.5

208.6

212.0

219.6

222.6

80.3

81.4

0

3.45

0

0.5

1

1.5

2

2.5

3

3.5

Voltage

IOL Min (100MHz)

I^OLMin (66MHz)

I^OLMax (100MHz)

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

Minimum VDD clamp current

(Referenced to VDD)

VDD Clamp @ CLK, CKE, CS, DQM & DQ

VDD (V)

0.0

0.2

0.4

0.6

0.7

0.8

0.9

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

I (mA)

0.0

0.23

1.34

3.02

5.06

7.35

9.83

12.48

15.30

18.31

20

15

10

5

0

1

2

3

Voltage

I (mA)

Minimum VSS clamp current

-2 -1

VSS Clamp @ CLK, CKE, CS, DQM & DQ

-3

0

VSS (V)

-2.6

-2.4

-2.2

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0

-0.9

-0.8

-0.7

-0.6

-0.4

-0.2

0.0

I (mA)

-57.23

-45.77

-38.26

-31.22

-24.58

-18.37

-12.56

-7.57

-3.37

-1.75

-0.58

-0.05

0.0

0

-10

-20

-30

-40

-50

-60

0.0

Voltage

I (mA)

Rev. 1.1 February, 2004

CMOS SDRAM

SDRAM 256Mb E-die (x4, x8)

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don't care, H=Logic high, L=Logic low)

A0 ~ A9

A11, A12

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM BA0,1

A10/AP

Note

Command

Mode register set

Register

Refresh

H

X

H

L

X

OP code

1,2

3

Auto refresh

H

L

H

X

Entry

Exit

3

Self

refresh

L

H

L

H

X

L

H

X

H

X

H

3

L

H

X

3

Bank active & row addr.

X

V

Row address

Read &

column address

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

L

H

L

4

4,5

4

Column

address

L

H

L

H

Column

address

Write &

column address

H

X

L

H

L

H

L

X

V

H

4,5

6

Burst stop

Precharge

X

Bank selection

All banks

V

X

L

X

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

Exit

H

L

H

L

X

Clock suspend or

active power down

X

H

L

Entry

H

Precharge power down mode

H

L

Exit

L

H

X

V

X

DQM

X

7

H

L

X

H

X

H

No operation command

Notes :

1. OP Code : Operand code

A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 1.1 February, 2004


型号：	K4S560832E-NL75
厂家：	SAMSUNG
描述：	256Mb E-die SDRAM Specification 54pin sTSOP-II 256Mb的电子芯片SDRAM规格54pin sTSOP -II 电子动态存储器
文件：	总13页 (文件大小：184K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4S560832E-NL75 [SAMSUNG]

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