K4S560832N-LC75 [SAMSUNG]
Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, TSOP2-54;
| 型号： | K4S560832N-LC75 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, TSOP2-54 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总18页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev. 1.0, Apr. 2010
K4S560432N
K4S560832N
K4S561632N
256Mb N-die SDRAM
54TSOP(II) with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
- 1 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
Revision History
Revision No.
History
Draft Date
Remark
Editor
1.0
- First Spec. Release
Apr. 2010
-
S.H.Kim
- 2 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
Table Of Contents
256Mb N-die SDRAM
1. KEY FEATURES...........................................................................................................................................................4
2. GENERAL DESCRIPTION ...........................................................................................................................................4
3. ORDERING INFORMATION ........................................................................................................................................4
4. PACKAGE PHYSICAL DIMENSION ............................................................................................................................5
5. FUNCTIONAL BLOCK DIAGRAM................................................................................................................................6
6. PIN CONFIGURATION (TOP VIEW)............................................................................................................................7
7. INPUT/OUTPUT FUNCTION DESCRIPTION ..............................................................................................................7
8. ABSOLUTE MAXIMUM RATINGS ...............................................................................................................................8
9. DC OPERATING CONDITIONS...................................................................................................................................8
10. CAPACITANCE ..........................................................................................................................................................8
11. DC CHARACTERISTICS (x4/x8)................................................................................................................................9
12. DC CHARACTERISTICS (x16)...................................................................................................................................10
13. AC OPERATING TEST CONDITIONS.......................................................................................................................11
14. OPERATING AC PARAMETER .................................................................................................................................12
15. AC CHARACTERISTICS............................................................................................................................................13
16. DQ BUFFER OUTPUT DRIVE CHARACTERISTICS.................................................................................................13
17. IBIS SPECIFICATION.................................................................................................................................................14
18. SIMPLIFIED TRUTH TABLE ......................................................................................................................................18
- 3 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
1. KEY FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• Lead-Free & Halogen-Free Package
• RoHS compliant
2. GENERAL DESCRIPTION
The K4S560432N / K4S560832N / K4S561632N is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4
bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous
design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, pro-
grammable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory sys-
tem applications.
3. ORDERING INFORMATION
Part No.
Orgainization
Max Freq.
Interface
Package
K4S560432N-LC/L75
K4S560832N-LC/L75
K4S561632N-LC/L60
K4S561632N-LC/L75
133MHz (CL=3)
133MHz (CL=3)
166MHz (CL=3)
133MHz (CL=3)
64M x 4
32M x 8
54pin TSOP(II)
Lead-Free & Halogen-Free
LVTTL
16M x 16
[ Table 1 ] Row & Column address configuration
Organization
64Mx4
Row Address
A0~A12
Column Address
A0-A9, A11
A0-A9
32Mx8
A0~A12
16Mx16
A0~A12
A0-A8
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K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
4. PACKAGE PHYSICAL DIMENSION
Unit : mm
#54
#28
#1
#27
(1.50)
+0.075
- 0.035
0.125
22.22 ± 0.10
(10°)
0.10 MAX
[
(10°)
0.80TYP
[0.80 ± 0.08]
0.075 MAX
[
(0.71)
Detail A
Detail B
Detail B
0.25TYP
NOTE :
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
Detail A
(0° ∼ 8°)
+0.10
- 0.05
+0.10
0.30
0.35
- 0.05
Figure 1. 54Pin TSOP(II) Package Dimension
- 5 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
5. FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
- 6 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
6. PIN CONFIGURATION (TOP VIEW)
x8
x4
x4
x8
x16
x16
VDD
VDD
VDD
1
2
3
4
5
6
7
8
VSS
VSS
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
N.C
VDDQ
N.C
DQ0
VSSQ
N.C
N.C
VDDQ
N.C
DQ1
VSSQ
N.C
VDD
N.C
WE 16
CAS 17
RAS 18
CS 19
BA0 20
BA1 21
N.C
VSSQ
N.C
DQ3
VDDQ
N.C
N.C
VSSQ
N.C
DQ2
VDDQ
N.C
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
9
10
11
12
13
14
15
VDDQ
DQ8
VSS
VSS
VSS
N.C/RFU N.C/RFU N.C/RFU
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A10/AP A10/AP A10/AP
22
A0
A1
A2
A3
VDD
A0
A1
A2
A3
VDD
A0 23
A1 24
A2 25
A3 26
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
A4
VSS
A4
VSS
A4
VSS
VDD
27
7. INPUT/OUTPUT FUNCTION DESCRIPTION
Pin
Name
Description
CLK
CS
System clock
Chip select
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12,
A0 ~ A12
Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
Data input/output
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)
DQ0 ~ N
V
DD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
VDDQ/VSSQ
N.C/RFU
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise immunity.
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
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K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
8. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to VSS
Storage temperature
VDD, VDDQ
TSTG
PD
-1.0 ~ 4.6
V
°C
W
-55 ~ +150
Power dissipation
1
Short circuit current
IOS
50
mA
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
9. DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
NOTE
VDD, VDDQ
3.0
3.3
3.6
V
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VIH
VIL
2.0
-0.3
2.4
-
3.0
VDD+0.3
V
V
1
0
-
0.8
-
2
VOH
VOL
ILI
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
NOTE :
1. V (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
IH
2. V (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
IL
3. Any input 0V ≤ V ≤ V
.
IN
DDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
10. CAPACITANCE
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Symbol
CCLK
CIN
Min
2.5
2.5
2.5
4.0
Max
Unit
pF
Clock
3.5
3.8
3.8
6.0
RAS, CAS, WE, CS, CKE, DQM
Address
pF
CADD
COUT
pF
(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15)
pF
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K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
11. DC CHARACTERISTICS (x4/x8)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
75
Parameter
Symbol
Test Condition
Unit
NOTE
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
40
mA
1
CKE ≤ VIL(max), tCC = 10ns
ICC2P
2
2
Precharge standby current in
power-down mode
mA
mA
mA
CKE & CLK ≤ VIL(max), tCC = ∞
ICC2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
Precharge standby current in non
power-down mode
ICC2N
15
CKE ≤ VIL(max), tCC = 10ns
ICC3P
5
5
Active standby current in power-
down mode
CKE & CLK ≤ VIL(max), tCC = ∞
ICC3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3N
20
20
mA
mA
Active standby current in
non power-down mode
(One bank active)
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks Activated
tCCD = 2CLKs
ICC4
40
mA
1
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
70
3
mA
mA
mA
2
3
4
C
Self refresh current
CKE ≤ 0.2V
L
1.5
NOTE :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S5604(08)32N-LC
4. K4S5604(08)32N-LL
5. Unless otherwise noticed, input swing level is CMOS(V /V =V
/V
).
IH IL
DDQ SSQ
- 9 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
12. DC CHARACTERISTICS (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit
NOTE
60
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
45
45
mA
1
CKE ≤ VIL(max), tCC = 10ns
ICC2P
2
2
2
2
Precharge standby current in
power-down mode
mA
mA
mA
CKE & CLK ≤ VIL(max), tCC = ∞
ICC2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
Precharge standby current in non
power-down mode
ICC2N
15
15
CKE ≤ VIL(max), tCC = 10ns
ICC3P
5
5
5
5
Active standby current in power-
down mode
CKE & CLK ≤ VIL(max), tCC = ∞
ICC3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3N
25
20
25
20
mA
mA
Active standby current in
non power-down mode
(One bank active)
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks Activated
tCCD = 2CLKs
ICC4
50
50
mA
1
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
80
3
80
3
mA
mA
mA
2
3
4
C
Self refresh current
CKE ≤ 0.2V
L
1.5
1.5
NOTE :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S561632N-LC
4. K4S561632N-LL
5. Unless otherwise noticed, input swing level is CMOS(V /V =V
/V
).
IH IL
DDQ SSQ
- 10 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
13. AC OPERATING TEST CONDITIONS
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Figure 3
3.3V
1200Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
50pF
870Ω
Figure 2. DC output load circuit
Vtt = 1.4V
50Ω
Output
Z0 = 50Ω
50pF
Figure 3. AC output load circuit
- 11 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
14. OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
60
Unit
NOTE
75
15
20
20
45
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
12
18
18
42
ns
ns
1
1
1
1
Row precharge time
ns
tRAS(min)
tRAS(max)
tRC(min)
ns
Row active time
100
us
Row cycle time
60
65
ns
1
2,5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + tRP
1
1
1
2
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
NOTE : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
6. t = t
, t
= t
RC
RFC RDL WR
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K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
15. AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
60
75
Parameter
CAS latency=3
Symbol
tCC
Unit
ns
NOTE
Min
Max
Min
Max
6
-
7.5
10
CLK cycle time
1000
1000
1
1,2
2
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
5
-
5.4
6
CLK to valid
output delay
tSAC
tOH
ns
2.5
-
3
Output data
hold time
ns
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
1
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
1
CAS latency=3
CAS latency=2
5
-
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
NOTE : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. tSS applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time.
tSH applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time.
16. DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
NOTE
Measure in linear
region : 1.2V ~ 1.8V
Output rise time
trh
1.37
4.37
Volts/ns
3
Measure in linear
region : 1.2V ~ 1.8V
Output fall time
Output rise time
Output fall time
tfh
trh
tfh
1.30
2.8
3.8
5.6
5.0
Volts/ns
Volts/ns
Volts/ns
3
Measure in linear
region : 1.2V ~ 1.8V
3.9
2.9
1,2
1,2
Measure in linear
region : 1.2V ~ 1.8V
2.0
NOTE : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
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K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
17. IBIS SPECIFICATION
[ Table 2 ] IOH Characteristics (Pull-up)
Voltage
166MHz
133MHz
Min
166MHz
133MHz
Max
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
I (mA)
I (mA)
-2.4
-27.3
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
-74.1
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
0
0.5
1
1.5
2
2.5
3
3.5
0
-100
-200
-300
-400
-500
-600
Voltage
IOH Min (166MHz/133MHz)
IOH Max (166MHz/133MHz)
Figure 4. 166MHz/133MHz Pull-up
- 14 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
[ Table 3 ] IOL Characteristics (Pull-down)
166MHz
133MHz
Min
166MHz
133MHz
Max
Voltage
(V)
0.0
I (mA)
0.0
I (mA)
0.0
0.4
27.5
70.2
0.65
0.85
1.0
1.4
1.5
1.65
1.8
1.95
3.0
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
80.3
81.4
3.45
250
200
150
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (166MHz/133MHz)
IOL Max (166MHz/133MHz)
Figure 5. 166MHz/133MHz Pull-down
- 15 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
[ Table 4 ] VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
I (mA)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
20
15
10
5
0
0
1
2
3
Voltage
I (mA)
Figure 6. Minimum VDD clamp current (Referenced to VDD
)
- 16 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
[ Table 5 ] VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V)
I (mA)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0.0
0.0
0.0
-3
-2
-1
0
0
-10
-20
-30
-40
-50
-60
Voltage
I (mA)
Figure 7. Minimum VSS clamp current
- 17 -
K4S560432N
K4S560832N
K4S561632N
Rev. 1.0
datasheet
SDRAM
18. SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
A0 ~ A9
A11, A12
Command
Mode register set
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1 A10/AP
NOTE
Register
Refresh
H
H
X
H
L
L
L
L
L
X
X
OP code
1,2
3
Auto refresh
L
L
L
H
X
X
Entry
Exit
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
L
H
H
H
X
X
X
X
X
3
Bank active & row addr.
V
V
Row address
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
Column
address
L
L
H
H
L
L
H
L
4,5
4
Write &
column address
Column
address
H
X
X
V
H
4,5
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
6
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
X
H
L
Entry
H
Precharge power down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No operation command
NOTE :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
- 18 -
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