K4S561632J-UC60 [SAMSUNG]
Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54,;
| 型号： | K4S561632J-UC60 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
256Mb J-die SDRAM Specification
54 TSOP-II
with Lead-Free & Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.22 August 2008
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K4S560432J
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Synchronous DRAM
Table of Contents
1.0 Features....................................................................................................................................... 4
2.0 General Description ................................................................................................................... 4
3.0 Ordering Information.................................................................................................................. 4
4.0 Package Physical Dimension ................................................................................................... 5
5.0 Functional Block Diagram......................................................................................................... 6
6.0 Pin Configuration (Top view)..................................................................................................... 7
7.0 Pin Function Description ........................................................................................................... 7
8.0 Absolute Maximum Ratings........................................................................................................8
9.0 DC Operating Conditions........................................................................................................... 8
10.0 Capacitance............................................................................................................................... 8
11.0 DC Characteristics (x4, x8) ......................................................................................................9
12.0 DC Characteristics (x16) ........................................................................................................10
13.0 AC Operating Test Conditions ...............................................................................................11
14.0 Operating AC Parameter ........................................................................................................11
15.0 AC Characteristics ..................................................................................................................12
16.0 DQ Buffer Output Drive Characteristics ...............................................................................12
17.0 IBIS Specification .....................................................................................................................13
18.0 Simplified Truth Table ............................................................................................................15
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Synchronous DRAM
Revision History
Revision
Month
Year
History
1.0
June
2007
- Release 1.0 version SPEC
- Changed IDD current SPEC
1.1
October
2007
- Revised typo of package dimension
- Added the comment of Halogen-free supporting
- Added 200Mhz speed
- Added Package pin out lead width
- Added 200MHz current SPEC
1.2
January
March
2008
2008
2008
1.21
1.22
August
- Corrected font format
Rev. 1.22 August 2008
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K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
1.0 Features
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• Lead-Free & Halogen-Free Package
• RoHS compliant
2.0 General Description
The K4S560432J / K4S560832J / K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x
16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
3.0 Ordering Information
Part No.
Orgainization
Max Freq.
Interface
Package
K4S560432J-U*1C/L75
K4S560832J-UC/L75
K4S561632J-UC/L50
K4S561632J-UC/L60
K4S561632J-UC/L75
64M x 4
133MHz (CL=3)
32M x 8
133MHz (CL=3)
200MHz (CL=3)
166MHz (CL=3)
133MHz (CL=3)
54pin TSOP(II)
LVTTL
Lead-Free & Halogen-Free*1
16M x 16
Note 1 : 256Mb J-die SDR DRAMs support Lead-Free & Halogen-Free package with Lead-Free package code(-U).
Organization
64Mx4
Row Address
A0~A12
Column Address
A0-A9, A11
A0-A9
32Mx8
A0~A12
16Mx16
A0~A12
A0-A8
Row & Column address configuration
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4.0 Package Physical Dimension
Unit : mm
#54
#28
#1
#27
(1.50)
+0.075
0.125
22.22 ± 0.10
- 0.035
(10°)
0.10 MAX
[
(10°)
0.80TYP
0.075 MAX
[
(0.71)
[0.80 ± 0.08]
Detail A
Detail B
Detail B
0.25TYP
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
Detail A
(0° ∼ 8°)
+0.10
- 0.05
+0.10
0.35
- 0.05
0.30
54Pin TSOP(II) Package Dimension
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5.0 Functional Block Diagram
LWE
Data Input Register
LDQM
Bank Select
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
Timing Register
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
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6.0 Pin Configuration (Top view)
x8
x4
x4
x8
x16
x16
VDD
VDD
VDD
1
2
3
4
5
6
7
8
9
VSS
VSS
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQ0
VDDQ
N.C
N.C
VDDQ
N.C
N.C
DQ7
VSSQ
N.C
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VSSQ
N.C
DQ1
VSSQ
N.C
DQ0
VSSQ
N.C
DQ3
VDDQ
N.C
DQ6
VDDQ
N.C
DQ2
VDDQ
N.C
N.C
N.C
DQ5
VSSQ
N.C
VDDQ
VSSQ
N.C
N.C 10
DQ3
VSSQ
N.C
DQ1
11
12
DQ2
VDDQ
N.C
DQ4
VDDQ
N.C
VSSQ
VDDQ
DQ8
N.C 13
VDD
N.C
VDD
14
VSS
VSS
VSS
LDQM
WE
N.C 15
WE 16
CAS 17
RAS 18
CS 19
N.C/RFU N.C/RFU N.C/RFU
WE
DQM
CLK
CKE
A12
A11
A9
DQM
CLK
CKE
A12
A11
A9
UDQM
CLK
CKE
A12
A11
A9
CAS
RAS
CS
CAS
RAS
CS
BA0
BA0
BA1
BA0 20
BA1 21
BA1
A10/AP A10/AP A10/AP 22
A8
A8
A8
A0
A1
A0
A1
A0 23
A1 24
A2 25
A3 26
A7
A7
A7
A6
A6
A6
A2
A2
A5
A5
A5
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
A3
A3
A4
A4
A4
VDD
VDD
VDD
27
VSS
VSS
VSS
7.0 Pin Function Description
Pin
Name
System clock
Input Function
Active on the positive going edge to sample all inputs.
CLK
CS
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12,
Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
A0 ~ A12
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
CAS
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)
DQ0 ~ N
Data input/output
VDD/VSS
VDDQ/VSSQ
Power supply/ground
Data output power/ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
No connection
/reserved for future use
N.C/RFU
This pin is recommended to be left No Connection on the device.
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Synchronous DRAM
8.0 Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
V
Voltage on VDD supply relative to VSS
Storage temperature
VDD, VDDQ
TSTG
PD
V
°C
W
Power dissipation
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
9.0 DC Operating Conditions
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
Min
3.0
Typ
3.3
Max
3.6
Unit
V
Note
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VIH
VIL
2.0
-0.3
2.4
-
3.0
VDD+0.3
V
V
1
0
-
0.8
-
2
VOH
VOL
ILI
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
Notes :
3. Any input 0V ≤ VIN ≤ VDDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
10.0 Capacitance
Pin
Symbol
CCLK
CIN
Min
2.5
2.5
2.5
4.0
Max
3.5
3.8
3.8
6.0
Unit
pF
pF
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15)
CADD
COUT
pF
pF
Rev. 1.22 August 2008
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Synchronous DRAM
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
11.0 DC Characteristics (x4, x8)
Version
Parameter
Symbol
Test Condition
Unit
Note
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
70
mA
1
CKE ≤ VIL(max), tCC = 10ns
ICC2P
2
2
Precharge standby current in
power-down mode
mA
mA
mA
CKE & CLK ≤ VIL(max), tCC = ∞
ICC2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC2N
15
10
Precharge standby current in
non power-down mode
ICC2NS
CKE ≤ VIL(max), tCC = 10ns
ICC3P
5
5
Active standby current in
power-down mode
CKE & CLK ≤ VIL(max), tCC = ∞
ICC3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3N
28
20
mA
mA
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Page burst
Operating current
(Burst mode)
ICC4
110
mA
1
4banks Activated.
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
160
3
1.5
mA
mA
mA
2
3
4
C
L
Self refresh current
CKE ≤ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S5604(08)32J-UC
4. K4S5604(08)32J-UL
5. Unless otherwise noticed, input swing level is CMOS(VIH /VIL=VDDQ/VSSQ).
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Synchronous DRAM
12.0 DC Characteristics (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit Note
50
60
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
110
90
70
mA
1
ICC2P CKE ≤ VIL(max), tCC = 10ns
2
2
Precharge standby current in
power-down mode
mA
mA
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N
15
10
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC2NS
ICC3P CKE ≤ VIL(max), tCC = 10ns
5
5
Active standby current in
power-down mode
mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC3N
28
20
mA
mA
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC3NS
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
140
200
120
110
160
mA
1
4banks Activated.
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
180
3
1.5
mA
mA
mA
2
3
4
C
L
Self refresh current
CKE ≤ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S561632J-UC
4. K4S561632J-UL
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
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Synchronous DRAM
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
13.0 AC Operating Test Conditions
Parameter
Value
Unit
AC input levels (VIH/VIL)
2.4/0.4
V
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
1.4
tr/tf = 1/1
1.4
V
ns
V
See Fig. 2
3.3V
VTT = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
Z0 = 50Ω
Output
Output
VOL (DC) = 0.4V, IOL = 2mA
50pF
50pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
(AC operating conditions unless otherwise noted)
14.0 Operating AC Parameter
Version
50 (x16 only) 60 (x16 only)
Parameter
Symbol
Unit
Note
75
15
20
20
45
Row active to row active delay
RAS to CAS delay
Row precharge time
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
10
15
15
12
18
18
42
ns
ns
ns
1
1
1
1
37.5
ns
Row active time
100
us
Row cycle time
55
60
2
65
ns
CLK
-
1
2,5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2 CLK + tRP
1
1
1
2
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
6. tRC =tRFC, tRDL = tWR.
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15.0 AC Characteristics
(AC operating conditions unless otherwise noted)
50 (x16 only)
60(x16 only)
75
Parameter
Symbol
tCC
Unit
ns
Note
1
Min
Max
Min
6
-
Max
Min
7.5
10
Max
CAS latency=3
CLK cycle time
5
-
1000
1000
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
-
-
2
-
4.5
-
-
-
5
-
5.4
6
CLK to valid
output delay
tSAC
tOH
ns
1,2
2
2.5
-
3
3
Output data
hold time
ns
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
tCH
tCL
tSS
tSH
tSLZ
2
2
1.5
1
1
-
-
-
-
-
-
2.5
2.5
1.5
1
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
1
CAS latency=3
CAS latency=2
4.5
-
5
-
5.4
6
CLK to output in Hi-Z
tSHZ
ns
-
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. tSS applies for address setup time, clock enable setup time. commend setup time and data setup time
tSH applies for address holde time, clock enable hold time. commend hold time and data hold time
16.0 DQ Buffer Output Drive Characteristics
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Measure in linear
Output rise time
trh
1.37
4.37
Volts/ns
Volts/ns
Volts/ns
Volts/ns
3
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Output fall time
Output rise time
Output fall time
tfh
trh
tfh
1.30
2.8
3.8
5.6
5.0
3
3.9
2.9
1,2
1,2
2.0
Notes :
1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS
.
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Synchronous DRAM
17.0 IBIS Specification
200MHz/166MHz/133MHz Pull-up
0.5 1.5 2.5
0
1
2
3
3.5
IOH Characteristics (Pull-up)
0
-100
-200
-300
-400
-500
-600
166MHz
166MHz
133MHz
Max
Voltage
133MHz
Min
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
I (mA)
I (mA)
-2.4
-27.3
-74.1
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
Voltage
IOH Min (200MHz/166MHz/133MHz)
IOH Max (200MHz/166MHz/133MHz)
200MHz/166MHz/133MHz Pull-down
IOL Characteristics (Pull-down)
250
200
150
100
50
166MHz
166MHz
133MHz
Max
Voltage
133MHz
Min
(V)
I (mA)
0.0
I (mA)
0.0
0.0
0.4
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
70.2
0.65
0.85
1.0
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
1.4
1.5
1.65
1.8
1.95
3.0
0
3.45
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (200MHz/166MHz/133MHz)
IOL Max (200MHz/166MHz/133MHz)
Rev. 1.22 August 2008
13 of 15
K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
Minimum VDD clamp current
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
I (mA)
0.0
20
15
10
5
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
-2 -1
VSS Clamp @ CLK, CKE, CS, DQM & DQ
-3
0
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0
-10
-20
-30
-40
-50
-60
0.0
0.0
0.0
Voltage
I (mA)
Rev. 1.22 August 2008
14 of 15
K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
18.0 Simplified Truth Table
A0 ~ A9
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
A11, A12
Register
Refresh
Mode register set
Auto refresh
H
X
H
L
L
L
L
L
X
OP code
1,2
3
3
3
3
H
L
L
L
H
X
X
X
X
Entry
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
Exit
L
H
H
H
X
X
Bank active & row addr.
Read &
column address
X
X
V
V
Row address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
4,5
6
Column
address
L
H
L
H
Column
address
Write &
column address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
Burst stop
Precharge
X
Bank selection
All banks
V
X
L
H
X
H
L
X
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No operation command
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.22 August 2008
15 of 15
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