K4S641632K-UL750 [SAMSUNG]
Synchronous DRAM, 4MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, ROHS COMPLIANT, TSOP2-54;
| 型号： | K4S641632K-UL750 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 4MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, ROHS COMPLIANT, TSOP2-54 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S640832K
K4S641632K
Synchronous DRAM
64Mb K-die SDRAM Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 February 2006
1 of 14
K4S640832K
K4S641632K
Synchronous DRAM
Revision History
Revision
0.0
Month
January
March
Year
2005
2005
2005
2005
2005
2006
History
- Target spec release
- Change DC current
- Delete bit organization for x4
- Delete 7ns speed bin
- Final spec release
0.1
0.2
April
0.3
July
1.0
1.1
September
February
- Added 5ns speed bin for x16
Rev. 1.1 February 2006
2 of 14
K4S640832K
K4S641632K
Synchronous DRAM
2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM (x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
• Pb/Pb-free Package
• RoHS compliant for Pb-free Package
GENERAL DESCRIPTION
The K4S640832K / K4S641632K is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8
bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows
precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies,
programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
Ordering Information
Part No.
Orgainization
Max Freq.
Interface
Package
K4S640832K-T(U)C/L75
K4S641632K-T(U)C/L50
K4S641632K-T(U)C/L60
K4S641632K-T(U)C/L75
8Mb x 8
133MHz(CL=3)
200MHz(CL=3)
166MHz(CL=3)
133MHz(CL=3)
54pin TSOP(II)
Pb (Pb-free)
LVTTL
4Mb x 16
Organization
Row Address
Column Address
A0-A8
8Mx8
4Mx16
A0~A11
A0~A11
A0-A7
Row & Column address configuration
Rev. 1.1 February 2006
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K4S641632K
Synchronous DRAM
Package Physical Dimension
0~8°C
0.25
TYP
0.010
#54
#28
#27
#1
+0.075
0.125
-0.035
+0.003
0.005
-0.001
22.62
0.891
MAX
22.22
0.875
± 0.10
0.21 ± 0.05
± 0.10
± 0.004
1.00
0.039
1.20
0.047
MAX
± 0.004
± 0.002
0.008
0.10
MAX
0.004
0.05
MIN
+0.10
0.30
0.80
0.0315
0.71
0.028
-0.05
0.002
(
)
+0.004
0.012 -0.002
54Pin TSOP(II) Package Dimension
Rev. 1.1 February 2006
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K4S640832K
K4S641632K
Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
2M x 8 / 1M x 16
2M x 8 / 1M x 16
2M x 8 / 1M x 16
2M x 8 / 1M x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
Samsung Electronics reserves the right to change products or specification without notice.
*
Rev. 1.1 February 2006
5 of 14
K4S640832K
K4S641632K
Synchronous DRAM
PIN CONFIGURATION (Top view)
x8
x8
x16
x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
VDD
DQ0
VDDQ
N.C
1
VSS
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
2
DQ7
VSSQ
N.C
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
3
4
DQ1
VSSQ
N.C
5
DQ6
VDDQ
N.C
6
7
DQ2
VDDQ
N.C
8
DQ5
VSSQ
N.C
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ3
VSSQ
N.C
DQ4
VDDQ
N.C
VDDQ
DQ8
VDD
VSS
VSS
LDQM
WE
N.C
N.C/RFU N.C/RFU
WE
DQM
CLK
CKE
N.C
A11
A9
UDQM
CLK
CKE
N.C
A11
A9
CAS
RAS
CS
CAS
RAS
CS
BA0
BA0
BA1
BA1
A10/AP A10/AP
A8
A8
A0
A1
A0
A1
A7
A7
A6
A6
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
A2
A2
A5
A5
A3
A3
A4
A4
VDD
VDD
VSS
VSS
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
CS
System clock
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,
Column address : (x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7)
A0 ~ A11
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
CAS
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
Data inputs/outputs are multiplexed on the same pins.
(x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)
DQ0 ~ N
Data input/output
VDD/VSS
VDDQ/VSSQ
Power supply/ground
Data output power/ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
No connection
/reserved for future use
N.C/RFU
This pin is recommended to be left No Connection on the device.
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Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
Unit
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
Max
3.6
Unit
V
Note
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VDD+0.3
0.8
V
1
VIL
V
2
VOH
-
-
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
V
ILI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Symbol
CCLK
CIN
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
Note
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
pF
CADD
COUT
pF
(x8 : DQ0 ~ DQ7), (x16 : DQ0 ~DQ15)
pF
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Synchronous DRAM
DC CHARACTERISTICS (x8)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x8)
Version
Parameter
Symbol
Test Condition
Unit
Note
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
ICC1
55
mA
mA
1
(One bank active)
ICC2P CKE ≤ VIL(max), tCC = 10ns
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
1
1
Precharge standby current in
power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N
15
6
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
mA
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC2NS
ICC3P CKE ≤ VIL(max), tCC = 10ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
3
3
Active standby current in
power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3N
30
25
Active standby current in
non power-down mode
(One bank active)
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
80
mA
1
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
85
1
400
mA
mA
uA
2
3
4
C
L
Self refresh current
CKE ≤ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S640832K-T(U)C
4. K4S640832K-T(U)L
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
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K4S641632K
Synchronous DRAM
DC CHARACTERISTICS (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x16 only)
Version
Parameter
Symbol
Test Condition
Unit
Note
50
60
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
ICC1
80
70
55
mA
mA
1
(One bank active)
ICC2P
CKE ≤ VIL(max), tCC = 10ns
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
1
1
Precharge standby current in
power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N
15
6
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
mA
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC2NS
ICC3P
CKE ≤ VIL(max), tCC = 10ns
3
3
Active standby current in
power-down mode
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3N
30
25
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
110
110
100
85
85
mA
1
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
100
1
400
mA
mA
uA
2
3
4
C
L
Self refresh current
CKE ≤ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S641632K-T(U)C
4. K4S641632K-T(U)L
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.1 February 2006
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K4S640832K
K4S641632K
Synchronous DRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Value
2.4/0.4
1.4
Unit
V
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
30pF
30pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
50
10
15
15
40
60
12
18
18
42
100
60
75
15
20
20
45
Row active to row active delay
RAS to CAS delay
Row precharge time
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
ns
ns
ns
ns
us
1
1
1
1
Row active time
Row cycle time
55
65
ns
1, 6
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
CLK
CLK
CLK
2,5,6
2 CLK + tRP
5
2
2
3
1
1
1
2
1
Col. address to col. address delay
CAS latency = 3
CAS latency = 2
Number of valid output data
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
6. tRC =tRFC, tRDL = tWR.
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K4S640832K
K4S641632K
Synchronous DRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
50
60
75
Parameter
Symbol
Unit Note
Min
Max
Min
6
Max
Min
7.5
10
-
Max
CAS latency=3
5
-
CLK cycle time
tCC
1000
1000
1000
ns
ns
ns
1
1,2
2
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
10
-
-
4.5
5
6
-
5.4
CLK to valid
output delay
tSAC
-
-
-
-
6
2
-
-
2.5
3
3
-
-
Output data
hold time
tOH
-
-
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2
2
1.5
1
1
-
-
2.5
2.5
1.5
1
-
2.5
2.5
1.5
0.8
1
-
ns
ns
ns
ns
ns
3
3
-
-
-
tSS
-
-
-
3, 4
3, 4
2
Input hold time
tSH
tSLZ
-
-
-
-
CLK to output in Low-Z
1
-
-
CAS latency=3
CAS latency=2
4.5
-
-
5
6
-
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
-
-
-
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. tSS applies for address setup time, clock enable setup time, commend setup time and data setup time
tSH applies for address holde time, clock enable hold time, commend hold time and data hold time
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Measure in linear
region : 1.2V ~ 1.8V
Output rise time
trh
1.37
4.37
Volts/ns
3
Measure in linear
Output fall time
Output rise time
Output fall time
tfh
trh
tfh
1.30
2.8
3.8
5.6
5.0
Volts/ns
Volts/ns
Volts/ns
3
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
3.9
2.9
1,2
1,2
Measure in linear
region : 1.2V ~ 1.8V
2.0
Notes :
1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Rev. 1.1 February 2006
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Synchronous DRAM
200MHz/133MHz Pull-up
1.5 2.5
IBIS SPECIFICATION
0
0.5
1
2
3
3.5
IOH Characteristics (Pull-up)
0
-100
-200
-300
-400
-500
-600
200MHz/133MHz 200MHz/133MHz
Voltage
Min
I (mA)
-
Max
(V)
I (mA)
3.45
3.30
3.00
2.70
2.50
1.95
1.80
1.65
1.50
1.40
1.00
0.20
-1.68
-
-19.11
-51.87
-90.44
-107.31
-137.9
-158.34
-173.6
-188.79
-199.01
-241.15
-351.68
-0.35
-3.75
-6.65
-13.75
-17.75
-20.55
-23.55
-26.2
-36.25
-46.5
Voltage
IOH Min (200MHz / 133MHz)
IOH Max (200MHz / 133MHz)
200MHz/133MHz Pull-down
IOL Characteristics (Pull-down)
250
200
150
100
50
200MHz/133MHz 200MHz/133MHz
Voltage
Min
I (mA)
43.92
-
Max
I (mA)
155.82
-
153.72
148.40
146.02
141.75
136.08
131.39
105.84
93.66
75.25
49.14
(V)
3.45
3.30
3.00
1.95
1.80
1.65
1.50
1.40
1.00
0.85
0.65
0.40
43.36
41.20
40.56
39.60
38.40
37.28
30.08
26.64
21.52
14.16
0
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (200MHz / 133MHz)
IOL Max (200MHz / 133MHz)
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Synchronous DRAM
Minimum VDD clamp current
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
I (mA)
0.0
20
15
10
5
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
-2 -1
VSS Clamp @ CLK, CKE, CS, DQM & DQ
-3
0
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0
-10
-20
-30
-40
-50
-60
0.0
0.0
0.0
Voltage
I (mA)
Rev. 1.1 February 2006
13 of 14
K4S640832K
K4S641632K
Synchronous DRAM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
A11,
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
A9 ~ A0
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
X
OP code
1,2
3
3
3
3
L
L
L
H
X
X
X
X
Entry
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
Exit
L
H
H
H
X
X
Bank active & row addr.
Read &
column address
X
X
V
V
Row address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
4,5
6
Column
address
L
H
L
H
Write &
column address
Column
address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
Burst stop
Precharge
X
Bank selection
All banks
V
X
L
H
X
H
L
X
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No operation command
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.1 February 2006
14 of 14
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