K4S643232H-UC550_技术文档

K4S643232H

SDRAM

2M x 32 SDRAM

86 TSOP-II with Pb-Free

(RoHS compliant)

Revision 1.2

April 2006

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.2 April 2006

- 1 -

K4S643232H

SDRAM

Revision History

Revision

0.0

Month

October

November

August

April

Year

2003

2004

2006

History

- Preliminary spec First release.

- Final spec release.

- Corrected typo.

0.1

1.1

1.2

- Applied now format and corrected typo.

Rev. 1.2 April 2006

- 2 -

K4S643232H

SDRAM

512K x 32Bit x 4 Banks

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock.

• Burst read single-bit write operation

• DQM (x4,x8) & L(U)DQM (x16) for masking

• Auto & self refresh

• 15.6us refresh duty cycle

• Pb-free Package

• RoHS compliant

GENERAL DESCRIPTION

The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated

with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.

I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable

latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Ordering Information

Part No.

Orgainization

Max Freq.

143MHz

166MHz

183MHz

200MHz

Interface

LVTTL

Package

K4S643232H-UC/L70

K4S643232H-UC/L60

K4S643232H-UC/L55

K4S643232H-UC/L50

86pin TSOP(II)

2Mbx32

Organization

2Mx32

Row Address

A0~A10

Column Address

A0-A7

Row & Column address configuration

Rev. 1.2 April 2006

- 3 -

K4S643232H

SDRAM

Package Physical Dimension

0~8°C

0.25

0.010

TYP

#86

#44

#43

#1

+0.075

-0.035

0.125

0.005

+0.003

-0.001

22.62

0.891

MAX

22.22

0.875

± 0.10

0.21 ± 0.05

1.00 ± 0.10

1.20

0.047

MAX

± 0.004

± 0.002

± 0.004

0.008

0.039

0.10

MAX

0.004

0.05

0.002

+0.07

MIN

0.20

0.50

0.0197

0.61

-0.03

(

)

+0.003

0.024

0.0079 _-0.001

86Pin TSOP Package Dimension

Rev. 1.2 April 2006

- 4 -

K4S643232H

SDRAM

FUNCTIONAL BLOCK DIAGRAM

LWE

Data Input Register

LDQM

Bank Select

512K x 32

DQi

CLK

ADD

Column Decoder

Latency & Burst Length

LCKE

Programming Register

LWCBR

LRAS

LCBR

LWE

LCAS

Timing Register

CLK

CKE

CS

RAS

CAS

WE

DQM

Rev. 1.2 April 2006

- 5 -

K4S643232H

SDRAM

PIN CONFIGURATION (Top view)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

1

2

3

4

5

6

7

8

9

VSS

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

N.C

DQ5 10

DQ6 11

VSSQ

12

DQ7 13

N.C 14

VDD

DQM0

15

16

VSS

DQM1

N.C

WE 17

CAS 18

RAS 19

CS 20

N.C

CLK

CKE

A9

N.C 21

BA0 22

BA1 23

A10/AP 24

A0 25

A8

A7

A6

A5

A1 26

A2 27

A4

A3

DQM2

VDD

28

29

DQM3

VSS

N.C 30

N.C

DQ16 31

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

VSSQ

DQ24

VSS

VSSQ

32

DQ17 33

DQ18 34

VDDQ

35

DQ19 36

DQ20 37

VSSQ

38

DQ21 39

DQ22 40

VDDQ

41

DQ23 42

43

86Pin TSOP (II)

(400mil x 875mil)

(0.5 mm Pin pitch)

VDD

Rev. 1.2 April 2006

- 6 -

K4S643232H

SDRAM

PIN FUNCTION DESCRIPTION

Name

System clock

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM.

CLK

CS

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disables input buffers for power down mode.

CKE

Clock enable

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA10, Column address : CA0 ~ CA7

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

A0 ~ A10

BA0,1

RAS

Address

Bank select address

Row address strobe

Column address strobe

Write enable

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

WE

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQM0 ~ 3

Data input/output mask

DQ0 ~ 31

VDD/VSS

Data input/output

Power supply/ground

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

This pin is recommended to be left No connection on the device.

VDDQ/VSSQ

NC

Data output power/ground

No Connection

Rev. 1.2 April 2006

- 7 -

K4S643232H

SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

50

Unit

V

°C

mA

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Short circuit current

IOS

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

2.0

-0.3

2.4

-

Typ

3.3

3.0

0

-

Max

3.6

VDDQ+0.3

Unit

V

Note

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

1

2

VIL

VOH

VOL

ILI

0.8

-

0.4

10

IOH = -2mA

IOL = 2mA

3

V

uA

-10

-

Notes :

1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ,

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

Symbol

CCLK

CIN

Min

Max

4

4.5

6.5

Unit

pF

Clock

-

RAS, CAS, WE, CS, CKE, DQM

Address

CADD

COUT

DQ0 ~ DQ31

Rev. 1.2 April 2006

- 8 -

K4S643232H

SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V)

Speed

CAS

Parameter

Symbol

Test Condition

Unit Note

Latency

-50

-55

-60

-70

Burst Length =1

3

2

140

130

Operating Current

(One Bank Active)

tRC ≥ tRC(min), tCC ≥ tCC(min), Io =

ICC1

mA

2

110

0mA

ICC2P

CKE ≤ VIL(max), tCC = 15ns

2

Precharge Standby Current

in power-down mode

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns

ICC2N

12

7

Input signals are changed one time during 30ns

Precharge Standby Current

in non power-down mode

mA

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

CKE ≤ VIL(max), tCC = 15ns

ICC2NS

ICC3P

4

Active Standby Current

in power-down mode

ICC3PS CKE ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns

ICC3N

40

35

Active Standby Current

in non power-down mode

(One Bank Active)

Input signals are changed one time during 30ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

ICC3NS

3

2

3

2

170

150

160

150

140

120

Operating Current

(Burst Mode)

Io = 0 mA, Page Burst

ICC4

ICC5

ICC6

mA

2

3

All bank Activated, tCCD = tCCD(min)

120

Refresh Current

tRC ≥ tRC(min)

CKE ≤ 0.2V

120

2

450

mA

uA

4

5

Self Refresh Current

Notes :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open.

3. Refresh period is 64ms.

4. K4S643232H-UC

5. K4S643232H-UL

Rev. 1.2 April 2006

- 9 -

K4S643232H

SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter

AC input levels (Vih/Vil)

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

Unit

V

ns

V

See Fig. 2

3.3V

Vtt = 1.4V

1200Ω

50Ω

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Output

Z0 = 50Ω

50pF

870Ω

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

50

55

60

70

Row active to row active delay

RAS to CAS delay

Row precharge time

tRRD(min)

tRCD(min)

tRP(min)

2

CLK

us

CLK

1

3

8

3

7

3

7

3

7

tRAS(min)

tRAS(max)

tRC(min)

tRDL(min)

tCDL(min)

tBDL(min)

tCCD(min)

tMRS(min)

Row active time

100

Row cycle time

11

10

1

2

3

Last data in to row precharge

Last data in to new col.address delay

Last data in to burst stop

Col. address to col. address delay

Mode Register Set cycle time

2

1

2

1

CAS Latency=3

CAS Latency=2

Number of valid

output data

ea

4

Note :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer. Refer to the following ns-unit based AC table.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Rev. 1.2 April 2006

- 10

K4S643232H

SDRAM

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

-50

-55

-60

-70

Parameter

Symbol

Unit Note

Min

5

10

-

2

3

2

3

Max

Min

5.5

10

-

2

3

2

3

Max

Min

6

10

-

2

2.5

3

2.5

3

1.5

2.5

1

Max

Min

Max

CAS Latency=3

7

10

-

2

3

CLK cycle time

tCC

1000

ns

1

CAS Latency=2

CAS Latency=3

CAS Latency=2

4.5

6

-

5.0

6

-

5.5

6

-

5.5

6

-

CLK to valid

output delay

tSAC

tOH

tCH

ns

1, 2

2

Output data hold time

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

CLK high pulse

width

3

-

CLK low

pulse width

tCL

tSS

ns

3

1.5

2.5

1

1.5

2.5

1

1.75

2.5

1

Input setup time

Input hold time

tSH

-

ns

3

2

CLK to output in Low-Z

tSLZ

1

-

1

-

1

-

1

CAS latency=3

CAS latency=2

-

4.5

6

-

5.0

6

-

5.5

6

-

5.5

6

CLK to output

in Hi-Z

tSHZ

ns

-

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Rev. 1.2 April 2006

- 11

K4S643232H

SDRAM

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don′t care, H=Logic high, L=Logic low)

,

CKEn-1 CKEn

CS

RAS

CAS

WE

DQM BA0,1

A10/AP

Note

Command

A9 ~ A0

Register

Refresh

Mode register set

Auto refresh

H

X

H

L

X

OP code

1,2

3

L

H

X

Entry

Self

refresh

L

H

L

H

X

L

H

X

H

X

H

Exit

L

H

X

Bank active & row addr.

Read &

column address

X

V

Row address

Column

address

(A⁰~ A7)

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

L

H

L

H

X

L

4

4,5

4

4,5

6

L

H

L

H

Column

address

(A⁰~ A7)

Write &

column address

H

X

L

H

L

H

L

X

V

Burst Stop

Precharge

Bank selection

All banks

V

X

H

L

X

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

Exit

H

L

H

L

X

Clock suspend or

active power down

X

Entry

H

Precharge power down mode

H

L

Exit

L

H

X

V

X

DQM

X

7

H

L

X

H

X

H

No operation command

Notes :

1. OP Code : Operand code

A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 1.2 April 2006

- 12

K4S643232H

SDRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

BA0 ~ BA1

RFU

A10/AP

RFU

A9

W.B.L

A8

A7

A6

A5

A4

A3

BT

A2

A1

A0

Address

Function

TM

CAS Latency

Burst Length

Test Mode

CAS Latency

Burst Type

Burst Length

A8

0

1

A7

0

1

0

1

Type

Mode Register Set

Reserved

A6

A5

0

1

0

1

A4

0

1

0

1

0

1

0

1

Latency

Reserved

2

A3

0

1

Type

Sequential

Interleave

A2

A1 A0

BT = 0

BT = 1

0

1

2

4

8

1

2

4

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

3

Reserved

Reserved Reserved

Full Page Reserved

Write Burst Length

Length

A9

0

1

Burst

Single Bit

Full Page Length : x32 (256)

POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

2. RFU (Reserved for future use) should stay "0" during MRS cycle.

Rev. 1.2 April 2006

- 13

K4S643232H

SDRAM

BURST SEQUENCE (BURST LENGTH = 4)

Initial Address

Sequential

Interleave

A1

0

A0

0

1

2

3

1

2

3

0

2

3

0

1

3

0

1

2

0

1

2

3

1

0

3

2

3

0

1

3

2

1

0

1

0

1

BURST SEQUENCE (BURST LENGTH = 8)

Initial Address

Sequential

Interleave

A2

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

0

2

3

4

5

6

7

0

1

3

4

5

6

7

0

1

2

4

5

6

7

0

1

2

3

5

6

7

0

1

2

3

4

6

7

0

1

2

3

4

5

7

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

1

0

3

2

5

4

7

6

2

3

0

1

6

7

4

5

3

2

1

0

7

6

5

4

5

6

7

0

1

2

3

5

4

7

6

1

0

3

2

6

7

4

5

2

3

0

1

7

6

5

4

3

2

1

0

Rev. 1.2 April 2006

- 14

Device Operation &

Timing Diagram

x32 SDRAM

DEVICE OPERATIONS

CLOCK (CLK)

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SDRAM performs no

operation (NOP). NOP does not initiate any new operation, but

is needed to complete operations which require more than sin-

gle clock cycle like bank activate, burst read, auto refresh, etc.

The device deselect is also a NOP and is entered by asserting

CS high. CS high disables the command decoder so that RAS,

CAS, WE and all the address inputs are ignored.

The clock input is used as the reference for all SDRAM opera-

tions. All operations are synchronized to the positive going edge

of the clock. The clock transitions must be monotonic between

VIL and VIH. During operation with CKE high all inputs are

assumed to be in a valid state (low or high) for the duration of

set-up and hold time around positive edge of the clock in order

to function well Q perform and ICC specifications.

CLOCK ENABLE (CKE)

POWER-UP

The clock enable(CKE) gates the clock onto SDRAM. If CKE

goes low synchronously with clock (set-up and hold time are the-

same as other inputs), the internal clock is suspended from the

next clock cycle and the state of output and burst address is fro-

zen as long as the CKE remains low. All other inputs are ignored

from the next clock cycle after CKE goes low. When all banks

are in the idle state and CKE goes low synchronously with clock,

the SDRAM enters the power down mode from the next clock

cycle. The SDRAM remains in the power down mode ignoring

the other inputs as long as CKE remains low. The power down

exit is synchronous as the internal clock is suspended. When

CKE goes high at least "1CLK + tSS" before the high going edge

of the clock, then the SDRAM becomes active from the same

clock edge accepting all the input commands.

SDRAMs must be powered up and initialized in a pre-

defined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM=

"H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition

for a minimum of 200us.

3. Issue precharge commands for both banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode reg-

ister.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

BANK ADDRESSES (BA0 ~ BA1)

This SDRAM is organized as four independent banks of 524,288

words x 32 bits memory arrays. The BA0 ~ BA1 inputs are

latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~

BA1 are latched at bank active, read, write, mode register set

and precharge operations.

ADDRESS INPUTS (A0 ~ A10)

The 19 address bits are required to decode the 524,288 word

locations are multiplexed into 11 address input pins (A0 ~ A10).

The 11 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 8 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

Rev. 1.2 April 2006

- 15

Device Operation &

Timing Diagram

x32 SDRAM

DEVICE OPERATIONS (Continued)

active to initiate sensing and restoring the complete row of

dynamic cells is determined by tRAS(min). Every SDRAM bank

activate command must satisfy tRAS(min) specification before a

precharge command to that active bank can be asserted. The

maximum time any bank can be in the active state is determined

by tRAS(max). The number of cycles for both tRAS(min) and

tRAS(max) can be calculated similar to tRCD specification.

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various

operating modes of SDRAM. It programs the CAS latency, burst

type, burst length, test mode and various vendor specific options

to make SDRAM useful for variety of different applications. The

default value of the mode register is not defined, therefore the

mode register must be written after power up to operate the

SDRAM. The mode register is written by asserting low on CS,

RAS, CAS and WE (The SDRAM should be in active mode with

CKE already high prior to writing the mode register). The state of

address pins A0 ~ A10 and BA0 ~ BA1 in the same cycle as CS,

RAS, CAS and WE going low is the data written in the mode

register. Two clock cycles is required to complete the write in the

mode register. The mode register contents can be changed

using the same command and clock cycle requirements during

operation as long as all banks are in the idle state. The mode

register is divided into various fields depending on the fields of

functions. The burst length field uses A0 ~ A2, burst type uses

A3, CAS latency (read latency from column address) use A4 ~

A6, vendor specific options or test mode use A7 ~ A8, A10/AP

and BA0 ~ BA1. The write burst length is programmed using A9.

A7 ~ A8, A10/AP and BA0 ~ BA1 must be set to low for normal

SDRAM operation. Refer to the table for specific codes for vari-

ous burst length, burst type and CAS latencies.

BURST READ

The burst read command is used to access burst of data on con-

secutive clock cycles from an active row in an active bank. The

burst read command is issued by asserting low on CS and CAS

with WE being high on the positive edge of the clock. The bank

must be active for at least tRCD(min) before the burst read com-

mand is issued. The first output appears in CAS latency number

of clock cycles after the issue of burst read command. The burst

length, burst sequence and latency from the burst read com-

mand is determined by the mode register which is already pro-

grammed. The burst read can be initiated on any column

address of the active row. The address wraps around if the initial

address does not start from a boundary such that number of out-

puts from each I/O are equal to the burst length programmed in

the mode register. The output goes into high-impedance at the

end of the burst, unless a new burst read was initiated to keep

the data output gapless. The burst read can be terminated by

issuing another burst read or burst write in the same bank or the

other active bank or a precharge command to the same bank.

The burst stop command is valid at every page burst length.

BANK ACTIVATE

The bank activate command is used to select a random row in

an idle bank. By asserting low on RAS and CS with desired row

and bank address, a row access is initiated. The read or write

operation can occur after a time delay of tRCD(min) from the time

of bank activation. tRCD is an internal timing parameter of

SDRAM, therefore it is dependent on operating clock frequency.

The minimum number of clock cycles required between bank

activate and read or write command should be calculated by

dividing tRCD(min) with cycle time of the clock and then rounding

off the result to the next higher integer. The SDRAM has four

internal banks in the same chip and shares part of the internal

circuitry to reduce chip area, therefore it restricts the activation

of four banks simultaneously. Also the noise generated during

sensing of each bank of SDRAM is high, requiring some time for

power supplies to recover before another bank can be sensed

reliably. tRRD(min) specifies the minimum time required between

activating different bank. The number of clock cycles required

between different bank activation must be calculated similar to

tRCD specification. The minimum time required for the bank to be

BURST WRITE

The burst write command is similar to burst read command and

is used to write data into the SDRAM on consecutive clock

cycles in adjacent addresses depending on burst length and

burst sequence. By asserting low on CS, CAS and WE with valid

column address, a write burst is initiated. The data inputs are

provided for the initial address in the same clock cycle as the

burst write command. The input buffer is deselected at the end

of the burst length, even though the internal writing can be com-

pleted yet. The writing can be completed by issuing a burst read

and DQM for blocking data inputs or burst write in the same or

another active bank. The burst stop command is valid at every

burst length. The write burst can also be terminated by using

DQM for blocking data and procreating the bank tRDL after the

last data input to be written into the active row. See DQM

OPERATION also.

Rev. 1.2 April 2006

- 16

Device Operation &

Timing Diagram

x32 SDRAM

DEVICE OPERATIONS (Continued)

AUTO REFRESH

DQM OPERATION

The DQM is used to mask input and output operations. It works

similar to OE during read operation and inhibits writing during

write operation. The read latency is two cycles from DQM and

zero cycle for write, which means DQM masking occurs two

cycles later in read cycle and occurs in the same cycle during

write cycle. DQM operation is synchronous with the clock. The

DQM signal is important during burst interruptions of write with

read or precharge in the SDRAM. Due to asynchronous nature

of the internal write, the DQM operation is critical to avoid

unwanted or incomplete writes when the complete burst write is

not required. Please refer to DQM timing diagram also.

The storage cells of SDRAM need to be refreshed every 64ms

to maintain data. An auto refresh cycle accomplishes refresh of

a single row of storage cells. The internal counter increments

automatically on every auto refresh cycle to refresh all the rows.

An auto refresh command is issued by asserting low on CS,

RAS and CAS with high on CKE and WE. The auto refresh com-

mand can only be asserted with both banks being in idle state

and the device is not in power down mode (CKE is high in the

previous cycle). The time required to complete the auto refresh

operation is specified by tRFC(min). The minimum number of

clock cycles required can be calculated by driving tRFC with

clock cycle time and them rounding up to the next higher integer.

The auto refresh command must be followed by NOP's until the

auto refresh operation is completed. All banks will be in the idle

state at the end of auto refresh operation. The auto refresh is the

preferred refresh mode when the SDRAM is being used for nor-

mal data transactions. The auto refresh cycle can be performed

once in 15.6us or a burst of 4096 auto refresh cycles once in

64ms.

PRECHARGE

The precharge operation is performed on an active bank by

asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1

of the bank to be precharged. The precharge command can be

asserted anytime after tRAS(min) is satisfied from the bank active

command in the desired bank. tRP is defined as the minimum

number of clock cycles required to complete row precharge is

calculated by dividing tRP with clock cycle time and rounding up

to the next higher integer. Care should be taken to make sure

that burst write is completed or DQM is used to inhibit writing

before precharge command is asserted. The maximum time any

bank can be active is specified by tRAS(max). Therefore, each

bank activate command. At the end of precharge, the bank

enters the idle state and is ready to be activated again. Entry to

Power down, Auto refresh, Self refresh and Mode register set

etc. is possible only when all banks are in idle state.

SELF REFRESH

The self refresh is another refresh mode available in the

SDRAM. The self refresh is the preferred refresh mode for data

retention and low power operation of SDRAM. In self refresh

mode, the SDRAM disables the internal clock and all the input

buffers except CKE. The refresh addressing and timing are

internally generated to reduce power consumption.

The self refresh mode is entered from all banks idle state by

asserting low on CS, RAS, CAS and CKE with high on WE.

Once the self refresh mode is entered, only CKE state being low

matters, all the other inputs including the clock are ignored in

order to remain in the self refresh mode.

The self refresh is exited by restarting the external clock and

then asserting high on CKE. This must be followed by NOP's for

a minimum time of tRFC before the SDRAM reaches idle state to

begin normal operation. If the system uses burst auto refresh

during normal operation, it is recommended to use burst 4096

auto refresh cycles immediately after exiting in self refresh

mode.

AUTO PRECHARGE

The precharge operation can also be performed by using auto

precharge. The SDRAM internally generates the timing to satisfy

tRAS(min) and "tRP" for the programmed burst length and CAS

latency. The auto precharge command is issued at the same

time as burst read or burst write by asserting high on A10/AP. If

burst read or burst write by asserting high on A10/AP, the bank is

left active until a new command is asserted. Once auto

precahrge command is given, no new commands are possible to

that particular bank until the bank achieves idle state.

BOTH BANKS PRECHARGE

Both banks can be precharged at the same time by using Pre-

charge all command. Asserting low on CS, RAS, and WE with

high on A10/AP after all banks have satisfied tRAS(min) require-

ment, performs precharge on all banks. At the end of tRP after

performing precharge to all the banks, both banks are in idle

state.

Rev. 1.2 April 2006

- 17

Device Operation &

Timing Diagram

x32 SDRAM

BASIC FEATURE AND FUNCTION DESCRIPTIONS

1. CLOCK Suspend

1) Clock Suspended During Write (BL=4

CLK

2) Clock Suspended During Read (BL=4)

RD

CMD

CKE

WR

Masked by CKE

Internal

CKE

D0

Q1

DQ(CL2)

DQ(CL3)

D0

D1

D2

D3

Q0

Q2

Q1

Q3

Q2

Q3

Q0

Not Written

SuspendedDout

2. DQM Operation

1) Write Mask (BL=4)

2) Read Mask (BL=4)

RD

CLK

WR

CMD

DQM

Masked byDQM

D3

Masked by DQM

Hi-Z

DQ(CL2)

DQ(CL3)

D0

D1

Q0

Q2

Q1

Q3

Q2

Hi-Z

D3

Q3

DQM to Data-in Mask = 0

DQM to Data-out Mask = 2

3) DQM with Clock Suspended (Full Page Read) ^{Note 2}

CLK

CMD

RD

CKE

DQM

Hi-Z

DQ(CL2)

DQ(CL3)

Q6

Q5

Q0

Q2

Q1

Q4

Q3

Q7

Q6

Q8

Q7

*Note : 1. CKE to CLK disable/enable = 1CLK.

2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"

3. DQM masks both data-in and data-out.

Rev. 1.2 April 2006

- 18

Device Operation &

Timing Diagram

x32 SDRAM

3. CAS Interrupt (I)

Note 1

1) Read interrupted by Read (BL=4)

CLK

CMD

ADD

RD RD

A

B

DQ(CL2)

DQ(CL3)

QA0 QB0 QB1 QB2 QB3

tCCD

Note 2

2) Write interrupted by Write (BL=2)

CLK

3) Write interrupted by Read (BL=2)

WR RD

WR WR

CMD

tCCD

Note 2

tCCD

Note 2

A

B

A

B

ADD

DQ

DA0 DB0 DB1

DQ(CL2)

DQ(CL3)

DA0

QB0 QB1

tCDL

Note 3

tCDL

Note 3

*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.

By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.

2. tCCD : CAS to CAS delay. (=1CLK)

3. tCDL : Last data in to new column address delay. (=1CLK)

Rev. 1.2 April 2006

- 19

Device Operation &

Timing Diagram

x32 SDRAM

4. CAS Interrupt (II) : Read Interrupted by Write & DQM

(a) CL=2, BL=4

CLK

i) CMD

DQM

RD WR

DQ

ii) CMD

D0

D1

D2

D3

D2

RD

WR

DQM

DQ

Hi-Z

D0

D1

D3

RD

WR

iii) CMD

DQM

DQ

Hi-Z

D0

D1

D2

D1

D3

D2

RD

WR

iv) CMD

DQM

DQ

Hi-Z

Note 1

Q0

D0

D3

(b) CL=3, BL=4

CLK

i) CMD

RD WR

DQM

DQ

D0

D1

D2

D3

D2

ii) CMD

RD

WR

DQM

DQ

D0

D1

D3

D2

RD

WR

iii) CMD

DQM

DQ

D0

D1

D3

WR

iii) CMD

DQM

DQ

Hi-Z

D0

D1

D2

D1

D3

D2

RD

WR

iv) CMD

DQM

DQ

Hi-Z

Note 1

D0

D3

Q0

*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.

Rev. 1.2 April 2006

- 20

Device Operation &

Timing Diagram

x32 SDRAM

5. Write Interrupted by Precharge & DQM

CLK

Note 3,4

WR

PRE

CMD

Note 2

DQM

DQ

D0

D1

D2

D3

Masked by DQM

1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.

2. To inhibit invalid write, DQM should be issued.

*Note :

3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge

interrupt but only another bank precharge of four banks operation.

4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"

.

From the next generation, tRDL will be only 2CLK for every clock frequency.

6. Precharge

2) Normal Read (BL=4)

CLK

1) Normal Write (BL=4)

CLK

Note 2

1

WR

D0

CMD

DQ

PRE

CMD

RD

PRE

Q2

D1

D2

D3

DQ(CL2)

Q0

Q1

Q0

Q3

tRDL

2

Note 1,4

DQ(CL3)

Q1

Q2

Q3

7. Auto Precharge

1) Normal Write (BL=4)

CLK

2) Normal Read (BL=4)

CLK

WR

D0

CMD

DQ

CMD

DQ(CL2)

DQ(CL3)

RD

D1

D2

D3

D0

D1

D0

D2

D1

D3

D2

Note 3,4

D3

Auto Precharge Starts

Note 3

Auto Precharge Starts

*Note : 1. tRDL : Last data in to row precharge delay

2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.

3. The row active command of the precharge bank can be issued after tRP from this point.

The new read/write command of other activated bank can be issued from this point.

At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.

4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"

.

From the next generation, tRDL will be only 2CLK for every clock frequency

Rev. 1.2 April 2006

- 21

Device Operation &

Timing Diagram

x32 SDRAM

8. Burst Stop & Interrupted by Precharge

1) Normal Write (BL=4)

CLK

2) Write Burst Stop (BL=8)

CLK

WR

STOP

CMD

DQM

DQ

WR

CMD

DQM

DQ

PRE

D0

D1

D2

D3

D0

D1

D2

D3

D4

D5

tRDL Note 1,5

tBDL Note 2

3) Read Interrupted by Precharge (BL=4)

CLK

4) Read Burst Stop (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

RD

PRE

Q0

STOP

Q0

CMD

DQ(CL2)

DQ(CL3)

RD

Note 3

1

Q1

Q0

Q1

Q0

2

Q1

9. MRS

1) Mode Register Set

CLK

Note 4

CMD

MRS

ACT

PRE

tRP

2CLK

*Note : 1. tRDL : 1 CLK

2. tBDL : 1 CLK ; Last data in to burst stop delay.

Read or write burst stop command is valid at every burst length.

3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.

4. PRE : All banks precharge if necessary.

MRS can be issued only at all banks precharge state.

5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"

.

From the next generation, tRDL will be only 2CLK for every clock frequency

Rev. 1.2 April 2006

- 22

Device Operation &

Timing Diagram

x32 SDRAM

10. Clock Suspend Exit & Power Down Exit

1) Clock Suspend (=Active Power Down) Exit

CLK

2) Power Down (=Precharge Power Down) Exit

CLK

CKE

tSS

Internal

CLK

Note 1

Internal

CLK

Note 2

CMD

ACT

NOP

RD

11. Auto Refresh & Self Refresh

Note 3

1) Auto Refresh

CLK

¡ó

Note 4

Note 5

CMD

CKE

PRE

AR

CMD

¡ó

tRP

tRFC

Note 6

2) Self Refresh

CLK

¡ó

Note 4

CMD

CKE

PRE

SR

CMD

¡ó

tRP

tRFC

*Note : 1. Active power down : one or more banks active state.

2. Precharge power down : all banks precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.

No precharge commands are required after auto refresh command.

During tRFC from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, all banks must be idle state.

5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh mode, refresh interval and refresh operation are perfomed internally.

After self refresh entry, self refresh mode is kept while CKE is low.

During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.

For the time interval of tRFC from self refresh exit command, any other command can not be accepted.

Before/After self refresh mode, burst auto refresh cycle (4096 cycles) is recommended.

Rev. 1.2 April 2006

- 23

Device Operation &

Timing Diagram

x32 SDRAM

12. About Burst Type Control

At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8)

BL=1, 2, 4, 8 and full page.

Sequential Counting

Basic

MODE

At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8)

BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting

Interleave Counting

Every cycle Read/Write Command with random column address can realize Random

Column Access.

That is similar to Extended Data Out (EDO) Operation of conventional DRAM.

Random

MODE

Random column Access

tCCD = 1 CLK

13. About Burst Length Control

At MRS A2,1,0 = "000".

At auto precharge, tRAS should not be violated.

1

At MRS A2,1,0 = "001".

At auto precharge, tRAS should not be violated.

2

Basic

MODE

4

At MRS A2,1,0 = "010".

At MRS A2,1,0 = "011".

8

At MRS A2,1,0 = "111".

Wrap around mode(Infinite burst length) should be stopped by burst stop

Ras interrupt or CAS interrupt

Full Page

At MRS A9 = "1".

Special

BRSW

MODE

Read burst =1, 2, 4, 8, full page write Burst =1

At auto precharge of write, tRAS should not be violated.

tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively

Using burst stop command, any burst length control is possible.

Random

Burst Stop

MODE

Before the end of burst, Row precharge command of the same bank stops read/write

burst with Row precharge.

RAS Interrupt

tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.

During read/write burst with auto precharge, RAS interrupt can not be issued.

(Interrupted by Precharge)

Interrupt

MODE

Before the end of burst, new read/write stops read/write burst and starts new

read/write burst.

During read/write burst with auto precharge, CAS interrupt can not be issued.

CAS Interrupt

Rev. 1.2 April 2006

- 24

Device Operation &

Timing Diagram

x32 SDRAM

FUNCTION TRUTH TABLE (TABLE 1)

Current

State

CS

RAS

CAS

WE

BA

ADDR

ACTION

Note

H

L

H

L

H

L

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

H

L

X

H

L

X

H

L

H

L

X

H

L

H

L

H

L

X

H

L

H

L

H

L

X

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

BA

X

NOP

ILLEGAL

2

CA, A10/AP ILLEGAL

RA

A10/AP

IDLE

Row (& Bank) Active ; Latch RA

NOP

Auto Refresh or Self Refresh

Mode Register Access

NOP

ILLEGAL

4

5

X

L

OP code

X

OP code

X

H

L

X

2

Row

Active

BA

X

BA

X

BA

X

BA

X

CA, A10/AP Begin Read ; latch CA ; determine AP

CA, A10/AP Begin Write ; latch CA ; determine AP

RA

A10/AP

L

H

L

X

H

L

ILLEGAL

Precharge

ILLEGAL

L

X

H

L

NOP (Continue Burst to End --> Row Active)

Term burst --> Row active

CA, A10/AP Term burst, New Read, Determine AP

CA, A10/AP Term burst, New Write, Determine AP

RA

A10/AP

Read

Write

L

3

2

H

L

X

H

L

ILLEGAL

L

Term burst, Precharge timing for Reads

ILLEGAL

NOP (Continue Burst to End --> Row Active)

Term burst --> Row active

X

H

L

CA, A10/AP Term burst, New read, Determine AP

CA, A10/AP Term burst, New Write, Determine AP

RA

A10/AP

3

2

3

L

H

L

X

H

L

H

L

X

H

L

H

L

X

H

L

ILLEGAL

L

Term burst, precharge timing for Writes

ILLEGAL

NOP (Continue Burst to End --> Precharge)

ILLEGAL

X

H

L

Read with

Auto

Precharge

CA, A10/AP ILLEGAL

RA, RA10

ILLEGAL

2

L

X

H

L

NOP (Continue Burst to End --> Precharge)

ILLEGAL

Write with

Auto

Precharge

X

BA

X

CA, A10/AP ILLEGAL

RA, RA10

ILLEGAL

NOP --> Idle after tRP

ILLEGAL

NOP --> Idle after tRPL

L

X

H

L

Pre-

charging

X

2

4

BA

CA

RA

A10/AP

H

L

Rev. 1.2 April 2006

- 25

Device Operation &

Timing Diagram

x32 SDRAM

FUNCTION TRUTH TABLE (TABLE 1)

Current

State

CS

RAS

CAS

WE

BA

ADDR

ACTION

Note

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

H

L

X

H

L

H

L

X

H

L

X

H

L

X

H

L

X

ILLEGAL

NOP --> Row Active after tRCD

ILLEGAL

NOP --> Idle after tRFC

ILLEGAL

NOP --> Idle after 2 clocks

ILLEGAL

Row

X

2

Activating

BA

X

CA

RA

A10/AP

X

Refreshing

L

X

H

L

X

H

L

X

Mode

Register

Accessing

X

ILLEGAL

X

Abbreviations : RA = Row Address

NOP = No Operation Command

BA = Bank Address

CA = Column Address

AP = Auto Precharge

*Note : 1. All entries assume the CKE was active (High) during the precharge clcok and the current clock cycle.

2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the

state of that bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).

5. Illegal if any bank is not idle.

Rev. 1.2 April 2006

- 26

Device Operation &

Timing Diagram

x32 SDRAM

FUNCTION TRUTH TABLE (TABLE 2)

CKE

n

Current

State

CKE

(n-1)

CS

RAS

CAS

WE

ADDR

ACTION

Note

H

L

H

L

H

L

X

H

L

X

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

INVALID

Exit Self Refresh --> Idle after tRFC (ABI)

ILLEGAL

NOP (Maintain Self Refresh)

INVALID

Exit Power Down --> ABI

ILLEGAL

6

Self

Refresh

L

X

H

L

All

Banks

7

Precharge

Power

ILLEGAL

Down

L

X

H

L

X

NOP (Maintain Low Power Mode)

Refer to Table 1

Enter Power Down

ILLEGAL

X

RA

8

All

Banks

Idle

ILLEGAL

Row (& Bank) Active

Enter Self Refresh

Mode Register Access

NOP

Refer to Operations in Table 1

Begin Clock Suspend next cycle

Exit Clock Suspend next cycle

Maintain Clcok Suspend

L

X

8

OP Code

X

H

L

H

L

H

L

Any State

other than

Listed

9

above

L

Abbreviations : ABI = All Banks Idle, RA = Row Address

*Note : 6. CKE low to high transition is asynchronous.

7. CKE low to high transition is asynchronous if restarts internal clock.

A minimum setup time 1CLK + tSS must be satisfied before any command other than exit.

8. Power down and self refresh can be entered only from the both banks idle state.

9. Must be a legal command.

Rev. 1.2 April 2006

- 27

Device Operation &

Timing Diagram

x32 SDRAM

Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1

tCH

CLOCK

tCL

tCC

HIGH

CKE

CS

tRAS

tRC

*Note 1

tSH

tRP

tRCD

tSS

tSH

tSS

RAS

CAS

tCCD

tSH

tSS

tSH

Ra

Ca

Cb

Cc

Rb

ADDR

tSS

*Note 2

*Note 2,3

*Note 2,3 *Note 4

*Note 2

BA0 ~ BA1

BS

*Note 3

*Note 3 *Note 4

Ra

A10/AP

DQ

Rb

tRAC

tSH

tSAC

tSLZ

Qa

tOH

Db

Qc

tSS

tSH

WE

tSS

tSH

DQM

Row Active

Read

Write

Read

Row Active

Precharge

: Don't care

Rev. 1.2 April 2006

- 28


型号：	K4S643232H-UC550
厂家：	SAMSUNG
描述：	Synchronous DRAM, 2MX32, 5ns, CMOS, PDSO86, 0.400 INCH X 0.875 INCH, 0.50 MM PITCH, ROHS COMPLIANT, TSOP2-86 动态存储器光电二极管
文件：	总28页 (文件大小：414K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4S643232H-UC550 [SAMSUNG]

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