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1Gb A-die DDR2 SDRAM Specification 1GB的A-死DDR2 SDRAM规格
K4T1G044QA 数据手册
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PDF下载1G A-die DDR2 SDRAM
DDR2 SDRAM
1Gb A-die DDR2 SDRAM Specification
Version 1.1
August 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 Aug. 2005
Page 1 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Contents
0. Ordering Information
1. Key Feature
2. Package Pinout/Mechanical Dimension & Addressing
2.1 Package Pinout & Mechanical Dimension
2.2 Input/Output Function Description
2.3 Addressing
3. Absolute Maximum Rating
4. AC & DC Operating Conditions & Specifications
Rev. 1.1 Aug. 2005
Page 2 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Ordering Information
Organization
256Mx4
DDR2-667 5-5-5
K4T1G044QA-ZCE6
K4T1G084QA-ZCE6
K4T1G164QA-ZCE6
DDR2-533 4-4-4
K4T1G044QA-ZCD5
K4T1G084QA-ZCD5
K4T1G164QA-ZCD5
DDR2-400 3-3-3
Package
K4T1G044QA-ZCCC
K4T1G084QA-ZCCC
K4T1G164QA-ZCCC
68 FBGA
68 FBGA
84 FBGA
128Mx8
64Mx16
Note 1 : Speed bin is in order of CL-tRCD-tRP.
Note 2 : x4/x8 Package - including 8 dummy balls.
Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
Units
tCK
ns
5
4
3
15
15
54
15
15
55
15
15
55
ns
tRC(min)
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8
banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 667Mb/sec/pin (DDR2-667) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 1Gb(x4) device receive 14/
11/3 addressing.
• 200 MHz f for 400Mb/sec/pin, 267MHz f for 533Mb/sec/
CK
CK
pin, 333MHz f for 667Mb/sec/pin
CK
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power
supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 68ball FBGAs(x4/x8) and in
84ball FBGAs(x16).
• Special Function Support
-PASR(Partial Array Self Refresh)
-50ohm ODT
-High Temperature Self-Refresh rate enable
Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of oper-
ation.
• Average Refresh Period 7.8us at lower than T
85°C,
CASE
3.9us at 85°C < T
< 95 °C
CASE
•
Package: 68ball FBGA - 256Mx4/128Mx8 , 84ball FBGA -
64Mx16
• All of Lead-free products are compliant for RoHS
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device
Operation & Timing Diagram”.
Rev. 1.1 Aug. 2005
Page 3 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Package Pinout/Mechanical Dimension & Addressing
Package Pinout
x4 package pinout (Top View) : 68ball FBGA Package (60balls + 8balls of dummy balls)
1
2
3
7
8
9
A
B
C
D
NC
NC
NC
NC
VDD
NC
NC
VSS
DM
E
F
VSSQ DQS
DQS VSSQ
VDDQ DQ0
VDDQ
NC
VSSQ
DQ1
VDDQ
NC
VDDQ
DQ3
G
H
J
VDDQ
NC
VSSQ
DQ2
VSSDL
RAS
VSSQ
CK
VDDL VREF
CKE
VSS
WE
VDD
ODT
K
L
CK
BA2
BA0
A10/AP
A3
BA1
A1
CAS
A2
CS
A0
A4
VDD
VSS
M
N
P
VSS
A5
A6
A7
A9
A11
NC
A8
Notes:
VDD
A12
NC
A13
R
T
1. Pin E3 has identical
capacitance as pin E7.
2. VDDL and VSSDL are
power and ground for the
DLL.
U
V
NC
NC
W
NC
NC
: Populated Ball
Ball Locations (x4)
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
+ + + + +
+ + + + + + + + +
+ + + + + + + + +
+ + + + + + + + +
+ + +
+ + +
+ + +
+ + +
+ + +
K
L
+
+
+
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
+
M
N
P
R
T
U
V
W
+ + + + + + + + +
+ + + + + + + + +
+ + + + + + + + +
+ + + + +
Rev. 1.1 Aug. 2005
Page 4 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
x8 package pinout (Top View) : 68ball FBGA Package (60balls + 8balls of dummy balls)
1
2
3
7
8
9
A
B
C
D
NC
NC
NC
NC
NU/
VDD
DQ6
VSS
E
F
VSSQ DQS
DQS VSSQ
VDDQ DQ0
VDDQ
DQ7
RDQS
DM/
Notes:
VSSQ
DQ1
RDQS
1. Pins F3 and E2 have
identical capacitance as
pins F7 and E8.
VDDQ
DQ4
VDDQ
DQ3
VSS
WE
G
H
J
VDDQ
DQ5
VSSQ
DQ2
VSSDL
RAS
VSSQ
CK
VDDL VREF
CKE
VDD
2. For a read, when enabled,
strobe pair RDQS &
K
L
CK
ODT
RDQS are identical in
function and timing to
strobe pair DQS & DQS
and input masking
BA2
BA0
A10/AP
A3
BA1
A1
CAS
A2
CS
A0
A4
VDD
VSS
M
N
P
VSS
A5
A6
A7
A9
A11
NC
A8
function is disabled.
3. The function of DM or
RDQS/RDQS are enabled
by EMRS command.
4. VDDL and VSSDL are
power and ground for the
DLL.
VDD
A12
NC
A13
R
T
U
V
NC
NC
W
NC
NC
: Populated Ball
Ball Locations (x8)
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
+ + + + +
+ + + + + + + + +
+ + + + + + + + +
+ + + + + + + + +
+ + +
+ + +
+ + +
+ + +
+ + +
K
L
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
+
+
+
+
M
N
P
R
T
U
V
W
+ + + + + + + + +
+ + + + + + + + +
+ + + + + + + + +
+ + + + +
Rev. 1.1 Aug. 2005
Page 5 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
x16 package pinout (Top View) : 84ball FBGA Package
1
2
3
7
8
9
A
B
C
D
E
F
VDD
DQ14
VDDQ
DQ12
NC
VSS
VSSQ
UDQS
VDDQ
DQ10
UDQS
VSSQ
DQ8
VDDQ
DQ15
VDDQ
DQ13
VSSQ
DQ9
UDM
VDDQ
DQ11
VSSQ
VSSQ
VDD
DQ6
NC
VSS
VSSQ
LDQS
VDDQ
DQ2
VDDQ
DQ7
LDQS
VSSQ
DQ0
VSSQ
DQ1
LDM
VDDQ
DQ3
G
H
J
VDDQ
DQ4
VDDQ
DQ5
VSSQ
VSSQ
VDDL
VREF
CKE
BA0
VSS
WE
VSSDL
RAS
CK
CK
CS
VDD
ODT
K
L
BA2
VSS
BA1
CAS
M
N
P
R
A10/AP
A3
A1
A5
A2
A6
A0
A4
VDD
VSS
A7
A9
A11
NC
A8
Note :
1. VDDL and VSSDL are
power and ground for the
DLL.
VDD
A12
NC
NC
2. In case of only 8 DQs out
of 16 DQs are used,
LDQS, LDQSB and
DQ0~7 must be used.
: Populated Ball
: Depopulated Ball
Ball Locations (x16)
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
+
+
+
+
Rev. 1.1 Aug. 2005
Page 6 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
FBGA Package Dimension(x4/x8)
11.00 ± 0.10
3.20
# A1 INDEX MARK
1.60
0.80
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
W
X
(0.95)
(1.90)
11.00 ± 0.10
#A1
0.10MAX
0.35±0.05
MAX 1.20
Rev. 1.1 Aug. 2005
Page 7 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
FBGA Package Dimension(x16)
11.00 ± 0.10
3.20
# A1 INDEX MARK
1.60
0.80
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
(0.95)
(1.90)
11.00 ± 0.10
#A1
0.10MAX
0.35±0.05
MAX 1.20
Rev. 1.1 Aug. 2005
Page 8 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Input/Output Functional Description
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing).
CK, CK
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. After V
has become stable during the power on and ini-
REF
CKE
CS
Input
Input
tialization swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry
and exit, V
must be maintained to this input. CKE must be maintained high throughout read and write accesses.
REF
Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
systems with multiple Ranks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For
x16 configuration, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin
will be ignored if the Extended Mode Register Set(EMRS) is programmed to disable ODT.
ODT
RAS, CAS, WE
DM
Input
Input
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coin-
cident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is
enabled by EMRS command.
Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines if the mode register or extended mode register is to be accessed dur-
ing a MRS or EMRS cycle.
BA0 - BA2
Input
Input
Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit
for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled
during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2. The address inputs
also provide the op-code during Mode Register Set commands.
A0 - A13
DQ
Input/Output Data Input/ Output: Bi-directional data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For
the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an
RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS,
UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS,
UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1)
control bit enables or disables all complementary data strobe signals.
DQS, (DQS)
(LDQS), (LDQS)
(UDQS), (UDQS)
(RDQS), (RDQS)
Input/Output
NC
No Connect: No internal electrical connection is present.
Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V
Ground, DQ Ground
V
/V
Supply
Supply
Supply
Supply
Supply
DD DDQ
V
/V
SS SSQ
V
DLL Power Supply: 1.8V +/- 0.1V
DLL Ground
DDL
V
SSDL
V
Reference voltage
REF
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)
x4 DQS/DQS
x8 DQS/DQS
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)
x4 DQS
x8 DQS
x8 DQS, RDQS,
if EMRS(1) [A11] = 0
if EMRS(1) [A11] = 1
x16 LDQS and UDQS
Rev. 1.1 Aug. 2005
Page 9 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
1Gb Addressing
Configuration
# of Bank
256Mb x4
8
128Mb x 8
8
64Mb x16
8
Bank Address
Auto precharge
Row Address
Column Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9
BA0 ~ BA2
A10/AP
A0 ~ A12
A0 ~ A9
A0 ~ A13
A0 ~ A9,A11
* Reference information: The following tables are address mapping information for other densities.
256Mb
Configuration
# of Bank
64Mb x4
4
32Mb x 8
4
16Mb x16
4
Bank Address
Auto precharge
Row Address
Column Address
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9,A11
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A8
512Mb
2Gb
Configuration
# of Bank
128Mb x4
4
64Mb x 8
4
32Mb x16
4
Bank Address
Auto precharge
Row Address
Column Address
BA0,BA1
A10/AP
BA0,BA1
A10/AP
A0 ~ A13
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
A0 ~ A13
A0 ~ A9,A11
Configuration
# of Bank
512Mb x4
8
256Mb x 8
8
128Mb x16
8
Bank Address
Auto precharge
Row Address
Column Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 ~ A14
A0 ~ A9
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9
A0 ~ A14
A0 ~ A9,A11
4Gb
Configuration
# of Bank
1 Gb x4
8
512Mb x 8
8
256Mb x16
8
Bank Address
Auto precharge
Row Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 - A15
A0 - A9
BA0 ~ BA2
A10/AP
A0 - A14
A0 - A9
A0 - A15
A0 - A9,A11
Column Address/page size
Rev. 1.1 Aug. 2005
Page 10 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
V
Notes
Voltage on V pin relative to V
V
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
DD
SS
DD
Voltage on V
Voltage on V
pin relative to V
V
V
DDQ
DDL
SS
DDQ
pin relative to V
V
V
1
SS
DDL
Voltage on any pin relative to V
Storage Temperature
V
V
V
1
SS
IN, OUT
T
°C
1, 2
STG
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
V
Supply Voltage
V
V
DD
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
DDL
V
1.7
1.8
1.9
V
DDQ
V
0.49*V
0.50*V
0.51*V
DDQ
mV
V
1,2
3
REF
DDQ
DDQ
V
V
-0.04
V
V
+0.04
REF
TT
REF
REF
Note : There is no specific device V supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
must be less than or equal
DDQ
DD
to V
.
DD
1. The value of V
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
is expected to be about 0.5
REF
REF
x V
of the transmitting device and V
is expected to track variations in V
.
DDQ
REF
DDQ
2. Peak to peak AC noise on V
may not exceed +/-2% V
(DC).
REF
REF
3. V of transmitting device must track V
of receiving device.
REF
TT
4. AC parameters are measured with V , V
and V
tied together.
DDL
DD
DDQ
Rev. 1.1 Aug. 2005
Page 11 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2
standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol
(DC)
Parameter
Min.
+ 0.125
Max.
V + 0.3
DDQ
Units
Notes
V
DC input logic high
DC input logic low
V
V
V
IH
REF
V (DC)
- 0.3
V
- 0.125
REF
IL
Input AC Logic Level
DDR2-400, DDR2-533
Min. Max.
DDR2-667
Symbol
Parameter
Units
Min.
Max.
V
(AC)
V
+ 0.250
V
+ 0.200
REF
AC input logic high
AC input logic low
-
V
V
IH
REF
V (AC)
V
- 0.250
V
- 0.200
REF
-
IL
REF
AC Input Test Conditions
Symbol
Condition
Value
Units
V
Notes
V
Input reference voltage
0.5 * V
1.0
1
1
REF
DDQ
V
Input signal maximum peak to peak swing
Input signal minimum slew rate
V
SWING(MAX)
SLEW
1.0
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
(AC) level applied to the device under test.
IH/IL
2. The input signal minimum slew rate is to be maintained over the range from V
to V (AC) min for rising edges and the range from V
to V (AC)
REF IL
REF
IH
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the negative
IL
IH
IH
IL
transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
(DC) max
IL
IL
(AC) max
SS
delta TF
V
delta TR
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
Rising Slew =
delta TF
< AC Input Test Signal Waveform >
Rev. 1.1 Aug. 2005
Page 12 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Differential input AC logic Level
Symbol
Parameter
Min.
Max.
+ 0.6
DDQ
Units
Notes
V
V
(AC)
(AC)
AC differential input voltage
0.5
V
V
1
ID
AC differential cross point voltage
0.5 * V
- 0.175
0.5 * V
+ 0.175
DDQ
V
2
IX
DDQ
Notes :
1. V (AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or
ID
UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V (AC) - V (AC).
IH
IL
2. The typical value of V (AC) is expected to be about 0.5 * V
of the transmitting device and V (AC) is expected to track variations in V . VIX(AC)
IX
DDQ
IX
DDQ
indicates the voltage at which differential input signals must cross.
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Differential AC output parameters
Symbol
Parameter
AC differential cross point voltage
Min.
Max.
0.5 * V + 0.125
DDQ
Units
V
Note
1
V
(AC)
0.5 * V
- 0.125
OX
DDQ
Note :
1. The typical value of VOX(AC) is expected to be about 0.5 * V
of the transmitting device and VOX(AC) is expected to track variations in V
.
DDQ
DDQ
VOX(AC) indicates the voltage at which differential output signals must cross.
Rev. 1.1 Aug. 2005
Page 13 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
OCD default characteristics
Description
Output impedance
Parameter
Min
12.6
0
Nom
Max
23.4
1.5
4
Unit
ohms
ohms
ohms
V/ns
Notes
1,2
18
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
6
0
1,2,3
Sout
1.5
5
1,4,5,6,7,8
Notes:
1. Absolute Specifications (0°C ≤ T
≤ +95°C; V = +1.8V ±0.1V, V = +1.8V ±0.1V)
DDQ
CASE
DD
2. Impedance measurement condition for output source dc current: V
= 1.7V; V
= 1420mV; (V
-V
)/Ioh must be less than 23.4 ohms for val-
DDQ
OUT
OUT DDQ
ues of V
between V
and V
-280mV. Impedance measurement condition for output sink dc current: V
= 1.7V; V
= 280mV; V
/
OUT
DDQ
DDQ
DDQ
OUT
OUT
Iol must be less than 23.4 ohms for values of V
between 0V and 280mV.
OUT
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from V (AC) to V (AC).
IL
IH
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaran-
teed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.
Output slew rate load :
VTT
25 ohms
Output
(VOUT)
Reference
Point
7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin and 667Mb/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
Rev. 1.1 Aug. 2005
Page 14 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Symbol
Proposed Conditions
Units
Notes
Operating one bank active-precharge current;
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
t
t
t
t
IDD0
mA
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
IDD1
mA
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern
is same as IDD4W
Precharge power-down current;
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
t
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus
Slow PDN Exit MRS(12) = 1mA
inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP
IDD4W
IDD4R
t
= RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
mA
mA
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
IDD5B
IDD6
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid com-
mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
Normal
mA
mA
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC
t
t
t
t
t
IDD7
t
t
t
t
t
t
t
mA
= RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions
Rev. 1.1 Aug. 2005
Page 15 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Notes :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS
bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
For purposes of IDD testing, the following parameters are utilized
DDR2-667
DDR2-533
DDR2-400
Units
Parameter
5-5-5
4-4-4
3-3-3
CL(IDD)
5
4
3
tCK
t
15
60
15
60
15
55
RCD(IDD)
ns
ns
t
RC(IDD)
t
7.5
ns
ns
RRD(IDD)-x4/x8
7.5
7.5
t
RRD(IDD)-x16
10
3
10
10
5
t
3.75
CK(IDD)
ns
ns
t
45
15
45
15
40
15
RASmin(IDD)
t
ns
ns
RP(IDD)
t
127.5
127.5
127.5
RFC(IDD)
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) and FAW(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
t
t
t
Timing Patterns for 8bank devices x4/ x8
-DDR2-400 3/3/3 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 4/4/4 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
Timing Patterns for 8bank devices x16
-DDR2-400 3/3/3 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 4/4/4 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
-DDR2-667 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
Rev. 1.1 Aug. 2005
Page 16 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM IDD Spec Table
256Mx4(K4T1G044QA)
533@CL=4
Symbol
Unit
Notes
Notes
Notes
667@CL=5
400@CL=3
CE6
LE6
CD5
LD5
CCC
LCC
IDD0
IDD1
90
100
85
95
85
95
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
15
8
15
8
15
8
45
45
40
18
60
135
135
220
45
45
35
18
60
120
120
215
40
40
35
18
55
100
100
210
15
6
15
6
15
6
IDD7
300
280
260
128Mx8(K4T1G084QA)
533@CL=4
Symbol
Unit
667@CL=5
400@CL=3
CE6
LE6
CD5
LD5
CCC
LCC
IDD0
IDD1
90
100
85
95
85
95
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
15
8
15
8
15
8
45
45
40
18
60
155
155
220
45
45
35
18
60
130
130
215
40
40
35
18
55
115
115
210
15
6
15
6
15
6
IDD7
300
280
260
64Mx16(K4T1G164QA)
533@CL=4
Symbol
Unit
667@CL=5
400@CL=3
CE6
LE6
CD5
LD5
CCC
LCC
IDD0
IDD1
120
140
110
130
105
125
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
15
8
15
8
15
8
45
45
40
18
65
195
200
220
45
45
35
18
65
170
170
215
40
40
35
18
60
145
140
210
15
6
15
6
15
6
IDD7
350
340
330
Rev. 1.1 Aug. 2005
Page 17 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Input/Output capacitance
DDR2-400/533
Min Max
1.0 2.0
DDR2-667
Units
Parameter
Symbol
CCK
Min
Max
2.0
Input capacitance, CK and CK
1.0
x
pF
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
CDCK
CI
x
1.0
x
0.25
2.0
0.25
2.0
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.0
x
CDI
0.25
4.0
0.25
3.5
CIO
2.5
x
2.5
x
CDIO
0.5
0.5
Electrical Characteristics & AC Timing for DDR2-667/533/400
(0 °C < T
< 95 °C; V
= 1.8V + 0.1V; V = 1.8V + 0.1V)
DDQ DD
CASE
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
tREFI
75
105
127.5
7.8
195
327.5
7.8
ns
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
CASE
Average periodic refresh interval
85 °C < T
3.9
3.9
CASE
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-667(E6)
DDR2-533(D5)
DDR2-400(CC)
3 - 3 - 3
5 - 5- 5
4 - 4 - 4
Units
min
max
min
max
min
max
5
3.75
3
8
5
3.75
3.75
15
8
5
5
8
ns
ns
ns
ns
ns
ns
ns
8
8
8
8
8
-
-
15
15
54
39
-
-
15
15
55
40
-
tRP
-
-
15
-
-
-
-
tRC
55
70000
70000
70000
tRAS
40
Rev. 1.1 Aug. 2005
Page 18 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DDR2-667
min
DDR2-533
min
DDR2-400
Parameter
Symbol
tAC
Units Notes
max
+450
+400
0.55
0.55
x
max
+500
+450
0.55
0.55
x
min
-600
max
+600
+500
0.55
0.55
x
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
-450
-500
ps
ps
tDQSCK
tCH
-400
-450
-500
0.45
0.45
0.45
tCK
tCK
CK low-level width
tCL
0.45
0.45
0.45
CK half period
tHP
min(tCL, tCH)
3000
min(tCL, tCH)
3750
min(tCL, tCH)
5000
ps
ps
20,21
24
Clock cycle time, CL=x
tCK
8000
8000
8000
15,16,
17,20
DQ and DM input hold time
DQ and DM input setup time
tDH(base)
tDS(base)
175
100
x
x
225
100
x
x
275
150
x
x
ps
ps
15,16,
17,21
Control & Address input pulse width for each input tIPW
0.6
x
x
0.6
x
x
0.6
x
x
tCK
tCK
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
tDIPW
0.35
0.35
0.35
tHZ
x
tAC min
2*tAC min
x
tAC max
tAC max
tAC max
240
x
tAC min
2* tACmin
x
tAC max
tAC max
tAC max
300
x
tAC min
2* tACmin
x
tAC max
tAC max
tAC max
350
tLZ(DQS)
tLZ(DQ)
ps
27
27
22
21
ps
DQS-DQ skew for DQS and associated DQ signals tDQSQ
ps
DQ hold skew factor
tQHS
tQH
x
340
x
400
x
450
ps
DQ/DQS output hold time from DQS
tHP - tQHS
x
tHP - tQHS
x
tHP - tQHS
x
ps
First DQS latching transition to associated clock
edge
tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
tCK
tCK
tCK
tCK
tCK
tCK
tCK
x
x
x
tDSH
x
x
x
tMRD
x
x
x
tWPST
tWPRE
0.4
0.35
0.6
x
0.4
0.35
0.6
x
0.4
0.35
0.6
x
19
Write preamble
14,16,
18,23
Address and control input hold time
Address and control input setup time
tIH(base)
tIS(base)
275
200
x
x
375
250
x
x
475
350
x
x
ps
ps
14,16,
18,22
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
tCK
tCK
28
28
Active to active command period for 1KB page size
products
tRRD
tRRD
7.5
10
x
x
7.5
10
x
x
7.5
10
x
x
ns
ns
12
12
Active to active command period for 2KB page size
products
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
37.5
50
37.5
50
37.5
50
ns
ns
Rev. 1.1 Aug. 2005
Page 19 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
DDR2-667
DDR2-533
DDR2-400
Parameter
Symbol
Units Notes
min
max
min
max
min
2
max
CAS to CAS command delay
tCCD
tWR
2
2
tCK
ns
Write recovery time
15
x
x
x
15
x
x
x
15
x
x
x
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
WR+tRP
7.5
WR+tRP
7.5
WR+tRP
10
tCK
ns
23
33
11
tWTR
tRTP
7.5
7.5
7.5
ns
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
tRFC + 10
200
ns
tCK
Exit precharge power down to any non-read com-
mand
tXP
2
2
x
x
2
2
x
x
2
2
x
x
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
9
Exit active power down to read command
(slow exit, lower power)
7 - AL
6 - AL
6 - AL
9, 10
CKE minimum pulse width
(high and low pulse width)
t
3
2
tCK
tCK
ns
36
3
2
3
2
CKE
t
ODT turn-on delay
2
2
2
AOND
tAC(max)+0.
7
t
ODT turn-on
tAC(min)
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
13, 25
AON
2tCK+tAC(m
ax)+1
2tCK+tAC(m
ax)+1
2tCK+tAC
(max)+1
t
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAC(min)+2
2.5
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
AONPD
t
2.5
2.5
2.5
AOFD
tAC(max)+
0.6
t
tAC(min)
tAC(max)+ 0.6
tAC(max)+ 0.6
ODT turn-off
tAC(min)
tAC(min)
26
24
AOF
2.5tCK+tAC(
max)+1
2.5tCK+
tAC(max)+1
2.5tCK+
tAC(max)+1
t
ODT turn-off (Power-Down mode)
tAC(min)+2
tAC(min)+2
tAC(min)+2
ns
AOFPD
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
tCK
tCK
ns
12
12
12
Minimum time clocks remains ON after CKE asyn-
chronously drops LOW
tDelay
tIS+tCK +tIH
tIS+tCK +tIH
tIS+tCK +tIH
ns
Rev. 1.1 Aug. 2005
Page 20 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals
(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design,
but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac)
for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (250mV to -500 mV for
falling edges).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential
strobe.
2. DDR2 SDRAM AC timing reference load
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise
representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
Output
DQS
RDQS
RDQS
DUT
V
= V
/2
DDQ
TT
Timing
reference
point
25Ω
<AC Timing Reference Load>
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ
DUT
DQ
Output
Test point
<Slew Rate Test Load>
DQS, DQS
RDQS, RDQS
V
= V
/2
DDQ
TT
25Ω
Rev. 1.1 Aug. 2005
Page 21 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied exter-
nally to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
VIH(dc)
V
IH(ac)
DQ
DM
D
D
D
D
t
V
IL(ac)
VIL(dc)
t
t
DH
DH
DS
t
DS
V
IH(ac)
VIH(dc)
DMin
DMin
DMin
DMin
V
IL(ac)
V
IL(dc)
<Data input (write) timing>
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
<Data output (read) timing>
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
Rev. 1.1 Aug. 2005
Page 22 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Specific Notes for dedicated AC parameters
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied.
12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns.
14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
15. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns.
16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns
in differential strobe mode and a slew rate of 1V/ns in single ended mode.
17. tDS and tDH derating Values
∆tDS, ∆tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
125
45
21
0
-
125
45
125
83
0
45
21
0
-
95
12
1
-13
-31
-
-
33
12
-2
-19
-42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83
0
-
83
21
-
-
-
-
0
0
24
13
-1
-19
-43
-
24
10
-7
-30
-59
-
-
-
-
-
-
-
-
-
-
-
-
DQ
Siew
rate
-11
-14
-11
-25
-
-14
-31
-
25
11
-7
-31
-74
-
22
5
-
23
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
17
-6
-35
-77
-
-
-18
-47
-89
-
17
-7
-50
6
-
-
V/ns
-
-
-
-
-
-
-
-
-19
-62
-23
-65
5
-38
-11
-53
-
-
-
-
-
-
-
-
-
-
-127 -140 -115 -128 -103 -116
∆tDS, ∆tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
100
45
21
0
-
100
45
100
67
0
-5
-13
-
45
21
0
-14
-31
-
-
79
12
7
-
33
12
-2
-19
-42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
67
0
-
67
0
-5
-
21
-
-
-
-
0
-14
24
19
11
2
-10
-
24
10
-7
-30
-59
-
-
-
22
5
-
-
-
-
-
-
-
-
-
-
DQ
Slew
rate
31
23
14
2
-
-
-
-
-
-
-
-1
-10
-
35
26
14
-12
-52
17
-6
-35
-77
-140
-
-
-
-
-
-
-
-
-
-
-18
-47
-89
-
38
26
0
6
-
-
V/ns
-
-
-23
-65
-128
38
12
-28
-11
-53
-116
-
-
-
-
-
-
-
-24
-
-
-
-
-
-
-
-
-
-
-40
For all input signals the total tDS (setup time) and tDH(hold time) required is calculated by adding the datasheet tDS(base) and tDH(base) value to the
delta tDS and delta tDH derating value respectively. Example: tDS(total setup time)= tDS(base) + delta tDS.
Rev. 1.1 Aug. 2005
Page 23 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
18. tIS and tIH (input setup and hold) derating.
∆tIS, ∆tIH Derating Values for DDR2-400, DDR2-533
CK, CK Differential Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
Units
Notes
∆tIS
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+217
+209
+197
+180
+155
+113
+30
∆tIH
+124
+119
+113
+105
+75
+51
+30
+16
-1
∆tIS
+247
+239
+227
+210
+185
+143
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
+187
+179
+167
+150
+125
+83
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+60
-11
-14
+19
+49
+46
Command/
Address Slew
rate(V/ns)
-25
-31
+5
+35
+29
-43
-54
-13
-24
+17
+6
-67
-83
-37
-53
-7
-23
-110
-175
-285
-350
-525
-800
-125
-188
-292
-375
-500
-708
-80
-95
-50
-65
-145
-255
-320
-495
-770
-158
-262
-345
-470
-678
-115
-225
-290
-465
-740
-128
-232
-315
-440
-648
∆tIS and ∆tIH Derating Values for DDR2-667, DDR2-800
CK, CK Differential Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
Units
Notes
∆tIS
+150
+143
+133
+120
+100
+67
0
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
∆tIH
+124
+119
+113
+105
+75
∆tIS
+210
+203
+193
+180
+160
+127
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
+30
+60
-5
-14
+16
+55
+46
Command/
Address Slew
rate(V/ns)
-13
-31
-1
+47
+29
-22
-54
-24
+38
+6
-34
-83
-4
-53
+26
-23
-60
-125
-188
-292
-375
-500
-708
-1125
-30
-95
0
-65
-100
-168
-200
-325
-517
-1000
-70
-158
-262
-345
-470
-678
-1095
-40
-128
-232
-315
-440
-648
-1065
-138
-170
-295
-487
-970
-108
-140
-265
-457
-940
For all input signals the total tIS (setup time) and tIH(hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta
tIS and delta tIH derating value respectively. Example: tIS(total setup time)= tIS(base) + delta tIS.
Rev. 1.1 Aug. 2005
Page 24 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be
greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP))
of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.
21. tQH = tHP – tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately,
due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate
mismatch between DQS / DQS and associated DQ in any given cycle.
23. tDAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up.
tWR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer.
tCK refers to the application clock period.
Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.
tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
24. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during pre-
charge power-down, a specific procedure is required as described in DDR2 device operation
25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
26. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Following figure shows a method to calculate the point when device is
no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical
as long as the calculation is consistent.
28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),
or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.
These notes are referenced in the “Timing parameters by speed grade” tables for DDR2-400/533 and DDR2-667.
Rev. 1.1 Aug. 2005
Page 25 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
VTT + 2x mV
VTT + x mV
VOH + x mV
VOH + 2x mV
tLZ
tRPRE begin point
tHZ
tRPST end point
VTT - x mV
VTT - 2x mV
VOL + 2x mV
VOL + x mV
T1
T2
T1
T2
tHZ,tRPST end point = 2*T1-T2
tLZ,tRPRE begin point = 2*T1-T2
<Test method for tLZ, tHZ, tRPRE and tRPST>
29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
level to the differ-
IH(ac)
ential data strobe crosspoint for a rising signal, and from the input signal crossing at the V
signal applied to the device under test.
level to the differential data strobe crosspoint for a falling
IL(ac)
30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
level to the differ-
IH(dc)
ential data strobe crosspoint for a rising signal and V
to the differential data strobe crosspoint for a falling signal applied to the device under test.
IL(dc)
Differential Input waveform timing
DQS
DQS
tDH
tDH
tDS
tDS
V
V
V
V
V
V
V
DDQ
min
min
IH(ac)
IH(dc)
REF(dc)
max
max
IL(dc)
IL(ac)
SS
Rev. 1.1 Aug. 2005
Page 26 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
31. Input waveform timing is referenced from the input signal crossing at the V
device under test.
level for a rising signal and V
for a falling signal applied to the
IL(ac)
IH(ac)
32. Input waverorm timing is referenced from the input signal crossing at the V
device under test.
) level for a rising signal and V (dc) for a falling signal applied to the
IH
IL(dc)
CK
CK
tIH
tIH
tIS
tIS
V
V
V
V
V
V
V
DDQ
min
min
IH(ac)
IH(dc)
REF(dc)
max
max
IL(dc)
IL(ac)
SS
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be mono-
tonic between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be mono-
tonic between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any CKE transition, CKE may not change from its valid level during the time period of tIS
+ 2*tCK + tIH.
Rev. 1.1 Aug. 2005
Page 27 of 28
1G A-die DDR2 SDRAM
DDR2 SDRAM
Revision History
Version 1.0 (Jul. 2005)
- Initial Release
Version 1.1 (Aug. 2005)
- Revised IDD Spec Table
Rev. 1.1 Aug. 2005
Page 28 of 28
K4T1G044QA 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| K4T1G044QA-ZCCC | SAMSUNG | DDR DRAM, 256MX4, 0.6ns, CMOS, PBGA68, ROHS COMPLIANT, FBGA-68 | 获取价格 |
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| K4T1G044QA-ZCCC0 | SAMSUNG | DDR DRAM, 256MX4, 0.6ns, CMOS, PBGA68, ROHS COMPLIANT, FBGA-68 | 获取价格 |
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| K4T1G044QA-ZCCCT | SAMSUNG | DDR DRAM, 256MX4, 0.6ns, CMOS, PBGA68 | 获取价格 |
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| K4T1G044QA-ZCD5 | SAMSUNG | 1Gb A-die DDR2 SDRAM Specification | 获取价格 |
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| K4T1G044QA-ZCD50 | SAMSUNG | DDR DRAM, 256MX4, 0.5ns, CMOS, PBGA68, ROHS COMPLIANT, FBGA-68 | 获取价格 |
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| K4T1G044QA-ZCE6 | SAMSUNG | 1Gb A-die DDR2 SDRAM Specification | 获取价格 |
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| K4T1G044QA-ZCE60 | SAMSUNG | DDR DRAM, 256MX4, 0.45ns, CMOS, PBGA68, ROHS COMPLIANT, FBGA-68 | 获取价格 |
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| K4T1G044QA-ZCE6T | SAMSUNG | DDR DRAM, 256MX4, 0.45ns, CMOS, PBGA68 | 获取价格 |
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| K4T1G044QC | SAMSUNG | 1Gb C-die DDR2 SDRAM Specification | 获取价格 |
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| K4T1G044QC-ZCLF7 | SAMSUNG | DDR DRAM, 256MX4, 0.4ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60 | 获取价格 |
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