K4T51083QC-ZCCCT [SAMSUNG]
DDR DRAM, 64MX8, 0.6ns, CMOS, PBGA60;
| 型号： | K4T51083QC-ZCCCT |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 64MX8, 0.6ns, CMOS, PBGA60 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总28页 (文件大小：652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
512Mb C-die DDR2 SDRAM Specification
60FBGA & 84FBGA with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
Table of Contents
1.0 Ordering Information ................................................................................................................... 4
2.0 Key Features................................................................................................................................. 4
3.0 Package Pinout/Mechanical Dimension & Addressing ............................................................ 5
3.1 x4 package pinout (Top View) : 60ball FBGA Package........................................................................ 5
3.2 x8 package pinout (Top View) : 60ball FBGA Package........................................................................ 6
3.3 x16 package pinout (Top View) : 84ball FBGA Package...................................................................... 7
3.4 FBGA Package Dimension(x4/x8) .................................................................................................... 8
3.5 FBGA Package Dimension(x16)....................................................................................................... 9
4.0 Input/Output Functional Description........................................................................................ 10
5.0 DDR2 SDRAM Addressing ........................................................................................................ 11
6.0 Absolute Maximum DC Ratings............................................................................................... 12
7.0 AC & DC Operating Conditions ................................................................................................ 12
7.1 Recommended DC Operating Conditions (SSTL - 1.8)...................................................................... 12
7.2 Operating Temperature Condition ................................................................................................. 13
7.3 Input DC Logic Level ................................................................................................................... 13
7.4 Input AC Logic Level ................................................................................................................... 13
7.5 AC Input Test Conditions ............................................................................................................. 13
7.6 Differential Input AC Logic Level................................................................................................... 14
7.7 Differential AC Output Parameters................................................................................................. 14
8.0 ODT DC Electrical Characteristics ........................................................................................... 14
9.0 OCD Default Characteristics..................................................................................................... 15
10.0 IDD Specification Parameters and Test Conditions ............................................................. 16
11.0 DDR2 SDRAM IDD Spec Table ............................................................................................... 18
12.0 Input/Output Capacitance ....................................................................................................... 20
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400..................................... 20
13.1 Refresh Parameters by Device Density........................................................................................ 20
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ............................................ 20
13.3 Timing Parameters by Speed Grade ............................................................................................ 21
14.0 General Notes, which may apply for all AC parameters....................................................... 23
15.0 Specific Notes for dedicated AC parameters ........................................................................ 25
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Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
Revision History
Revision
Month
Year
History
1.0
February
2005
- Initial Release
- Added Low power current values for 533&400 speed
- Changed IDD3N/2Q normal current values for x16 org.
1.1
March
2005
1.2
1.3
1.4
1.5
1.6
1.7
May
July
August
January
June
2005
2005
2005
2005
2006
2006
- Corrected Typo
- Revised the Odering Information
- Revised the IDD Current Values
- Added DDR2-800 IDD Current Values
- Added DDR2-800 6-6-6 Speed bin
- Added DDR2-800 6-6-6 IDD Current Values
July
- Added the detailed explanation on the notes for AC parameters
- Corrected Typo
- Added data setup and hold time derating values for single-end DQS
1.8
1.9
October
March
2006
2007
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Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
1.0 Ordering Information
Org.
DDR2-800 5-5-5
DDR2-800 6-6-6
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
Package
60 FBGA
60 FBGA
84 FBGA
128Mx4 K4T51043QC-ZC(L)E7 K4T51043QC-ZC(L)F7 K4T51043QC-ZC(L)E6 K4T51043QC-ZC(L)D5 K4T51043QC-ZC(L)CC
64Mx8 K4T51083QC-ZC(L)E7 K4T51083QC-ZC(L)F7 K4T51083QC-ZC(L)E6 K4T51083QC-ZC(L)D5 K4T51083QC-ZC(L)CC
32Mx16 K4T51163QC-ZC(L)E7 K4T51163QC-ZC(L)F7 K4T51163QC-ZC(L)E6 K4T51163QC-ZC(L)D5 K4T51163QC-ZC(L)CC
Note : Speed bin is in order of CL-tRCD-tRP.
2.0 Key Features
DDR2-800
5-5-5
DDR2-800
6-6-6
DDR2-667
5-5-5
DDR2-533
4-4-4
DDR2-400
3-3-3
Speed
Units
CAS Latency
tRCD(min)
tRP(min)
5
6
5
4
3
tCK
ns
12.5
12.5
57.5
15
15
60
15
15
54
15
15
55
15
15
55
ns
tRC(min)
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/
pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/
sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1, 2, 3, 4 and 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4
banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency -1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 512Mb(x4) device receive
14/11/2 addressing.
The 512Mb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V VDDQ.
The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and
in 84ball FBGAs(x16).
• Special Function Support
- PASR(Partial Array Self Refresh)
- 50ohm ODT
Note : The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode
of operation.
- High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95 °C
• All of Lead-free products are compliant for RoHS
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2
SDRAM Device Operation & Timing Diagram”
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Rev. 1.9 March 2007
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512Mb DDR2 SDRAM
3.0 Package Pinout/Mechanical Dimension & Addressing
3.1 x4 package pinout (Top View) : 60ball FBGA Package
1
2
3
7
8
9
VDDQ
VDD
NC
NC
VSS
DM
DQS
VSSQ
DQ0
A
VSSQ
DQS
VSSQ
NC
B
C
VDDQ
DQ3
VDDQ
DQ2
VDDQ
VDDQ
NC
DQ1
VSSQ
VSSQ
CK
NC
D
VDDL
VREF
VSSDL
VSS
VDD
ODT
E
F
CK
CKE
BA0
WE
RAS
CAS
NC
BA1
CS
G
H
J
A10/AP
A3
A1
A5
A2
A6
A0
VDD
VSS
VSS
A4
A7
A9
K
A11
NC
A8
VDD
A12
NC
A13
L
Note :
1. Pin B3 has identical capacitance as pin B7.
2. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x4)
: Populated Ball
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
G
H
J
+
+
+
K
L
+
+
5 of 29
Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
3.2 x8 package pinout (Top View) : 60ball FBGA Package
1
2
3
7
8
9
NU/
VDD
DQ6
VSSQ
VSS
DQS
VSSQ
DQ0
VDDQ
DQ7
A
RDQS
DM/
DQS
VDDQ
DQ2
VSSQ
DQ1
B
C
RDQS
VDDQ
DQ4
VDDQ
DQ3
VDDQ
DQ5
VSSQ
VSSQ
D
E
F
VDDL
VREF
CKE
CK
CK
VSS
VSSDL
RAS
VDD
ODT
WE
BA1
A1
BA0
NC
CAS
A2
CS
A0
G
H
J
A10/AP
VDD
VSS
VSS
A3
A7
A5
A9
NC
A6
A11
NC
A4
A8
K
VDD
A12
A13
L
Note :
1. Pins B3 and A2 have identical capacitance as pins B7 and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function
and timing to strobe pair DQS & DQS and input masking function is disabled.
3. The function of DM or RDQS/RDQS are enabled by EMRS command.
4. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x8)
: Populated Ball
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
+
G
H
J
+
+
+
K
L
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Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
3.3 x16 package pinout (Top View) : 84ball FBGA Package
1
2
3
7
8
9
A
VSSQ
UDQS
VDDQ
UDQS
VSSQ
VDDQ
DQ15
VDD
DQ14
VDDQ
NC
VSS
UDM
VDDQ
DQ11
VSS
VSSQ
DQ9
B
C
VDDQ
DQ8
VSSQ
LDQS
VSSQ
DQ12
VDD
DQ10
VSSQ
LDQS
DQ13
VDDQ
DQ7
VSSQ
NC
D
E
F
DQ6
VSSQ
DQ1
LDM
VDDQ
DQ4
VDDQ
DQ3
VDDQ
DQ2
DQ0
VDDQ
G
H
J
VSSQ
VREF
VSSQ
CK
DQ5
VDD
VSSDL
VSS
VDDL
CKE
BA0
ODT
K
CK
WE
RAS
NC
BA1
L
CAS
A2
CS
A0
A4
A8
NC
M
N
P
A10/AP
A3
A1
A5
A9
VDD
VSS
VSS
A6
A7
A11
NC
R
A12
NC
VDD
Note :
1. VDDL and VSSDL are power and ground for the DLL.
2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
Ball Locations (x16)
: Populated Ball
: Depopulated Ball
+
G
H
J
Top View
(See the balls through the Package)
K
L
+
+
+
+
+
+
M
N
P
R
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Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
3.4 FBGA Package Dimension(x4/x8)
10.00 ± 0.10
# A1 INDEX MARK
6.40
0.80
1.60
4
9
8
7
6
5
3
2
1
A
B
C
D
E
F
G
H
J
K
L
3.20
(5.00)
(0.90)
(1.80)
60-∅0.45±0.05
∅0.2 M
A B
10.00 ± 0.10
#A1
0.35±0.05
MAX.1.20
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Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
3.5 FBGA Package Dimension(x16)
11.00 ± 0.10
# A1 INDEX MARK
6.40
0.80
1.60
4
9
8
7
6
5
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
3.20
(5.50)
(0.90)
(1.80)
84-∅0.45±0.05
∅0.2 M
A B
11.00 ± 0.10
#A1
0.35±0.05
MAX.1.20
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Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
4.0 Input/Output Functional Description
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of
CK, CK
Input
CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Tak-
ing CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any
bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. After
V
has become stable during the power on and initialization swquence, it must be maintained for proper operation of the CKE
CKE
Input
REF
receiver. For proper self-refresh entry and exit, V
must be maintained to this input. CKE must be maintained high throughout read
REF
and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple
CS
Input
Input
Ranks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16 configuration ODT is applied to each
DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is pro-
grammed to disable ODT.
ODT
RAS, CAS, WE
DM
Input
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input
data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied (For 256Mb and
512Mb, BA2 is not applied). Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS or EMRS cycle.
BA0 - BA1
Input
Input
Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write com-
mands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands.
A0 - A13
DQ
Input/Output Data Input/ Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, LDQS corre-
sponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be
enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode
or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system during
both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals.
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)
x4 DQS/DQS
DQS, (DQS)
(LDQS), (LDQS)
(UDQS), (UDQS)
(RDQS), (RDQS)
Input/Output x8 DQS/DQS
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)
x4 DQS
x8 DQS if EMRS(1)[A11] = 0
x8 DQS, RDQS, if EMRS(1)[A11] = 1
x16 LDQS and UDQS
NC
No Connect: No internal electrical connection is present.
Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V
Ground, DQ Ground
V
/V
Supply
Supply
Supply
Supply
Supply
DD DDQ
V
/V
SS SSQ
V
DLL Power Supply: 1.8V +/- 0.1V
DLL Ground
DDL
V
SSDL
V
Reference voltage
REF
10 of 29
Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
5.0 DDR2 SDRAM Addressing
512Mb
Configuration
# of Banks
128Mb x4
4
64Mb x 8
4
32Mb x16
4
Bank Address
Auto precharge
Row Address
Column Address
BA0,BA1
A10/AP
A0 ~ A13
A0 ~ A9,A11
BA0,BA1
A10/AP
A0 ~ A13
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
* Reference information: The following tables are address mapping information for other densities.
256Mb
Configuration
# of Banks
64Mb x4
4
32Mb x 8
4
16Mb x16
4
Bank Address
Auto precharge
Row Address
Column Address
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9,A11
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A8
1Gb
2Gb
4Gb
Configuration
# of Banks
Bank Address
Auto precharge
Row Address
Column Address
256Mb x4
8
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9,A11
128Mb x 8
8
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9
64Mb x16
8
BA0 ~ BA2
A10/AP
A0 ~ A12
A0 ~ A9
Configuration
# of Banks
Bank Address
Auto precharge
Row Address
Column Address
512Mb x4
8
BA0 ~ BA2
A10/AP
A0 ~ A14
A0 ~ A9,A11
256Mb x 8
8
BA0 ~ BA2
A10/AP
A0 ~ A14
A0 ~ A9
128Mb x16
8
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9
Configuration
# of Banks
1 Gb x4
8
512Mb x 8
8
256Mb x16
8
Bank Address
Auto precharge
Row Address
BA0 ~ BA2
A10/AP
A0 - A15
A0 - A9,A11
BA0 ~ BA2
A10/AP
A0 - A15
A0 - A9
BA0 ~ BA2
A10/AP
A0 - A14
A0 - A9
Column Address/page size
11 of 29
Rev. 1.9 March 2007
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K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
6.0 Absolute Maximum DC Ratings
Symbol
VDD
Parameter
Rating
Units
V
Notes
Voltage on VDD pin relative to VSS
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VDDQ
VDDL
V
V
1
V
IN, VOUT
TSTG
Note :
V
1
°C
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
7.0 AC & DC Operating Conditions
7.1 Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Typ.
1.8
Symbol
Parameter
Units
Notes
Min.
1.7
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
Supply Voltage
V
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
1.7
1.8
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal
to VDD
.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
12 of 29
Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
7.2 Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to
self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
7.3 Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
VIH(DC)
DC input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL(DC)
DC input logic low
- 0.3
VREF - 0.125
V
7.4 Input AC Logic Level
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Symbol
Parameter
Units
Min.
Max.
Min.
Max.
VIH (AC)
IL (AC)
AC input logic high
AC input logic low
VREF + 0.250
-
-
VREF + 0.200
V
V
V
VREF - 0.250
VREF - 0.200
7.5 AC Input Test Conditions
Symbol
VREF
Condition
Input reference voltage
Value
0.5 * VDDQ
Units
V
Notes
1
VSWING(MAX)
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
1
SLEW
V/ns
2, 3
Note :
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
(DC) min
IH
V
SWING(MAX)
REF
(DC) max
IL
IL
(AC) max
SS
delta TF
V
delta TR
Rising Slew =
V
(AC) min - V
delta TR
- V (AC) max
IL
IH
REF
REF
Falling Slew =
delta TF
< AC Input Test Signal Waveform >
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512Mb DDR2 SDRAM
7.6 Differential Input AC Logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
VID(AC)
0.5
VDDQ + 0.6
V
1
AC differential input voltage
AC differential cross point voltage
VIX(AC)
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
Note :
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or
UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH (AC) - V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ .
VIX(AC) indicates the voltage at which differential input signals must cross.
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
7.7 Differential AC Output Parameters
Symbol
Parameter
Min.
Max.
0.5 * VDDQ + 0.125
Units
V
Note
1
V
OX(AC)
0.5 * VDDQ - 0.125
AC differential cross point voltage
Note :
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ .
VOX(AC) indicates the voltage at which differential output signals must cross.
8.0 ODT DC Electrical Characteristics
PARAMETER/CONDITION
Rtt effective impedance value for EMRS(A6, A2)= 0,1 ; 75 ohm
Rtt effective impedance value for EMRS(A6, A2)= 1,0 ; 150 ohm
Rtt effective impedance value for EMRS(A6, A2)= 1,1 ; 50 ohm
Deviation of VM with respect to VDDQ/2
SYMBOL
Rtt1(eff)
Min.
60
NOM
75
Max.
90
Units
ohm
Note
1
Rtt2(eff)
Rtt3(eff)
delta VM
120
40
-6
150
50
180
60
ohm
ohm
%
1
1,2
1
+6
Note :
1. Test condition for Rtt measurements
2. Optional for DDR2-400/533/667
Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I(VIL (ac)) respectively.
VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18
VIH (ac) - VIL (ac)
Rtt(eff) =
I(VIH (ac)) - I(VIL (ac))
Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load.
2 x Vm
- 1
x 100%
delta VM =
VDDQ
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Rev. 1.9 March 2007
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K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
9.0 OCD Default Characteristics
Description
Parameter
Min
Nom
Max
Unit
Notes
Normal 18ohms
See full strength default driver characteristics
Output impedance
ohms
1,2
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
0
0
1.5
4
ohms
ohms
V/ns
6
1,2,3
Sout
1.5
5
1,4,5,6,7,8
Note :
1. Absolute Specifications (0°C ≤ TCASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ- 280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from VIL(AC) to VIH(AC).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC.
This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.
Output slew rate load :
VTT
25 ohms
Output
(VOUT)
Reference
Point
7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin, 667Mb/sec/pin and 800Mb/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
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512Mb DDR2 SDRAM
10.0 IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Symbol
Proposed Conditions
Operating one bank active-precharge current;
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Units
Notes
t
t
t
t
t
t
IDD0
mA
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
IDD1
mA
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pat-
tern is same as IDD4W
Precharge power-down current;
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
t
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus
Slow PDN Exit MRS(12) = 1mA
inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP
IDD4W
IDD4R
t
= RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
mA
mA
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
IDD5B
IDD6
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid com-
mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
Normal
mA
mA
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC
t
t
t
t
t
IDD7
t
t
t
t
t
t
t
= RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions
mA
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512Mb DDR2 SDRAM
Note :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS
bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
masks or strobes.
For purposes of IDD testing, the following parameters are utilized
DDR2-800
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Units
Parameter
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
CL(IDD)
5
6
5
4
3
tCK
t
12.5
57.5
15
60
15
60
15
60
15
55
RCD(IDD)
ns
ns
t
RC(IDD)
t
7.5
ns
ns
RRD(IDD)-x4/x8
7.5
7.5
7.5
7.5
t
RRD(IDD)-x16
10
10
10
3
10
10
5
t
2.5
2.5
3.75
CK(IDD)
ns
ns
t
45
45
15
45
15
45
15
40
15
RASmin(IDD)
t
12.5
105
ns
ns
RP(IDD)
t
105
105
105
105
RFC(IDD)
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) and FAW(IDD) using a burst length of 4.
Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA
t
t
t
Timing Patterns for 4 bank devices with 1KB or 2KB page size
-DDR2-400 3/3/3
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
-DDR2-533 4/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-667 5/5/5
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
-DDR2-800 6/6/6
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
-DDR2-800 5/5/5
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
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Rev. 1.9 March 2007
K4T51043QC
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K4T51163QC
512Mb DDR2 SDRAM
11.0 DDR2 SDRAM IDD Spec
128Mx4(K4T51043QC)
667@CL=5
Symbol
Unit
Notes
Notes
Notes
800@CL=5
800@CL=6
533@CL=4
400@CL=3
CE7
LE7
CF7
LF7
CE6
85
LE6
65
75
5
CD5
LD5
65
CCC
LCC
65
75
4.5
25
30
25
8
IDD0
IDD1
95
105
8
90
105
8
80
95
8
80
95
8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
100
8
75
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
4.5
25
35
35
35
30
35
25
8
30
35
30
12
50
110
115
140
8
30
35
30
12
50
100
105
140
8
40
40
40
30
30
30
30
25
12
TBD
12
TBD
12
8
55
55
55
45
120
125
135
4
40
40
90
95
125
4
145
150
150
8
145
150
150
8
130
135
150
8
100
105
125
4
IDD6
IDD7
250
240
220
180
220
180
220
180
64Mx8(K4T51083QC)
667@CL=5
Symbol
Unit
800@CL=5
800@CL=6
533@CL=4
400@CL=3
CE7
100
110
8
LE7
CF7
90
LF7
CE6
85
LE6
65
75
5
CD5
80
LD5
65
CCC
80
LCC
65
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
110
8
100
8
95
75
95
75
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
8
4.5
25
8
4.5
25
35
35
35
30
35
25
8
30
30
40
40
40
35
30
35
30
30
30
30
30
25
30
25
12
TBD
12
TBD
12
12
8
12
8
60
60
55
45
130
135
135
4
50
40
50
40
165
170
155
8
165
170
150
8
140
145
150
8
120
125
140
8
110
115
125
4
110
110
140
8
95
100
125
4
IDD6
IDD7
255
245
220
180
220
180
220
180
32Mx16(K4T51163QC)
667@CL=5
Symbol
Unit
800@CL=5
800@CL=6
533@CL=4
400@CL=3
CE7
105
120
8
LE7
CF7
100
120
8
LF7
CE6
100
115
8
LE6
85
CD5
95
LD5
85
CCC
95
LCC
85
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
100
5
110
8
100
4.5
25
110
8
100
4.5
25
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
35
35
35
30
30
30
40
40
40
35
35
30
35
30
30
30
30
25
30
25
30
25
12
TBD
12
TBD
12
8
12
8
12
8
60
60
55
45
50
40
50
40
195
200
155
8
195
200
155
8
175
180
150
8
165
170
135
4
155
160
140
8
145
150
125
4
135
140
140
8
125
130
125
4
IDD6
IDD7
340
320
300
270
300
270
300
270
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Rev. 1.9 March 2007
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512Mb DDR2 SDRAM
12.0 Input/Output Capacitance
DDR2-400
DDR2-533
DDR2-667
DDR2-800
Parameter
Symbol
Units
Min
Max
2.0
Min
1.0
x
Max
2.0
Min
Max
2.0
Input capacitance, CK and CK
CCK
CDCK
CI
1.0
x
1.0
x
pF
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
0.25
2.0
0.25
2.0
0.25
1.75
0.25
3.5
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
1.0
x
1.0
x
1.0
x
CDI
CIO
0.25
4.0
0.25
3.5
2.5
x
2.5
x
2.5
x
Input/output capacitance delta, DQ, DM, DQS, DQS CDIO
0.5
0.5
0.5
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(TOPER ; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
13.1 Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
tREFI
75
105
127.5
195
7.8
327.5
ns
0 °C ≤ TCASE ≤ 85°C
85 °C < TCASE ≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
Average periodic refresh interval
3.9
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin(CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tCK, CL=6
tRCD
DDR2-800(E7)
5 - 5 - 5
DDR2-800(F7)
6 - 6 - 6
DDR2-667(E6)
5 - 5 - 5
DDR2-533(D5)
4 - 4 - 4
DDR2-400(CC)
3 - 3 - 3
Units
min
5
max
min
-
max
min
5
max
min
5
max
min
5
max
8
-
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
3.75
2.5
-
8
3.75
3
8
3.75
3
8
3.75
3.75
-
8
5
8
8
8
8
8
-
-
-
2.5
15
15
60
45
8
-
-
-
-
-
12.5
12.5
57.5
45
-
-
15
15
54
39
-
15
-
15
15
55
40
-
tRP
-
-
-
-
-
-
15
-
-
-
-
tRC
55
70000
70000
70000
70000
70000
tRAS
40
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Rev. 1.9 March 2007
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512Mb DDR2 SDRAM
13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Symbol
Units Notes
Parameter
min
-400
-350
0.45
0.45
max
+400
+350
0.55
0.55
min
max
+450
+400
0.55
0.55
min
-500
-450
0.45
0.45
max
+500
+450
0.55
0.55
min
max
+600
+500
0.55
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-450
-400
0.45
0.45
-600
-500
0.45
0.45
ps
ps
tDQSCK
tCH
tCK
tCK
CK low-level width
tCL
min(tCL,
tCH)
min(tCL,
tCH)
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
x
8000
x
x
8000
x
x
8000
x
x
8000
x
ps
ps
ps
20,21
24
Clock cycle time, CL=x
DQ and DM input hold time
tCK
2500
3000
3750
5000
15,16,
17,20
tDH(base)
125
175
225
275
15,16,
17,21
DQ and DM input setup time
tDS(base)
tIPW
50
x
x
100
0.6
x
x
100
0.6
x
x
150
0.6
x
x
ps
Control & Address input pulse width for each
input
0.6
tCK
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
tDIPW
tHZ
0.35
x
x
0.35
x
x
0.35
x
x
0.35
x
x
tCK
ps
tAC max
tAC max
tAC max
tAC max
tLZ(DQS)
tAC min tAC max
tAC min tAC max
2*tAC
min
tAC min tAC max tAC min tAC max
ps
27
27
2*tAC
tAC max
min
DQ low-impedance time from CK/CK
tLZ(DQ)
tAC max 2* tACmin tAC max 2* tACmin tAC max
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
tQHS
tQH
x
x
200
300
x
x
240
340
x
x
x
300
400
x
x
x
350
450
x
ps
ps
ps
22
21
DQ hold skew factor
x
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock
edge
tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
tCK
tCK
tCK
tCK
tCK
tCK
tCK
x
x
x
x
tDSH
x
x
x
x
tMRD
x
x
x
x
tWPST
tWPRE
0.4
0.35
0.6
x
0.4
0.35
0.6
x
0.4
0.35
0.6
x
0.4
0.35
0.6
x
19
Write preamble
14,16,1
8,23
Address and control input hold time
Address and control input setup time
tIH(base)
tIS(base)
250
175
x
x
275
200
x
x
375
250
x
x
475
350
x
x
ps
ps
14,16,1
8,22
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
tCK
tCK
28
28
Active to active command period for 1KB page
size products
tRRD
7.5
10
35
45
x
x
7.5
10
x
x
7.5
10
x
x
7.5
10
x
x
ns
ns
ns
ns
12
12
Active to active command period for 2KB page
size products
tRRD
tFAW
Four Activate Window for 1KB page size
products
37.5
50
37.5
50
37.5
50
Four Activate Window for 2KB page size
products
tFAW
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
15
2
15
2
15
2
15
tCK
ns
x
x
x
x
x
x
x
x
x
x
x
Auto precharge write recovery + precharge time tDAL
WR+tRP
7.5
WR+tRP
7.5
WR+tRP
7.5
WR+tRP
10
tCK
ns
23
33
11
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
tWTR
tRTP
7.5
7.5
7.5
7.5
ns
tXSNR
tRFC + 10
tRFC + 10
tRFC + 10
tRFC + 10
ns
20 of 29
Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Symbol
Units Notes
Parameter
min
max
min
max
min
max
min
max
Exit self refresh to a read command
tXSRD
tXP
200
200
200
200
tCK
tCK
Exit precharge power down to any non-read
command
2
x
x
2
x
x
2
2
x
x
2
x
x
Exit active power down to read command
tXARD
tXARDS
2
2
2
tCK
tCK
9
Exit active power down to read command
(slow exit, lower power)
8 - AL
7 - AL
6 - AL
6 - AL
9, 10
CKE minimum pulse width
(high and low pulse width)
t
tCK
36
3
2
3
2
CKE
3
2
3
2
t
ODT turn-on delay
2
2
2
2
tCK
ns
AOND
tAC(max)
+0.7
tAC(max)
+0.7
tAC(max)
+1
tAC(max)
+1
t
ODT turn-on
tAC(min)
tAC(min)
tAC(min)
tAC(min)
13, 25
AON
2tCK+tA
C(max)+
1
tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC tAC(min)+
tAC(min)+ 2tCK+tAC
t
ODT turn-on(Power-Down mode)
ns
AONPD
2
(max)+1
2
(max)+1
2
2
(max)+1
t
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ns
AOFD
tAC(max)
+ 0.6
tAC(max)
+ 0.6
tAC(max)+
0.6
tAC(max)+
0.6
t
tAC(min)
tAC(min)
tAC(min)
tAC(min)
26
24
AOF
2.5tCK+
tAC(max)
+1
2.5tCK+
tAC(max)
+1
2.5tCK+
tAC(max)
+1
2.5tCK+
tAC(max)
+1
tAC(min)+
2
tAC(min)+
2
tAC(min)+
2
tAC(min)+
2
t
ODT turn-off (Power-Down mode)
ns
AOFPD
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
3
8
0
tCK
tCK
ns
12
12
12
12
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tDelay
ns
21 of 29
Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
14.0 General Notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals.
For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV.
Output slew rate is guaranteed by design, but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac)
for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (250mV to -500 mV
for falling edges).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential
strobe.
2. DDR2 SDRAM AC timing reference load
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise
representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
Output
DQS
RDQS
RDQS
DUT
VTT = VDDQ/2
Timing
reference
point
25Ω
<AC Timing Reference Load>
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ
DUT
DQ
Output
Test point
DQS, DQS
RDQS, RDQS
VTT = VDDQ/2
25Ω
<Slew Rate Test Load>
22 of 29
Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally
to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
VIH(dc)
VIL(dc)
VIH(ac)
DQ
DM
D
D
D
D
t
VIL(ac)
t
t
DH
DH
DS
t
DS
VIH(ac)
VIH(dc)
DMin
DMin
DMin
DMin
VIL(ac)
VIL(dc)
<Data input (write) timing>
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
<Data output (read) timing>
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
tester correlation.
may be guaranteed by device design or
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
23 of 29
Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
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512Mb DDR2 SDRAM
15.0 Specific Notes for dedicated AC parameters
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied.
12. For DDR2-533/400, A minimum of two clocks (2*tCK) is required irrespective of operating frequency.
For DDR2-800/667, tnPARAM=RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specification are satisfied.
13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns.
14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
15. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns.
16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns
in differential strobe mode and a slew rate of 1V/ns in single ended mode.
17. tDS and tDH derating Values
∆tDS, ∆tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
125
45
21
0
-
-
-
-
-
-
125
83
0
-11
-
-
-
-
-
45
21
0
-14
-
-
-
-
-
125
83
0
-11
-25
-
-
-
-
45
21
0
-14
-31
-
-
-
-
-
95
12
1
-13
-31
-
-
33
12
-2
-19
-42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83
0
-
-
-
-
-
-
24
13
-1
-19
-43
-
24
10
-7
-30
-59
-
DQ
Siew
rate
25
11
-7
-31
-74
-
22
5
-18
-47
-89
-
-
17
-6
-35
-77
17
-7
-50
6
-23
-65
-
5
-38
-
V/ns
-19
-62
-11
-53
-
-
-
-
-
-
-127 -140 -115 -128 -103 -116
∆tDS, ∆tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
100
45
21
0
-
-
-
-
-
-
100
45
21
0
-14
-
-
-
-
-
100
67
0
-5
-13
-
-
-
-
45
21
0
-14
-31
-
-
-
-
-
79
12
7
-1
-10
-
-
33
12
-2
-19
-42
-
-
-
24
19
11
2
-10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
17
-6
-35
-77
-140
-
-
-
-
-
38
26
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
67
0
-
-
-
-
-
-
67
0
-5
-
-
-
24
10
-7
-30
-59
-
DQ
Slew
rate
31
23
14
2
-24
-
22
5
-18
-47
-89
-
-
35
26
14
-12
-52
6
-
-
V/ns
-23
-65
-128
38
12
-28
-11
-53
-116
-
-
-
-
-
-
-
-40
For all input signals the total tDS (setup time) and tDH(hold time) required is calculated by adding the datasheet tDS(base) and tDH(base) value to the
delta tDS and delta tDH derating value respectively. Example: tDS(total setup time)= tDS(base) + delta tDS.
24 of 29
Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
∆tDS1, ∆tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table)
DQS Single-ended Slew Rate
0.9 V/ns 0.8 V/ns 0.7 V/ns
2.0 V/ns
1.5 V/ns
1.0 V/ns
0.6 V/ns
0.5 V/ns
0.4 V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
1
188
1
188
1
167
125
42
31
-
1
146
125
83
69
-
1
125
83
0
1
63
42
0
1
-
1
-
1
-
1
-
1
-
1
-
1
-
-
1
-
1
-
1
-
1
-
-
-
-
-
-
1
-
-
-
-
-
-
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
146
167
81
-2
-13
-27
-45
-
43
1
-
-
-
-
-
-
-
-
63
-
125
-7
-18
-32
-50
-74
-
-13
-27
-44
-67
-96
-
-
-
-
-
-
DQ
Slew
rate
-
-
-
-
-
-
-11
-25
-
-14
-31
-
-13
-30
-53
-
-29
-43
-61
-85
-45
-62
-85
-
-
-
-
-
-60
-78
-86
-
-
-
-
-
-109 -108 -152
V/ns
-
-
-
-
-
-114 -102 -138 -138 -181 -183 -246
-
-
-
-
-
-
-
-128 -156 -145 -180 -175 -223 -226 -288
-210 -243 -240 -286 -291 -351
-
-
-
-
-
-
-
-
-
-
-
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the
∆tDS and ∆tDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ∆tDS.
25 of 29
Rev. 1.9 March 2007
K4T51043QC
K4T51083QC
K4T51163QC
512Mb DDR2 SDRAM
18. tIS and tIH (input setup and hold) derating.
tIS, tIH Derating Values for DDR2-400, DDR2-533
CK,CK Differential Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
Units
Notes
∆tIS
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+217
+209
+197
+180
+155
+113
+30
∆tIH
+124
+119
+113
+105
+75
+51
+30
+16
-1
∆tIS
+247
+239
+227
+210
+185
+143
+60
∆tIH
+154
+149
+143
+135
+105
+81
60
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
+187
+179
+167
+150
+125
+83
0
-11
-25
-43
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-14
-31
-54
+19
+5
-13
+49
+35
+17
+46
+29
+6
Command/Ad-
dress Slew
rate
(V/ns)
-24
-67
-83
-37
-80
-53
-95
-7
-50
-23
-65
-110
-175
-285
-350
-525
-800
-125
-188
-292
-375
-500
-708
-145
-255
-320
-495
-770
-158
-262
-345
-470
-678
-115
-225
-290
-465
-740
-128
-232
-315
-440
-648
∆tIS and ∆tIH Derating Values for DDR2-667, DDR2-800
CK,CK Differential Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
Units
Notes
∆tIS
+150
+143
+133
+120
+100
+67
0
-5
-13
-22
-34
∆tIH
+94
+89
+83
+75
+45
+21
0
-14
-31
-54
-83
-125
-188
-292
-375
-500
-708
-1125
∆tIS
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
-4
-30
-70
-138
-170
-295
-487
-970
∆tIH
+124
+119
+113
+105
+75
+51
+30
+16
-1
-24
-53
-95
-158
-262
-345
-470
-678
-1095
∆tIS
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+26
∆tIH
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Command/Ad-
dress Slew
rate
(V/ns)
-23
-65
-60
0
-40
-100
-168
-200
-325
-517
-1000
-128
-232
-315
-440
-648
-1065
-108
-140
-265
-457
-940
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta
tIS and delta tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + delta tIS
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19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
20. MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater
than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the
clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.
21. tQH = tHP – tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately,
due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers.
22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate
mismatch between DQS / DQS and associated DQ in any given cycle.
23. tDAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up.
WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer
tCK refers to the application clock period.
Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.
tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
24. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during
precharge power-down, a specific procedure is required as described in DDR2 device operation
25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
26. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Following figure shows a method to calculate the point when device
is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not
critical as long as the calculation is consistent.
28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),
or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is
consistent.
These notes are referenced in the “Timing parameters by speed grade” tables for DDR2-400/533/667 and DDR2-800.
VTT + 2x mV
VTT + x mV
VOH + x mV
VOH + 2x mV
tLZ
tHZ
tRPRE begin point
tRPST end point
VTT - x mV
VTT - 2x mV
VOL + 2x mV
VOL + x mV
T1
T2
T2
T1
tHZ,tRPST end point = 2*T1-T2
tLZ,tRPRE begin point = 2*T1-T2
<Test method for tLZ, tHZ, tRPRE and tRPST>
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29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the
differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for
a falling signal applied to the device under test.
30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(dc) level to the
differential data strobe crosspoint for a rising signal and VIL(dc) to the differential data strobe crosspoint for a falling signal applied to the device under
test.
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
< Differential Input waveform timing >
31. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the
device under test.
32. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the
device under test.
CK
CK
tIH
tIH
tIS
tIS
V
V
V
V
V
V
V
DDQ
min
min
IH(ac)
IH(dc)
REF(dc)
max
max
IL(dc)
IL(ac)
SS
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any CKE transition, CKE may not change from its valid level during the time period of
tIS + 2*tCK + tIH.
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