K4X56323PN-8GC6000 [SAMSUNG]
DDR DRAM, 8MX32, 5.5ns, CMOS, PBGA90, HALOGEN AND LEAD FREE, FBGA-90;
| 型号： | K4X56323PN-8GC6000 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 8MX32, 5.5ns, CMOS, PBGA90, HALOGEN AND LEAD FREE, FBGA-90 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总24页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev. 1.0, Mar. 2010
K4X56323PN
256Mb N-die Mobile DDR SDRAM
8x13, 90FBGA, 8M x32
VDD / VDDQ = 1.8V / 1.8V
datasheet
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SPECIFICATIONS WITHOUT NOTICE.
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- 1 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
Revision History
Revision No.
History
Draft Date
Nov. 27, 2009
Mar. 02, 2010
Remark
Target
Editor
J.Y.Bae
J.Y.Bae
0.0
0.5
- First version for target specification.
- Preliminary datasheet.
- Corrected errata.
Preliminary
- Revised DC characteristics.
- Final datasheet.
0.9
Mar. 30, 2010
Preliminary
J.Y.Bae
- Corrected errata.
- Added note for Functional truth table.
- 2 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
Table Of Contents
256Mb N-die Mobile DDR SDRAM
1. FEATURES ...............................................................................................................................................................4
2. OPERATING FREQUENCY......................................................................................................................................4
3. ADDRESS CONFIGURATION..................................................................................................................................4
4. ORDERING INFORMATION.....................................................................................................................................4
5. FUNCTIONAL BLOCK DIAGRAM.............................................................................................................................5
6. PACKAGE DIMENSION AND PIN CONFIGURATION .............................................................................................6
7. INPUT/OUTPUT FUNCTION DESCRIPTION...........................................................................................................7
8. FUNCTIONAL DESCRIPTION..................................................................................................................................8
9. MODE REGISTER DEFINITION...............................................................................................................................9
9.1 Mode Register Set(MRS).................................................................................................................................... 9
9.2 Extended Mode Register Set(EMRS) ................................................................................................................. 11
9.3 Internal Temperature Compensated Self Refresh (TCSR) ................................................................................. 12
9.4 Partial Array Self Refresh (PASR) ...................................................................................................................... 12
10. ABSOLUTE MAXIMUM RATINGS..........................................................................................................................13
11. DC OPERATING CONDITIONS..............................................................................................................................13
12. DC CHARACTERISTICS ........................................................................................................................................14
13. AC OPERATING CONDITIONS & TIMMING SPECIFICATION .............................................................................15
14. AC TIMMING PARAMETERS & SPECIFICATIONS...............................................................................................16
15. AC OPERATING TEST CONDITIONS (VDD = 1.7V to 1.95V, Tc = -25 to 85°C)...................................................18
16. INPUT/OUTPUT CAPACITANCE (VDD=1.8, VDDQ=1.8V, TC = 25°C, f=100MHz) .............................................19
17. AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR ADDRESS & CONTROL PINS ..................................20
18. AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR CLK, DQ, DQS AND DM PINS ..................................20
19. COMMAND TRUTH TABLE....................................................................................................................................21
20. FUNCTIONAL TRUTH TABLE................................................................................................................................22
- 3 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
1. FEATURES
• VDD/VDDQ = 1.8V/1.8V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
- CAS Latency ( 2, 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
• EMRS cycle with address key programs
- Partial Array Self Refresh ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8 )
• Internal Temperature Compensated Self Refresh
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• DM0 - DM3 for write masking only.
• Clock Stop capability.
• Auto refresh duty cycle
- 15.6us for -25 to 85 °C
2. OPERATING FREQUENCY
DDR400
DDR333
83Mhz
Speed @CL21)
-
Speed @CL31)
200Mhz
166Mhz
NOTE :
1) CAS Latency
3. ADDRESS CONFIGURATION
Organization
Bank Address
Row Address
Column Address
A0 - A8
8Mx32
BA0,BA1
A0 - A11
- DM is internally loaded to match DQ and DQS identically.
4. ORDERING INFORMATION
Part No.
Max Freq.
Interface
LVCMOS
Package
90FBGA
K4X56323PN-8GC6
166MHz(CL=3),83MHz(CL=2)
K4X56323PN-8GD8
200MHz(CL=3, tRCD=3, tRP=3)
- K4X56323PN-8GC6(D8) : 90FBGA Pb(Pb Free, Halogen Free)
- K4X56323PN-8GC6(D8) : Extended Temperature(-25 °C ~ 85 °C)
- K4X56323PN-8GC6(D8) : 166MHz(CL=3) / 83MHz(CL=2)
- K4X56323PN-8GC6(D8) : 200MHz(CL=3, tRCD=3, tRP=3)
- 4 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
5. FUNCTIONAL BLOCK DIAGRAM
LWE
LDM
32
CK, CK
Data Input Register
Serial to parallel
Bank Select
64
2Mx64
2Mx64
2Mx64
2Mx64
64
32
X32
DQi
CK, CK
ADD
Column Decoder
Latency & Burst Length
Data Strobe
Programming Register
LWCBR
LCKE
LRAS LCBR
LWE
LCAS
LDM
Timing Register
DM Input Register
CK, CK
CKE
CS
RAS
CAS
WE
DM
- 5 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
6. PACKAGE DIMENSION AND PIN CONFIGURATION
< Bottom View*1
>
< Top View*2
>
E1
90Ball(6x15) FBGA
9
8
7
6
5
4
3
2
1
1
2
3
7
VDDQ
DQ17
DQ19
DQ21
DQ23
NC
8
9
A
B
C
D
E
F
A
B
C
D
E
F
VSS
DQ31
DQ29
DQ27
DQ25
DQS3
DM3
CK
VSSQ
DQ30
DQ28
DQ26
DQ24
NC
DQ16
DQ18
DQ20
DQ22
DQS2
DM2
CAS
BA0
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CKE
A9
VSSQ
VDDQ
VSSQ
VDDQ
VSS
G
H
J
G
H
J
CK
WE
RAS
BA1
A1
A11
NC
CS
A6
A7
A8
A10/AP
A2
A0
K
L
K
L
A4
DM1
DQS1
DQ9
DQ11
DQ13
DQ15
A5
DM0
DQS0
DQ6
DQ4
DQ2
DQ0
A3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
DQ8
DQ10
DQ12
DQ14
VSSQ
DQ7
DQ5
DQ3
DQ1
VDDQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
M
N
P
R
M
N
P
R
e
E
Ball Name
CK, CK
CS
Ball Function
*2: Top View
System Differential Clock
Chip Select
CKE
Clock Enable
A0 ~ A11
BA0 ~ BA1
RAS
Address
A
A1
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
z
b
CAS
*1: Bottom View
WE
< Top View*2
>
DM0~3
DQS0~3
DQ0 ~ 31
VDD/VSS
VDDQ/VSSQ
Data Input Mask
Data Strobe
#A1 Ball Origin Indicator
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit::mm]
Symbol
Min
Typ
-
Max
1.00
-
A
A1
E
-
0.25
-
7.90
8.00
6.40
13.00
11.20
0.80
0.50
-
8.10
-
E1
D
-
12.90
13.10
-
D1
e
-
-
0.45
-
-
b
0.55
0.10
z
- 6 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
7. INPUT/OUTPUT FUNCTION DESCRIPTION
Symbol
Type
Description
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK.
CK, CK
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and out-
put drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),
or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is synchronous for all functions except for disabling out-
puts, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE , are disabled during power-down
and self refresh mode which are contrived for low standby power consumption.
CKE
Input
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with mul-
tiple banks. CS is considered part of the command code.
CS
Input
Input
RAS, CAS, WE
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with
that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading inter-
nally, to match the DQ and DQS loading. For the x32, DM0 corresponds to the data on DQ0-DQ7 ; DM1 corresponds to
the data on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, DM3 corresponds to the data on DQ24-DQ31
DM0,DM1,
DM2,DM3
Input
Input
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is
being applied.
BA0, BA1
Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE
bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled
during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide
the op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register( mode register
or extended mode register ) is loaded during the MODE REGISTER SET command.
A [n : 0]
DQ
Input
I/O
I/O
-
Data Inputs/Outputs : Data bus
Data Strobes : Output with read data, input with write data. Edge-aligned with read data, centered in write data. it is
used to fetch write data. For the x32, DQS0 corresponds to the data on DQ0-DQ7 ; DQS1 corresponds to the data on
DQ8-DQ15,DQS2 corresponds to the data on DQ16-DQ23, DQS3 corresponds to the data on DQ24-DQ31
DQS0,DQS1,
DQS2,DQS3
NC
No Connect : No internal electrical connection is present.
VDDQ
VSSQ
VDD
Supply DQ Power Supply : 1.7V to 1.95V
Supply DQ Ground.
Supply Power Supply : 1.7V to 1.95V
Supply Ground.
VSS
- 7 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
8. FUNCTIONAL DESCRIPTION
POWER
ON
POWER
APPLIED
PARTIAL
SELF
REFRESH
SELF
REFRESH
PRECHARGE
ALL BANKS
REFS
REFSX
IDLE
MRS
REFA
CKEL
AUTO
EMRS
MRS
ALL BANKS
REFRESH
PRECHARGED
CKEH
ACT
POWER
DOWN
CKEH
POWER
DOWN
ROW
BURST STOP
ACTIVE
CKEL
WRITE
READ
WRITEA
READA
READ
WRITE
READ
WRITEA
READA
READA
PRE
PRE
WRITEA
READA
PRE
PRE
PRECHARGE
PREALL
Automatic Sequence
Command Sequence
Figure 1. State diagram
- 8 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
9. MODE REGISTER DEFINITION
9.1 Mode Register Set(MRS)
The mode register is designed to support the various operating modes of Mobile DDR SDRAM. It includes Cas latency, addressing mode, burst length,
test mode and vendor specific options to make Mobile DDR SDRAM useful for variety of applications. The mode register is written by asserting low on
CS, RAS, CAS and WE(The Mobile DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The states of
address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the mode register. Two clock cycles are
required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operation is executed
afterward, the mode register contents can be changed with the same command and two clock cycles. This command must be issued only when all banks
are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3,
Cas latency(read latency from column address) uses A4 ~ A6, A7 ~ A11 is used for test mode. BA0 and BA1 must be set to low for proper MRS opera-
tion. .
Address Bus
BA1
BA0
A11 ~ A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RFU1)
0
0
0
CAS Latency
BT
Burst Length
Mode Register
0
0
A3
Burst Type
Sequential
Interleave
0
1
A6
0
A5
0
A4
0
CAS Latency
Reserved
Reserved
2
A2
0
A1
0
A0
0
Burst Type
Reserved
0
0
1
0
0
1
2
0
1
0
0
1
0
4
0
1
1
3
0
1
1
8
1
0
0
Reserved
Reserved
Reserved
Reserved
1
0
0
16
1
0
1
1
0
1
Reserved
Reserved
Reserved
1
1
0
1
1
0
1
1
1
1
1
1
Figure 2. Mode Register Set
NOTE :
1) RFU(Reserved for future use) should stay "0" during MRS cycle
- 9 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
[Table 1] Burst address ordering for burst length
Burst
Length
Starting Address
(A3, A2, A1, A0)
Sequential Mode
Interleave Mode
xxx0
xxx1
xx00
xx01
xx10
xx11
x000
x001
x010
x011
x100
x101
x110
x111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0, 1
0, 1
2
4
1, 0
1, 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
8
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2
4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3
5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4
6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5
7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6
8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7
9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8
10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12
14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15
1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14
2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13
3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12
4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11
5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10
6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9
7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8
8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7
9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6
10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5
11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4
12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3
13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2
14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1
15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
16
- 10 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
9.2 Extended Mode Register Set(EMRS)
The extended mode register is designed to support for the desired operating modes of DDR SDRAM. The extended mode register is written by asserting
low on CS, RAS, CAS, WE and high on BA1 ,low on BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing
into the extended mode register). The state of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS and WE going low is written in the extended
mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished
and some read or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But
this command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A6 are used for driver
strength control. "High" on BA1 and"Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0 must be set to low
for proper EMRS operation. Refer to the table for specific codes.
Address Bus
A11 ~ A10/AP
BA1
BA0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RFU1)
0
0
DS
RFU1)
PASR
Mode Register
1
0
DS
PASR
A7
A6
0
A5
0
Driver Strength
A2
0
A1
A0
0
Refreshed Area
Full Array
1/2 Array
0
0
0
0
1
1
1
1
Full
1/2
1/4
1/8
3/4
3/8
5/8
7/8
0
0
1
1
0
0
1
1
0
1
0
1
1
0
0
0
1/4 Array
1
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
1
0
0
1
1
1
1
0
1
0
1
1
1
1
Figure 3. Extended Mode Register Set
NOTE :
1) RFU(Reserved for future use) should stay "0" during EMRS cycle
- 11 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
9.3 Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, this Mobile DRAM includes the internal temperature sensor and control units to control the self refreshcycle auto-
matically according to the real device temperature.
2. TCSR ranges for IDD6 shown in the table are as an example only. Max IDD6 valus for 45°C, 85°C are guaranteed. Typical values for 85 °C, 70 °C, 45
°C and 15 °C are obtained from device characterization.
3. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (IDD6)
Full Array
1/2 Array
1/4 Array
Unit
Temperature Range
Typ.
250
170
100
90
Max
Typ.
200
140
85
Max
Typ.
170
120
80
Max
85 °C
70 °C
45 °C
15 °C
300
250
220
uA
150
135
130
75
70
9.4 Partial Array Self Refresh (PASR)
1. In order to save power consumption, Mobile DDR SDRAM includes PASR option.
2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array.
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
- 1/4 Array
- Full Array
- 1/2 Array
Partial Self Refresh Area
Figure 4. EMRS code and TCSR , PASR
- 12 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
10. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 2.7
-0.5 ~ 2.7
-0.5 ~ 2.7
-55 ~ +150
1.0
Unit
V
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Storage temperature
V
VDDQ
TSTG
PD
V
°C
W
Power dissipation
IOS
Short circuit current
50
mA
NOTE :
1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
2) Functional operation should be restricted to recommend operation condition.
3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
11. DC OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, Tc = -25°C to 85°C)
Parameter
Symbol
Min
1.7
Max
Unit
V
Note
Supply voltage(for device with a nominal VDD of 1.8V)
VDD
1.95
1
1
VDDQ
I/O Supply voltage
1.7
1.95
V
0.8 x VDDQ
0.7 x VDDQ
VDDQ+0.3
VDDQ+0.3
0.2 x VDDQ
0.3 x VDDQ
Input logic high voltage ( for Add.)
Input logic high voltage (for Data)
Input logic low voltage ( for Add.)
Input logic low voltage (for Data)
Output logic high voltage
Output logic low voltage
V
VIH(DC)
2
2
V
-0.3
-0.3
V
VIL(DC)
V
VOH(DC)
VOL(DC)
II
0.9 x VDDQ
IOH = -0.1mA
IOL = 0.1mA
3
-
V
0.1 x VDDQ
-
V
Input leakage current
-2
-5
2
5
uA
uA
IOZ
Output leakage current
NOTE :
1) Under all conditions, VDDQ must be less than or equal to VDD.
2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
3) Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
- 13 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
12. DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C)
Parameter
Symbol
Test Condition
DDR333 DDR400 Unit Note
Operating Current
(One Bank Active)
tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands; address
inputs are SWITCHING; data bus inputs are STABLE
IDD0
45
0.3
0.3
10
4
55
0.3
0.3
12
5
mA
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2P
IDD2PS
IDD2N
Precharge Standby Current
in power-down mode
mA
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge Standby Current
in non power-down mode
mA
mA
mA
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2NS
IDD3P
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
3
3
Active Standby Current
in power-down mode
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3PS
IDD3N
2
2
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
12
8
15
10
Active Standby Current
in non power-down mode
(One Bank Active)
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3NS
one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts;
I
=0 mA
IDD4R
80
90
OUT
Operating Current
(Burst Mode)
address inputs are SWITCHING; 50% data change each burst transfer
mA
mA
one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
IDD4W
IDD5
60
70
tRC ≥ tRFC; tCK = tCKmin ; burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Refresh Current
130
130
1
Values
TCSR Range
Typ.
250
170
100
90
Max.
85°C
70°C
45°C
15°C
85°C
70°C
45°C
15°C
85°C
70°C
45°C
15°C
300
Full Array
1/2 Array
1/4 Array
uA
uA
uA
150
250
135
220
130
CKE is LOW; t CK = t CKmin ;
200
140
85
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Self Refresh Current
IDD6
75
170
120
80
70
NOTE :
1) IDD5 is measured in the below test condition.
Density
tRFC
128Mb
256Mb
512Mb
1Gb
2Gb
Unit
80
80
110
140
140
ns
2) The IDD values need to be measured after devices are properly initialized following all sequences including MRS and EMRS in "Power Up Sequence" section in the specifi-
cation.
3) Input slew rate is 1V/ns.
4) Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ ;
HIGH is defined as V IN ≥ 0.9 * VDDQ ;
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
5) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
Please contact Samsung for more information.
- 14 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
13. AC OPERATING CONDITIONS & TIMMING SPECIFICATION
Parameter/Condition
Symbol
Min
Max
Unit
Note
VIH(AC)
0.8 x VDDQ
VDDQ+0.3
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
Input Crossing Point Voltage, CK and CK inputs
V
1
1
2
VIL(AC)
VIX(AC)
0.2 x VDDQ
0.6 x VDDQ
-0.3
V
0.4 x VDDQ
V
NOTE :
1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
2) The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
- 15 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
14. AC TIMMING PARAMETERS & SPECIFICATIONS
DDR400
DDR333
Parameter
Symbol
Unit
Note
Min
12.0
5
Max
Min
12.0
6
Max
CL=2
CL=3
t
Clock cycle time
ns
1,2
CK
t
Row cycle time
55
60
ns
ns
ns
ns
ns
ns
-
RC
t
Row active time
RAS to CAS delay
Row precharge time
40
15
15
10
12
-
70,000
42
18
18
12
12
-
70,000
RAS
t
RCD
t
RP
t
Row active to Row active delay
Write recovery time
RRD
t
WR
t
Last data in to Active delay
Last data in to Read command
3
DAL
t
2
1
tCK
CDLR
1
1
t
Col. address to Col. address delay
tCK
CCD
t
Clock high level width
Clock low level width
0.45
0.45
0.55
0.55
0.45
0.55
tCK
tCK
CH
t
0.45
0.55
8
CL
CL=2
CL=3
CL=2
CL=3
2
2
2
2
DQ Output data access time
from CK/CK
t
ns
4
AC
2
2
5
5.5
8
DQS Output data access time
from CK/CK
t
ns
ns
DQSCK
5
5.5
0.5
1.1
1.1
0.6
t
Data strobe edge to ouput data edge
Read Preamble
0.4
1.1
1.1
0.6
DQSQ
CL=2
CL=3
0.5
0.9
0.4
0.5
0.9
0.4
t
tCK
RPRE
t
Read Postamble
tCK
tCK
ns
RPST
t
CK to valid DQS-in
0.75
0
1.25
0.75
0
1.25
DQSS
t
DQS-in setup time
5
WPRES
t
DQS-in hold time
0.25
0.4
0.4
0.2
0.2
0.25
0.4
0.4
0.2
0.2
0.9
tCK
tCK
tCK
tCK
tCK
tCK
WPREH
t
DQS-in high level width
DQS-in low level width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS-in cycle time
0.6
0.6
0.6
0.6
DQSH
t
DQSL
t
DSS
t
DSH
t
0.9
0.9
1.1
1.1
DSC
fast slew rate
slow slew rate
fast slew rate
slow slew rate
7
8
7
8
t
Address and Control Input setup time
1.1
ns
ns
IS
1.1
0.9
t
Address and Control Input hold time
Address & Control input pulse width
DQ & DM setup time to DQS
1.1
2.2
0.6
IH
1.1
t
2.2
IPW
fast slew rate
slow slew rate
fast slew rate
slow slew rate
0.48
0.58
0.48
0.58
1.2
6,7
6,8
6,7
6,8
t
ns
ns
DS
t
DQ & DM hold time to DQS
0.6
DH
t
DQ & DM input pulse width
1.2
1.0
ns
ns
DIPW
t
DQ & DQS low-impedence time from CK/CK
DQ & DQS high-impedence time from CK/CK
DQS write postamble time
1.0
LZ
t
5
5.5
0.6
ns
HZ
t
0.4
0.6
0.4
tCK
tCK
ms
tCK
tCK
WPST
t
DQS write preamble time
0.25
0.25
WPRE
t
Refresh interval time
64
64
REF
t
Mode register set cycle time
Power down exit time
2
2
2
1
MRD
t
PDEX
- 16 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
DDR400
DDR333
Parameter
Symbol
Unit
Note
Min
2
Max
Min
2
Max
t
CKE min. pulse width(high and low pulse width)
Auto refresh cycle time
tCK
ns
CKE
t
72
72
9
RFC
t
Exit self refresh to active command
120
120
ns
XSR
t
-
tHPmin-
tQHS
HP
t
Data hold from DQS to earliest DQ edge
Data hold skew factor
ns
ns
QH
t
QHS
t
0.5
0.65
QHS
tCLmin
or
tCLmin
or
t
Clock half period
ns
HP
tCHmin
tCHmin
NOTE :
1) tCK(max) value is measured at 100ns.
2) The only time that the clock Frequency is allowed to be changed is during clock stop, power-down, self-refresh modes.
3) In case of below 33MHz (tCK=30ns) condition, SEC could support tDAL(=2*tCK).
tDAL =(tWR/tCK) + (tRP/tCK)
4) tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C).
tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).
tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page).
5) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no
writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Data Rise/Fall Rate
ΔtDS
(ps)
0
ΔtDH
(ps)
0
(ns/V)
0
±0.25
±0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For
example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V.
7) Input slew rate 1.0 V/ ns.
8) Input slew rate 0.5V/ns and < 1.0V/ns.
9) Maximum burst refresh cycle : 8
- 17 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
15. AC OPERATING TEST CONDITIONS (VDD = 1.7V to 1.95V, Tc = -25 to 85°C)
Parameter
Value
Unit
0.8 x VDDQ / 0.2 x VDDQ
AC input levels (Vih/Vil)
V
0.5 x VDDQ
Input timing measurement reference level
Input signal minimum slew rate
Output timing measurement reference level
Output load condition
V
1.0
V/ns
V
0.5 x VDDQ
See Figure 6
1.8V
13.9KΩ
- VOH (DC) = 0.9 x VDDQ, IOH = -0.1mA
- VOL (DC) = 0.1 x VDDQ, IOL = 0.1mA
Output
20pF
10.6KΩ
Figure 5. DC Output Load Circuit
Vtt=0.5 x VDDQ
50Ω
Output
Z0=50Ω
Test load values need to be proportional to the driver strength
which is set by the controller.
- Test load for Full Driver Strength Buffer (20pF)
- Test load for Half Driver Strength Buffer (10pF)
Figure 6. AC Output Load Circuit1),2)
NOTE :
1) The circuit shown above represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representa-
tion of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will used IBIS or other simulations tools to correlate
the timing reference load to system environment. Manufacturers will correlate to their poduction test conditions (generally a coaxial transmission line terminated at the tester
electronics). For the half strength driver with a nominal 10pF load parameters tAC and tQH are expected to be in ther same range. However, these parameters are not subject
to production test but are estimated by design / characterization. Use of IBIS or other simulation tolls for system design validation is suggested.
2) Based on nominal impedance at 0.5 x VDDQ.
The impedence for Half(1/2) Driver Strength is designed 55ohm. And for other Driver Strength, it is designed proportionally.
- 18 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
16. INPUT/OUTPUT CAPACITANCE (VDD=1.8, VDDQ=1.8V, TC = 25°C, f=100MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance
(A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
1.5
3.0
pF
Input capacitance( CK, CK )
CIN2
COUT
CIN3
1.5
2.0
2.0
3.5
4.5
4.5
pF
pF
pF
Data & DQS input/output capacitance
Input capacitance(DM)
- 19 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
17. AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR ADDRESS & CONTROL PINS
Parameter
Specification
Maximum peak Amplitude allowed for overshoot area
Maximum peak Amplitude allowed for undershoot area
Maximum overshoot area above VDD
0.9V
0.9V
3V-ns
Maximum undershoot area below VSS
3V-ns
Maximum Amplitude
Overshoot Area
VDD
VSS
Volts
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 7: AC Overshoot and Undershoot Definition for Address and Control Pins
18. AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR CLK, DQ, DQS AND DM PINS
Parameter
Specification
Maximum peak Amplitude allowed for overshoot area
Maximum peak Amplitude allowed for undershoot area
Maximum overshoot area above VDDQ
0.9V
0.9V
3V-ns
Maximum undershoot area below VSSQ
3V-ns
Maximum Amplitude
Overshoot Area
VDDQ
VSSQ
Volts
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 8: AC Overshoot and Undershoot Definition for CLK, DQ, DQS and DM Pins
- 20 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
19. COMMAND TRUTH TABLE
A11
A9~A0
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
Register
Refresh
Mode Register Set
Auto Refresh
H
X
H
L
L
L
L
L
OP CODE
1, 2
3
H
L
L
L
H
X
X
Entry
3
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
X
3
Bank Active & Row Addr.
H
V
V
Row Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Entry
L
H
L
Column
Address
(A0~A8)
4
4
Read &
Column Address
H
H
X
X
L
L
H
H
L
L
H
L
Column
Address
(A0~A8)
4
Write &
Column Address
V
H
4, 6
H
L
L
H
X
L
H
L
H
X
H
H
X
H
L
X
L
Deep Power Down
X
X
Exit
Burst Stop
Bank Selection
All Banks
H
7
5
V
X
L
Precharge
H
X
L
L
H
L
X
H
H
L
X
H
X
X
H
X
H
X
X
H
X
H
X
X
H
X
H
X
H
X
X
H
X
H
Entry
H
L
L
H
L
Active Power Down
X
X
Exit
X
H
L
Entry
H
Precharge Power Down
DM
H
L
Exit
L
H
H
H
X
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
NOTE :
1) OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2) EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3) Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4) BA0 ~ BA1 : Bank select addresses.
5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6) During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7) Burst stop command is valid at every burst length.
8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM.
- 21 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
20. FUNCTIONAL TRUTH TABLE
Current State
CS
RAS
CAS
WE
Address
Command
Burst Stop
READ/WRITE
Active
Action
ILLEGAL2)
L
H
H
L
X
ILLEGAL2)
L
H
L
X
BA, CA, A10
L
L
H
H
L
BA, RA
Bank Active, Latch RA
PRECHARGE
STANDBY
ILLEGAL4)
L
L
H
BA, A10
PRE/PREA
Refresh
AUTO-Refresh5)
L
L
L
H
L
X
Mode Register Set5)
NOP
L
L
L
Op-Code, Mode-Add
X
MRS
L
H
H
L
Burst Stop
Begin Read, Latch CA,
Determine Auto-Precharge
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ/READA
Begin Write, Latch CA,
Determine Auto-Precharge
WRITE/WRITEA
ACTIVE
STANDBY
Bank Active/ILLEGAL2)
Precharge/Precharge All
ILLEGAL
L
L
L
L
L
L
L
L
L
H
H
H
L
H
L
BA, RA
Active
PRE/PREA
Refresh
BA, A10
H
L
X
L
Op-Code, Mode-Add
X
MRS
ILLEGAL
H
L
Burst Stop
Terminate Burst
Terminate Burst, Latch CA,
Begin New Read, Determine
L
H
L
H
BA, CA, A10
READ/READA
Auto-Precharge3)
L
L
H
L
L
L
BA, CA, A10
BA, RA
WRITE/WRITEA
Active
ILLEGAL
READ
Bank Active/ILLEGAL2)
H
H
Terminate Burst, Precharge10)
ILLEGAL
L
L
L
L
L
L
H
L
L
H
L
BA, A10
PRE/PREA
Refresh
X
L
L
Op-Code, Mode-Add
X
MRS
ILLEGAL
H
H
L
Burst Stop
ILLEGAL
Terminate Burst With DM=High, Latch
CA, Begin Read, Determine Auto-
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ/READA
Precharge3)
Terminate Burst, Latch CA,
Begin new Write, Determine Auto-
WRITE/WRITEA
WRITE
Precharge3)
Bank Active/ILLEGAL2)
L
L
L
L
H
H
H
L
BA, RA
Active
Terminate Burst With DM=High,
Precharge10)
BA, A10
PRE/PREA
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
X
Op-Code, Mode-Add
X
Refresh
MRS
ILLEGAL
ILLEGAL
ILLEGAL
6)
H
H
H
L
H
L
L
Burst Stop
READ/READA
WRITE/WRITEA
Active
H
L
BA, CA, A10
BA, CA, A10
BA, RA
READ with
AUTO
PRECHARGE6)
L
ILLEGAL
6)
H
H
L
H
L
(READA)
L
BA, A10
PRE/PREA
Refresh
6)
L
H
L
X
ILLEGAL
ILLEGAL
L
L
Op-Code, Mode-Add
MRS
- 22 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
Current State
CS
L
RAS
H
CAS
H
WE
L
Address
Command
Burst Stop
READ/READA
WRITE/WRITEA
Active
Action
ILLEGAL
7)
X
BA, CA, A10
BA, CA, A10
BA, RA
L
H
L
H
L
WRITE with AUTO
RECHARGE7)
L
H
L
7)
L
L
H
H
L
7)
(WRITEA)
L
L
H
BA, A10
PRE/PREA
Refresh
7)
L
L
L
H
L
X
ILLEGAL
ILLEGAL
L
L
L
Op-Code, Mode-Add
X
MRS
ILLEGAL2)
ILLEGAL2)
ILLEGAL2)
L
H
H
L
Burst Stop
L
L
H
L
L
X
H
BA, CA, A10
BA, RA
READ/WRITE
Active
H
PRECHARGING
(DURING tRP)
NOP4)(Idle after tRP)
ILLEGAL
L
L
L
L
L
L
H
L
L
H
L
BA, A10
PRE/PREA
Refresh
MRS
X
L
L
Op-Code, Mode-Add
X
ILLEGAL
ILLEGAL2)
ILLEGAL2)
ILLEGAL2)
H
H
L
Burst Stop
L
L
H
L
L
X
H
BA, CA, A10
BA, RA
READ/WRITE
Active
ROW
H
ACTIVATING
(FROM ROW
ACTIVE TO
tRCD)
BA, A10
ILLEGAL2)
L
L
H
L
PRE/PREA
L
L
L
L
L
L
L
H
L
L
X
Refresh
MRS
ILLEGAL
ILLEGAL
Op-Code, Mode-Add
X
ILLEGAL2)
H
H
Burst Stop
ILLEGAL2)
WRITE
L
L
L
H
H
L
L
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
READ
WRITE
Active
WRITE
RECOVERING
(DURING tWR
OR tCDLR)
ILLEGAL2)
H
H
ILLEGAL2)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
BA, A10
PRE/PREA
Refresh
X
L
L
Op-Code, Mode-Add
MRS
H
H
L
H
L
L
X
BA, CA, A10
BA, RA
Burst Stop
READ/WRITE
Active
X
H
L
RE-
FRESHING
H
H
L
L
BA, A10
PRE/PREA
Refresh
L
H
L
X
L
L
Op-Code, Mode-Add
X
MRS
H
H
L
H
L
L
Burst Stop
READ/WRITE
Active
X
H
BA, CA, A10
BA, RA
MODE
REGISTER
SETTING
H
BA, A10
L
L
H
L
PRE/PREA
ILLEGAL
L
L
L
L
L
L
H
L
X
Refresh
MRS
ILLEGAL
ILLEGAL
Op-Code, Mode-Add
- 23 -
Rev. 1.0
K4X56323PN-8GC6
K4X56323PN-8GD8
datasheet Mobile DDR SDRAM
CKE
Current State
n-1
CKE
n
CS
RAS
CAS
WE
Add
Action
L
L
H
H
H
H
H
L
H
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh
Exit Self-Refresh
L
L
L
ILLEGAL
SELF-
REFRESHING8)
L
X
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
X
L
ILLEGAL
L
X
X
X
H
X
X
L
X
X
X
X
X
X
L
NOP (Maintain Self-Refresh)
Exit Power Down(Idle after tPDEX)
NOP (Maintain Power Down)
L
H
L
POWER
DOWN
L
Exit Deep Power Down10)
NOP (Maintain Deep Power Down)
Refer to Function Truth Table
Enter Self-Refresh
L
H
L
DEEP POWER
DOWN
L
H
H
H
H
H
H
H
H
L
H
L
L
H
L
X
H
H
H
H
L
X
H
H
H
L
Enter Power Down
L
Enter Power Down
ALL BANKS
IDLE9)
L
L
Enter Deep Power Down
ILLEGAL
L
L
L
L
L
X
X
X
ILLEGAL
L
L
X
X
ILLEGAL
X
X
X
Refer to Current State=Power Down
(H=High Level, L=Low level, X=Don′t Care)
NOTE :
1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2) ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
(ILLEGAL = Device operation and/or data integrity are not guaranteed.)
3) Must satisfy bus contention, bus turn around and write recovery requirements.
4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA.
5) ILLEGAL if any bank is not idle.
6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information.
7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information.
8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously.
A minimum setup time must be satisfied before issuing any command other than EXIT.
9) Power-Down, Self-Refresh can be entered only from All Bank Idle state.
- 24 -
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