K5A3B41YBA-K370 [SAMSUNG]

Memory Circuit, 2MX16, CMOS, PBGA66, 8 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, TBGA-66;
K5A3B41YBA-K370
型号: K5A3B41YBA-K370
厂家: SAMSUNG    SAMSUNG
描述:

Memory Circuit, 2MX16, CMOS, PBGA66, 8 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, TBGA-66

静态存储器 内存集成电路
文件: 总44页 (文件大小:509K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
K5A3x41YT(B)A  
MCP MEMORY  
Document Title  
Multi-Chip Package MEMORY  
32M Bit (2Mx16) Dual Bank NOR Flash Memory / 4M(256Kx16) Full CMOS SRAM  
Revision History  
Revision No. History  
Draft Date  
Remark  
0.0  
1.0  
Initial Draft  
August 28, 2001  
Preliminary  
Final Specification  
November 13, 2001 Final  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.  
Revision 1.0  
November 2001  
- 1 -  
K5A3x41YT(B)A  
MCP MEMORY  
Multi-Chip Package MEMORY  
32M Bit (2Mx16) Dual Bank NOR Flash Memory / 4M(256Kx16) Full CMOS SRAM  
FEATURES  
GENERAL DESCRIPTION  
· Power Supply voltage : 2.7V to 3.3V  
· Organization  
- Flash : 2,097,152 x 16 bit  
- SRAM : 262,144 x 16 bit  
· Access Time (@2.7V)  
The K5A3x41YT(B)M featuring single 3.0V power supply is a  
Multi Chip Package Memory which combines 32Mbit Dual Bank  
Flash and 4Mbit fCMOS SRAM.  
The 32Mbit Flash memory is organized as 2M x16 bit and 4Mbit  
SRAM is organized as 256K x16 bit. The memory architecture of  
flash memory is designed to divide its memory arrays into 71  
blocks and this provides highly flexible erase and program capa-  
bility. This device is capable of reading data from one bank while  
programming or erasing in the other bank with dual bank organi-  
zation.  
- Flash : 80 ns, SRAM : 70 ns  
· Power Consumption (typical value)  
- Flash Read Current : 14 mA (@5MHz)  
Program/Erase Current : 15 mA  
Standby mode/Autosleep mode : 0.2 mA  
Read while Program or Read while Erase : 25 mA  
- SRAM Operating Current : 17 mA  
Standby Current : 0.5 mA  
· Secode(Security Code) Block : Extra 32KW Block (Flash)  
· Support Common Flash Memory Interface  
· Block Group Protection / Unprotection (Flash)  
· Flash Bank Size : 8Mb / 24Mb , 16Mb / 16Mb  
· Flash Endurance : 100,000 Program/Erase Cycles Minimum  
· SRAM Data Retention : 1.5 V (min.)  
· Industrial Temperature : -40°C ~ 85°C  
· Package : 66-ball TBGA Type - 8 x 11mm, 0.8 mm pitch  
1.2mm (Max.) Thickness  
The Flash memory performs a program operation in units of 16  
bits (Word) and erases in units of a block. Single or multiple  
blocks can be erased. The block erase operation is completed  
for typically 0.7sec.  
The 4Mbit SRAM supports low data retention voltage for battery  
backup operation with low data retention current.  
The K5A3x41YT(B)M is suitable for the memory of mobile com-  
munication system to reduce mount area. This device is available  
in 66-ball TBGA Type package.  
BALL CONFIGURATION & DESCRIPTION  
1
2
3
4
5
6
7
8
9
10  
11  
12  
A
A11  
A8  
A15  
A10  
NC  
NC  
A14  
A9  
A13  
A12  
A20  
A16  
WE  
Vss  
NC  
NC  
Vcc  
F
F
DQ15 WE  
B
C
D
E
F
DQ14  
DQ4  
DQ7  
DQ5  
S
NC  
DQ13 DQ6  
DQ12 CS2  
F
RESET  
Vss  
Vcc  
S
Vcc  
F
S
S
WP/  
ACC  
A19  
DQ11  
DQ10  
NC  
LB  
DQ2  
DQ0  
A1  
DQ3  
DQ1  
CS1  
UB  
A17  
A5  
OE  
S
DQ9 DQ8  
A7  
A4  
A6  
A0  
A3  
A2  
A18  
NC  
G
H
S
NC  
NC  
CE  
Vss  
NC  
NC  
OE  
F
NC  
F
F
Top View (Ball Down)  
Description  
Ball Name  
A0 to A17  
A18 to A20  
Description  
Ball Name  
CEF  
Address Input Balls (Common)  
Chip Enable (Flash Memory)  
Write Enable (SRAM)  
Address Input Balls (Flash Memory)  
WES  
WEF  
DQ0 to DQ15 Data Input/Output Balls (Common)  
Write Enable (Flash Memory)  
Output Enable (SRAM)  
Output Enable (Flash Memory)  
Power Supply (SRAM)  
RESET  
WP/ACC  
UB  
Hardware Reset (Flash Memory)  
OES  
Write Protection/Acceleration Program (Flash Memory)  
Upper Byte Enable (SRAM)  
OEF  
VccS  
VccF  
LB  
Lower Byte Enable (SRAM)  
Power Supply (Flash Memory)  
Ground (SRAM)  
CS1S  
CS2S  
Chip Enable (SRAM Low Active)  
Chip Enable (SRAM High Active)  
VssS  
VssF  
Ground (Flash Memory)  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
Revision 1.0  
November 2001  
- 2 -  
K5A3x41YT(B)A  
MCP MEMORY  
ORDERING INFORMATION  
K 5 A 3 x 4 1 Y T A - K 8 70  
Samsung  
MCP Memory  
SRAM Access Time  
70 ns  
Device Type  
Flash Access Time  
8 = 80 ns  
3 = 85 ns  
Dual Bank Boot Block NOR  
+ fCMOS SRAM  
9 = 90 ns  
NOR Flash Density  
Package  
(Bank Size), (Organization)  
3A : 32Mbit, (8Mb, 24Mb), (x16)  
3B : 32Mbit, (16Mb, 16Mb), (x16)  
66 TBGA  
Version  
2nd Generation  
SRAM Density, (Organization)  
4Mbit, (x16)  
Block Architecture  
T = Top Boot Block  
B = Bottom Boot Block  
Operating Voltage Range  
2.7V to 3.3V  
Figure 1. FUNCTIONAL BLOCK DIAGRAM  
VccF  
Bank1  
Address  
Bank1  
Cell Array  
VssF  
X
Dec  
RESET  
Latch &  
Control  
Y Dec  
Bank1 Data-In/Out  
A0 to A17  
(Common)  
Bank2 Data-In/Out  
Y Dec  
I/O  
A18 to A20  
CEF  
Interface  
Latch &  
Control  
&
Bank  
Control  
X
Dec  
Bank2  
Cell Array  
Bank2  
Address  
OEF  
WEF  
Erase  
Control  
High  
Voltage  
Gen.  
WP/ACC  
Program  
Control  
DQ0  
to  
Clk gen.  
Precharge circuit.  
DQ15  
OES  
WES  
UB  
LB  
SRAM  
Main Cell Array  
(256K x16)  
Row  
select  
CS1S  
CS2S  
VccS  
VssS  
Data  
control  
I/O Circuit  
Control  
logic  
Column select  
Revision 1.0  
November 2001  
- 3 -  
K5A3x41YT(B)A  
MCP MEMORY  
Table 1. Flash Memory Top Boot Block Address (K5A3A41YT/K5A3B41YT)  
K5  
A3A41  
YT  
K5  
A3B41  
YT  
Block Address  
Block Size  
(KW)  
Block  
Address Range  
A20  
A19  
A18  
A17 A15  
A16  
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
A14  
1
A13  
1
A12  
1
BA70  
BA69  
BA68  
BA67  
BA66  
BA65  
BA64  
BA63  
BA62  
BA61  
BA60  
BA59  
BA58  
BA57  
BA56  
BA55  
BA54  
BA53  
BA52  
BA51  
BA50  
BA49  
BA48  
BA47  
BA46  
BA45  
BA44  
BA43  
BA42  
BA41  
BA40  
BA39  
BA38  
BA37  
BA36  
BA35  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4
1FF000H-1FFFFFH  
1FE000H-1FEFFFH  
1FD000H-1FDFFFH  
1FC000H-1FCFFFH  
1FB000H-1FBFFFH  
1FA000H-1FAFFFH  
1F9000H-1F9FFFH  
1F8000H-1F8FFFH  
1F0000H-1F7FFFH  
1E8000H-1EFFFFH  
1E0000H-1E7FFFH  
1D8000H-1DFFFFH  
1D0000H-1D7FFFH  
1C8000H-1CFFFFH  
1C0000H-1C7FFFH  
1B8000H-1BFFFFH  
1B0000H-1B7FFFH  
1A8000H-1AFFFFH  
1A0000H-1A7FFFH  
198000H-19FFFFH  
190000H-197FFFH  
188000H-18FFFFH  
180000H-187FFFH  
178000H-17FFFFH  
170000H-177FFFH  
168000H-16FFFFH  
160000H-167FFFH  
158000H-15FFFFH  
150000H-157FFFH  
148000H-14FFFFH  
140000H-147FFFH  
138000H-13FFFFH  
130000H-137FFFH  
128000H-12FFFFH  
120000H-127FFFH  
118000H-11FFFFH  
1
1
0
4
1
0
1
4
1
0
0
4
0
1
1
4
0
1
0
4
0
0
1
4
0
0
0
4
Bank1  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
Bank1  
Bank2  
Revision 1.0  
November 2001  
- 4 -  
K5A3x41YT(B)A  
MCP MEMORY  
Table 1. Flash Memory Top Boot Block Address (K5A3A41YT/K5A3B41YT)  
K5  
A3A41  
YT  
K5  
A3B41  
YT  
Block Address  
Block Size  
(KW)  
Block  
Address Range  
A20  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
BA34  
BA33  
BA32  
BA31  
BA30  
BA29  
BA28  
BA27  
BA26  
BA25  
BA24  
BA23  
BA22  
BA21  
BA20  
BA19  
BA18  
BA17  
BA16  
BA15  
BA14  
BA13  
BA12  
BA11  
BA10  
BA9  
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
110000H-117FFFH  
108000H-10FFFFH  
100000H-107FFFH  
0F8000H-0FFFFFH  
0F0000H-0F7FFFH  
0E8000H-0EFFFFH  
0E0000H-0E7FFFH  
0D8000H-0DFFFFH  
0D0000H-0D7FFFH  
0C8000H-0CFFFFH  
0C0000H-0C7FFFH  
0B8000H-0BFFFFH  
0B0000H-0B7FFFH  
0A8000H-0AFFFFH  
0A0000H-0A7FFFH  
098000H-09FFFFH  
090000H-097FFFH  
088000H-08FFFFH  
080000H-087FFFH  
078000H-07FFFFH  
070000H-077FFFH  
068000H-06FFFFH  
060000H-067FFFH  
058000H-05FFFFH  
050000H-057FFFH  
048000H-04FFFFH  
040000H-047FFFH  
038000H-03FFFFH  
030000H-037FFFH  
028000H-02FFFFH  
020000H-027FFFH  
018000H-01FFFFH  
010000H-017FFFH  
008000H-00FFFFH  
000000H-007FFFH  
Bank1  
Bank2  
Bank2  
BA8  
BA7  
BA6  
BA5  
BA4  
BA3  
BA2  
BA1  
BA0  
Note : The bank address bits is A20 ~ A19 for K5A3A41YT, A20 for K5A3B41YT.  
Table 2. Secode Block Addresses for Top Boot Devices  
Device  
Block Address (A20-A12)  
111111xxx  
Block Size  
32  
Address Range  
K5A3A41YT/K5A3B41YT  
1F8000H-1FFFFFH  
Revision 1.0  
November 2001  
- 5 -  
K5A3x41YT(B)A  
MCP MEMORY  
Table 3. Flash Memory Bottom Boot Block Address (K5A3A41YB/K5A3B41YB)  
K5  
A3A41  
YB  
K5  
A3B41  
YB  
Block Address  
Block Size  
(KW)  
Block  
Address Range  
A20  
A19  
A18  
A17 A15  
A16  
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A14  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BA70  
BA69  
BA68  
BA67  
BA66  
BA65  
BA64  
BA63  
BA62  
BA61  
BA60  
BA59  
BA58  
BA57  
BA56  
BA55  
BA54  
BA53  
BA52  
BA51  
BA50  
BA49  
BA48  
BA47  
BA46  
BA45  
BA44  
BA43  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
1F8000H-1FFFFFH  
1F0000H-1F7FFFH  
1E8000H-1EFFFFH  
1E0000H-1E7FFFH  
1D8000H-1DFFFFH  
1D0000H-1D7FFFH  
1C8000H-1CFFFFH  
1C0000H-1C7FFFH  
1B8000H-1BFFFFH  
1B0000H-1B7FFFH  
1A8000H-1AFFFFH  
1A0000H-1A7FFFH  
198000H-19FFFFH  
190000H-197FFFH  
188000H-18FFFFH  
180000H-187FFFH  
178000H-17FFFFH  
170000H-177FFFH  
168000H-16FFFFH  
160000H-167FFFH  
158000H-15FFFFH  
150000H-157FFFH  
148000H-14FFFFH  
140000H-147FFFH  
138000H-13FFFFH  
130000H-137FFFH  
128000H-12FFFFH  
120000H-127FFFH  
Bank2  
Bank2  
BA42  
BA41  
BA40  
BA39  
BA38  
BA37  
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
118000H-11FFFFH  
110000H-117FFFH  
108000H-10FFFFH  
100000H-107FFFH  
0F8000H-0FFFFFH  
0F0000H-0F7FFFH  
32  
32  
32  
32  
32  
32  
32  
BA36  
BA35  
0
0
1
1
1
1
1
1
0
0
1
0
X
X
X
X
X
X
0E8000H-0EFFFFH  
0E0000H-0E7FFFH  
Revision 1.0  
November 2001  
- 6 -  
K5A3x41YT(B)A  
MCP MEMORY  
Table 3. Flash Memory Bottom Boot Block Address (K5A3A41YB/K5A3B41YB)  
K5  
A3A41  
YB  
K5  
A3B41  
YB  
Block Address  
Block Size  
(KW)  
Block  
Address Range  
A20  
A19  
A18  
A17 A15  
A16  
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
A14  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
A13  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
A12  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
BA34  
BA33  
BA32  
BA31  
BA30  
BA29  
BA28  
BA27  
BA26  
BA25  
BA24  
BA23  
BA22  
BA21  
BA20  
BA19  
BA18  
BA17  
BA16  
BA15  
BA14  
BA13  
BA12  
BA11  
BA10  
BA9  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
4
0D8000H-0DFFFFH  
0D0000H-0D7FFFH  
0C8000H-0CFFFFH  
0C0000H-0C7FFFH  
0B8000H-0BFFFFH  
0B0000H-0B7FFFH  
0A8000H-0AFFFFH  
0A0000H-0A7FFFH  
098000H-09FFFFH  
090000H-097FFFH  
088000H-08FFFFH  
080000H-087FFFH  
078000H-07FFFFH  
070000H-077FFFH  
068000H-06FFFFH  
060000H-067FFFH  
058000H-05FFFFH  
050000H-057FFFH  
048000H-04FFFFH  
040000H-047FFFH  
038000H-03FFFFH  
030000H-037FFFH  
028000H-02FFFFH  
020000H-027FFFH  
018000H-01FFFFH  
010000H-017FFFH  
008000H-00FFFFH  
007000H-007FFFH  
006000H-006FFFH  
005000H-005FFFH  
004000H-004FFFH  
003000H-003FFFH  
002000H-002FFFH  
001000H-001FFFH  
000000H-000FFFH  
Bank2  
Bank1  
Bank1  
BA8  
BA7  
BA6  
1
1
0
4
BA5  
1
0
1
4
BA4  
1
0
0
4
BA3  
0
1
1
4
BA2  
0
1
0
4
BA1  
0
0
1
4
BA0  
0
0
0
4
Note : The bank address bits is A20 ~ A19 for K5A3A41YB, A20 for K5A3B41YB.  
Table 4. Secode Block Addresses for Bottom Boot Devices  
Device  
Block Address (A20-A12)  
000000xxx  
Block Size  
32  
Address Range  
K5A3A41YB/K5A3B41YB  
000000H-007FFFH  
Revision 1.0  
November 2001  
- 7 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash MEMORY COMMAND DEFINITIONS  
Flash memory operates by selecting and executing its operational modes. Each operational mode has its own command set. In order  
to select a certain mode, a proper command with specific address and data sequences must be written into the command register.  
Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode.  
The defined valid register command sequences are stated in Table 5. Note that Erase Suspend (B0H) and Erase Resume (30H)  
commands are valid only while the Block Erase Operation is in progress.  
Table 5. Command Sequences  
Command Sequence  
Cycle  
1st Cycle  
RA  
2nd Cycle  
3rd Cycle  
4th Cycle  
5th Cycle  
6th Cycle  
Addr  
Read  
Data  
1
RD  
Addr  
XXXH  
F0H  
Reset  
Data  
1
4
Autoselect  
Manufacturer  
ID (2,3)  
Addr  
Data  
Addr  
Data  
Addr  
555H  
2AAH  
55H  
DA / 555H  
90H  
DA / X00H  
ECH  
AAH  
555H  
AAH  
555H  
Autoselect  
Device Code  
(2,3)  
2AAH  
55H  
DA / 555H  
90H  
DA / X01H  
(See Table 6)  
BA / X02H  
4
4
Autoselect  
Block Group  
Protect Verify  
(2,3)  
2AAH  
DA / 555H  
Data  
Addr  
Data  
AAH  
555H  
AAH  
55H  
2AAH  
55H  
90H  
DA / 555H  
90H  
(See Table 6)  
DA / X03H  
Auto Select  
Secode Block  
Factory Protect  
Verify (2,3)  
4
(See Table 6)  
Addr  
Data  
Addr  
555H  
AAH  
2AAH  
55H  
555H  
88H  
Enter Secode  
BlockRegion  
3
4
555H  
2AAH  
555H  
XXXH  
00H  
Exit Secode  
Block  
Region  
Data  
AAH  
55H  
90H  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
555H  
AAH  
555H  
AAH  
XXXH  
A0H  
2AAH  
55H  
555H  
A0H  
555H  
20H  
PA  
PD  
Program  
4
3
2
2
6
6
1
1
1
2AAH  
55H  
Unlock Bypass  
PA  
Unlock Bypass  
Program  
PD  
XXXH  
90H  
XXXH  
00H  
Unlock Bypass  
Reset  
555H  
AAH  
555H  
AAH  
XXXH  
B0H  
2AAH  
55H  
555H  
80H  
555H  
AAH  
555H  
AAH  
2AAH  
55H  
555H  
10H  
BA  
Chip Erase  
Block Erase  
2AAH  
55H  
555H  
80H  
2AAH  
55H  
30H  
Block Erase  
Suspend (4, 5)  
XXXH  
30H  
Block Erase  
Resume  
55H  
CFI Query (6)  
98H  
Revision 1.0  
November 2001  
- 8 -  
K5A3x41YT(B)A  
MCP MEMORY  
Notes : 1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data  
DA : Dual Bank Address (A19 - A20), BA : Block Address (A12 - A20), X = Don’t care .  
2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register.  
3. The 4th cycle data of Autoselect mode is output data.  
The 3rd and 4th cycle bank addresses of Autoselect mode must be same.  
4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode.  
5. The Erase Suspend command is applicable only to the Block Erase operation.  
6. Command is valid when the device is in read mode or Autoselect mode.  
7. DQ8 - DQ15 are don’t care in command sequence, except for RD and PD.  
8. A11 - A20 are also don’t care, except for the case of special notice.  
Table 6. Flash Memory Autoselect Codes  
Description  
DQ15 to DQ8  
DQ7 to DQ0  
Manufacturer ID  
X
ECH  
B8H  
Device Code K5A3A41YT (Top Boot Block)  
Device Code K5A3A41YB (Bottom Boot Block)  
Device Code K5A3B41YT (Top Boot Block)  
Device Code K5A3B41YB (Bottom Boot Block)  
Block Protection Verification  
22H  
22H  
22H  
22H  
30H  
BBH  
3EH  
01H (Protected),  
00H (Unprotected)  
X
X
80H (Factory locked),  
00H (Not factory locked)  
Secode Block Indicator Bit (DQ7)  
Table 7. Flash Memory Operation Table  
WP/  
ACC  
DQ8/  
DQ15  
DQ0/  
DQ7  
CEF  
OEF  
L
WEF  
H
Operation  
A9  
A9  
X
A6  
A6  
X
A1  
A1  
X
A0  
A0  
X
RESET  
H
Read  
L
L/H  
DOUT  
VccF  
±
Stand-by  
X
X
(2)  
High-Z  
(2)  
0.3V  
Output Disable  
Reset  
L
X
L
H
X
H
H
X
L
L/H  
L/H  
(4)  
X
X
X
X
X
X
X
X
High-Z  
High-Z  
DIN  
H
L
Write  
A9  
A6  
A1  
A0  
H
Enable Block Group  
Protect (3)  
L
L
H
H
X
L
L
X
L/H  
(4)  
(4)  
X
X
X
L
H
X
H
H
X
L
L
X
X
X
DIN  
DIN  
VID  
VID  
Enable Block Group  
Unprotect (3)  
Temporary Block Group  
Unprotect  
X
X
VID  
Notes :  
1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care.  
2. WP/ACC and RESET ball are asserted at VccF±0.3 V or Vss±0.3 V in the Stand-by mode.  
3. Addresses must be composed of the Block address (A12 - A20).  
The Block Protect and Unprotect operations may be implemented via programming equipment too.  
Refer to the "Block Group Protection and Unprotection".  
4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those  
blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks  
will be temporarily unprotected.  
Revision 1.0  
November 2001  
- 9 -  
K5A3x41YT(B)A  
MCP MEMORY  
Table 8. SRAM Operation Table  
CS1S  
CS2S  
X1)  
L
OES  
X1)  
X1)  
X1)  
H
WES  
X1)  
X1)  
X1)  
H
LB  
X1)  
X1)  
H
UB  
X1)  
X1)  
H
D/Q0~7  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Dout  
D/Q8~15  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Dout  
Mode  
Power  
H
X1)  
X1)  
L
Deselected2)  
Deselected2)  
Standby  
Standby  
Standby  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
X1)  
H
Deselected2)  
L
X1)  
L
Output Disabled2)  
Output Disabled2)  
Lower Byte Read3)  
Upper Byte Read3)  
Word Read3)  
L
H
H
H
X1)  
L
L
H
L
H
H
L
H
L
H
H
L
High-Z  
Dout  
L
H
L
H
L
L
Dout  
L
H
X1)  
X1)  
X1)  
L
L
H
Din  
High-Z  
Din  
Lower Byte Write3)  
Upper Byte Write3)  
Word Write3)  
L
H
L
H
L
High-Z  
Din  
L
H
L
L
L
Din  
Note:  
1. X = VIL or VIH  
2. Any NOR Flash mode is allowable.  
3. NOR Flash must be in High-Z  
Revision 1.0  
November 2001  
- 10 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash DEVICE OPERATION  
Read Mode  
Flash memory is controlled by Chip Enable (CEF), Output Enable (OEF) and Write Enable (WEF). When CEF and OEF are low and  
WEF is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance  
state whenever CEF or OEF is high.  
Standby Mode  
Flash memory features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is either  
unselected or deselected by making CEF high (CEF = VIH). Refer to the DC characteristics for more details on stand-by modes.  
Output Disable  
The device outputs are disabled when OEF is High (OEF = VIH). The output balls are in high impedance state.  
Automatic Sleep Mode  
Flash memory features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws 200nA  
of current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When  
addresses remain steady for tAA+50ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data  
is latched and always available to the system. When addresses are changed, the device provides new data without wait time.  
tAA + 50ns  
Address  
Outputs  
Data  
Data  
Data  
Data  
Data  
Data  
Auto Sleep Mode  
Figure 2. Auto Sleep Mode Operation  
Autoselect Mode  
Flash memory offers the Autoselect Mode to identify manufacturer and device type by reading a binary code. The Autoselect Mode  
allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm.  
In addition, this mode allows the verification of the status of write protected blocks. The manufacturer and device code can be read  
via the command register. The Command Sequence is shown in Table 5 and Figure 3. The autoselect operation of block protect ver-  
ification is initiated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command (90H). If  
Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address ball, it will produce a logical "1" at the device output DQ0  
to indicate a write protected block or a logical "0" at the device output DQ0 to indicate a write unprotected block. To terminate the  
autoselect operation, write Reset command (F0H) into the command register.  
Revision 1.0  
November 2001  
- 11 -  
K5A3x41YT(B)A  
MCP MEMORY  
WEF  
555H  
2AAH  
555H  
00H  
01H  
A20~A0*  
22B8H  
or  
ECH  
90H  
DQ15~DQ0  
55H  
AAH  
F0H  
2230H  
Manufacturer  
Code  
Device Code  
(K5A3A41Y)  
Return to  
Read Mode  
Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 6 for device code.  
Figure 3. Autoselect Operation  
Write (Program/Erase) Mode  
Flash memory executes its program/erase operations by writing commands into the command register. In order to write the com-  
mands to the register, CEF and WEF must be low and OEF must be high. Addresses are latched on the falling edge of CEF or WEF  
(whichever occurs last) and the data are latched on the rising edge of CEF or WEF (whichever occurs first). The device uses stan-  
dard microprocessor write timing.  
Program  
Flash memory can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal  
Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two  
cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory  
location and the data to be programmed at that location are written. The device automatically generates adequate program pulses  
and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not  
required to provide further controls or timings.  
During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program  
operation will cause data corruption at the corresponding location.  
WEF  
Program  
Address  
555H  
2AAH  
555H  
A20~A0  
Program  
Data  
A0H  
55H  
AAH  
DQ15-DQ0  
Figure 4. Program Command Sequence  
Revision 1.0  
November 2001  
- 12 -  
K5A3x41YT(B)A  
MCP MEMORY  
Unlock Bypass  
Flash memory provides the unlock bypass mode to save its program time. The mode is invoked by the unlock bypass command  
sequence. Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command  
sequence comprises only two bus cycles.  
The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writ-  
ing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock  
bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program  
command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the pro-  
gram address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode.  
The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock  
bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains  
only the data (00H). Then, the device returns to the read mode  
Chip Erase  
To erase a chip is to write 1¢s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus  
cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two  
more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the  
entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WEF or CEF  
pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.  
WEF  
555H  
2AAH  
555H  
555H  
2AAH  
555H  
A20~A0  
80H  
55H  
AAH  
AAH  
10H  
55H  
DQ15-DQ0  
Figure 5. Chip Erase Command Sequence  
Block Erase  
To erase a block is to write 1¢s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six  
bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is  
written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine  
automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of  
WEF or CEF, while the Block Erase command is latched on the rising edge of WEF or CEF.  
Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Fig 6. Upon completion of the last cycle for the  
Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50us  
(typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the  
50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of  
the WEF occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any com-  
mand other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the  
50 us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block  
Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recog-  
nized except the Erase Suspend command.  
Revision 1.0  
November 2001  
- 13 -  
K5A3x41YT(B)A  
MCP MEMORY  
WEF  
Block  
Address  
555H  
A20~A0  
2AAH  
555H  
555H  
2AAH  
DQ15-DQ0  
80H  
55H  
AAH  
AAH  
30H  
55H  
Figure 6. Block Erase Command Sequence  
Erase Suspend / Resume  
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Sus-  
pend command is only valid during the Block Erase operation including the time window of 50 us. The Erase Suspend command is  
not valid while the Chip Erase or the Internal Program Routine sequence is running.  
When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20 us to suspend  
the erase operation. But, when the Erase Suspend command is written during the block erase time window (50 us) , the device  
immediately terminates the block erase time window and suspends the erase operation.  
After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being  
erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode.  
When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume  
command is executed, the addresses are in Don't Care state.  
WEF  
Block  
Address  
555H  
XXXH  
A20~A0  
XXXH  
30H  
AAH  
B0H  
30H  
DQ15-DQ0  
Block Erase  
Command Sequence  
Erase  
Resume  
Block Erase  
Start  
Erase  
Suspend  
Figure 7. Erase Suspend/Resume Command Sequence  
Revision 1.0  
November 2001  
- 14 -  
K5A3x41YT(B)A  
MCP MEMORY  
Read While Write  
Flash memory provides dual bank memory architecture that divides the memory array into two banks. The device is capable of read-  
ing data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with dual  
bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-Suspend-Pro-  
gram operation.  
The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either  
single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write operation is prohibited  
when blocks from Bank1 and another blocks from Bank2 are loaded all together for the multi-block erase operation.  
Block Group Protection & Unprotection  
Flash memory feature hardware block group protection. This feature will disable both program and erase operations in any combina-  
tion of twenty five block groups of memory. Please refer to Tables 10 and 11. The block group protection feature is enabled using  
programming equipment at the user’s site. The device is shipped with all block groups unprotected.  
This feature can be hardware protected or unprotected. If a block is protected, program or erase command in the protected block will  
be ignored by the device. The protected block can only be read. This is useful method to preserve an important program data. The  
block group unprotection allows the protected blocks to be erased or programed. All blocks must be protected before unprotect oper-  
ation is executing. The block protection and unprotection can be implemented by the following method.  
Table 9. Block Group Protection & Unprotection  
DQ8/  
DQ115  
DQ0/  
DQ7  
CEF  
OEF  
WEF  
Operation  
A9  
A6  
A1  
A0  
RESET  
Block Group Protect  
L
L
H
H
L
L
X
X
L
H
H
L
L
X
X
DIN  
DIN  
VID  
VID  
Block Group Unprotect  
H
Address must be inputted to the block group address (A12~A20) during block group protection operation. Please refer to Figure 9  
(Algorithm) and Switching Waveforms of Block Group Protect & Unprotect Operation.  
Temporary Block Group Unprotect  
The protected blocks of the Flash memory can be temporarily unprotected by applying high voltage (VID = 8.5V~12.5V) to the RESET  
ball. In this mode, previously protected blocks can be programmed or erased with the program or erase command routines. When  
the RESET ball goes high (RESET = VIH), all the previously protected blocks will be protected again. If the WP/ACC ball is asserted  
at VIL , the two outermost boot blocks remain protected.  
VID  
V = VIH or VIL  
RESET  
CEF  
Program & Erase operation  
at Protected Block  
WEF  
Figure 8. Temporary Block Group Unprotect Sequence  
Revision 1.0  
November 2001  
- 15 -  
K5A3x41YT(B)A  
MCP MEMORY  
START  
COUNT = 1  
RESET=VID  
Wait 1ms  
No  
First Write  
Temporary Block Group  
Cycle=60h?  
Unprotect Mode  
Yes  
Yes  
No  
Block Group  
Protection ?  
No  
Block Unprotect  
Algorithm  
Block Protect  
Algorithm  
Yes  
All Block Groups  
Protected ?  
Set up Block Group  
Block Group <i>, i= 0  
address  
Block Group Unprotect  
Write 60H  
with  
Block Group Protect:  
Write 60H to Block  
Group address with  
A6=0,A1=1  
A6=1,A1=1  
A0=0  
A0=0  
Wait 15ms  
Wait 150ms  
Reset  
Verify Block Group  
Unprotect:Write 40H to  
Block Group address  
with A6=1,  
COUNT=1  
Verify Block Group  
Protect:Write 40H to  
Block Group address  
with A6=0,  
Increment  
COUNT  
A1=1,A0=0  
Increment  
COUNT  
A1=1,A0=0  
Read from  
Block Group address  
with A6=1,  
Read from  
Block Group address  
with A6=0,  
A1=1,A0=0  
Set up next Block  
Group address  
A1=1,A0=0  
No  
No  
No  
COUNT  
=1000?  
Data=00h?  
Yes  
No  
COUNT  
=25?  
Data=01h?  
Yes  
Yes  
Yes  
No  
Last Block Group  
verified ?  
Device failed  
Protect another  
Block Group?  
Device failed  
Yes  
Yes  
Remove VID  
from RESET  
No  
Remove VID  
from RESET  
Write RESET  
command  
Write RESET  
command  
END  
END  
Note : All blocks must be protected before unprotect operation is executing.  
Figure 9. Block Group Protection & Unprotection Algorithms  
Revision 1.0  
November 2001  
- 16 -  
K5A3x41YT(B)A  
MCP MEMORY  
Table 10. Flash Memory Block Group Address (Top Boot Block)  
Block Address  
Block Group  
Block  
A20  
A19  
A18  
A17  
A16  
A15  
0
A14  
A13  
A12  
BGA0  
BGA1  
0
0
0
0
0
X
X
X
BA0  
0
1
0
0
0
0
1
0
X
X
X
BA1 to BA3  
1
1
BGA2  
BGA3  
BGA4  
BGA5  
BGA6  
BGA7  
BGA8  
BGA9  
BGA10  
BGA11  
BGA12  
BGA13  
BGA14  
BGA15  
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BA4 to BA7  
BA8 to BA11  
BA12 to BA15  
BA16 to BA19  
BA20 to BA23  
BA24 to BA27  
BA28 to BA31  
BA32 to BA35  
BA36 to BA39  
BA40 to BA43  
BA44 to BA47  
BA48 to BA51  
BA52 to BA55  
BA56 to BA59  
BGA16  
1
1
1
1
0
1
X
X
X
BA60 to BA62  
1
0
BGA17  
BGA18  
BGA19  
BGA20  
BGA21  
BGA22  
BGA23  
BGA24  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
BA63  
BA64  
BA65  
BA66  
BA67  
BA68  
BA69  
BA70  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Revision 1.0  
November 2001  
- 17 -  
K5A3x41YT(B)A  
MCP MEMORY  
Table 11. Flash Memory Block Group Address (Bottom Boot Block)  
Block Address  
Block Group  
Block  
A20  
A19  
A18  
A17  
A16  
A15  
0
A14  
0
A13  
0
A12  
BGA0  
BGA1  
BGA2  
BGA3  
BGA4  
BGA5  
BGA6  
BGA7  
0
0
0
0
0
0
BA0  
BA1  
BA2  
BA3  
BA4  
BA5  
BA6  
BA7  
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
BGA8  
0
0
0
0
1
0
X
X
X
BA8 to BA10  
1
1
BGA9  
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BA11 to BA14  
BA15 to BA18  
BA19 to BA22  
BA23 to BA26  
BA27 to BA30  
BA31 to BA34  
BA35 to BA38  
BA39 to BA42  
BA43 to BA46  
BA47 to BA50  
BA51 to BA54  
BA55 to BA58  
BA59 to BA62  
BA63 to BA66  
BGA10  
BGA11  
BGA12  
BGA13  
BGA14  
BGA15  
BGA16  
BGA17  
BGA18  
BGA19  
BGA20  
BGA21  
BGA22  
BGA23  
BGA24  
1
1
1
1
1
1
1
1
0
1
X
X
X
X
X
X
BA67 to BA69  
BA70  
1
0
1
1
Revision 1.0  
November 2001  
- 18 -  
K5A3x41YT(B)A  
MCP MEMORY  
Write Protect (WP)  
The WP/ACC ball has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID.  
The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph).  
When the WP/ACC ball is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 4K word  
boot blocks independently of whether those blocks were protected or unprotected using the method described in "Block Group pro-  
tection/Unprotection".  
The write protected blocks can only be read. This is useful method to preserve an important program data.  
The two outermost 4K word boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or  
the two blocks containing the highest addresses in a top-boot-congfigured device.  
(K5A3A41YT/K5A3B41YT : BA69 and BA70, K5A3A41YB/K5A3B41YB : BA0 and BA1)  
When the WP/ACC ball is asserted at VIH, the device reverts to whether the two outermost 4K word boot blocks were last set to be  
protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected  
or unprotected using the method described in "Block Group protection/unprotection".  
Recommend that the WP/ACC ball must not be in the state of floating or unconnected, or the device may be led to malfunction.  
Secode(Security Code) Block Region  
The Secode Block feature provides a Flash memory region to be stored unique and permanent identification code, that is, Electronic  
Serial Number (ESN), customer code and so on. This is primarily intended for customers who wish to use an Electronic Serial Num-  
ber (ESN) in the device with the ESN protected against modification. Once the Secode Block region is protected, any further modifi-  
cation of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.  
The Secode Block is factory locked or customer lockable. Before the device is shipped, the factory locked Secode Block is written on  
the special code and it is protected. The Secode Indicator bit (DQ7) is permanently fixed at "1" and it is not changed. The customer  
lockable Secode Block is unprotected, therefore it is programmed and erased. The Secode Indicator bit (DQ7) of it is permanently  
fixed at "0" and it is not changed. But once it is protected, there is no procedure to unprotect and modify the Secode Block.  
The Secode Block region is 32K words in length and is accessed through a new command sequence (see Table 5). After the system  
has written the Enter Secode Block command sequence, the system may read the Secode Block region by using the same  
addresses of the boot blocks (4KWx8). The K5A3A41YT/K5A3B41YT occupies the address of the word mode 1F8000H to 1FFFFFH  
and the K5A3A41YB/K5A3B41YB type occupies the address of the word mode 000000H to 007FFFH. This mode of operation con-  
tinues until the system issues the Exit Secode Block command sequence, or until power is removed from the device. On power-up, or  
following a hardware reset, the device reverts to read mode.  
Accelerated Program Operation  
Accelerated program operation reduces the program time through the ACC function. This is one of two functions provided by the  
WP/ACC ball. When the WP/ACC ball is asserted as VHH, the device automatically enters the aforementioned Unlock Bypass mode,  
temporarily unprotecting any protected blocks, and reduces the program operation time. The system would use a two-cycle program  
command sequence as required by the Unlock Bypass mode. Removing VHH from the WP/ACC ball returns the device to normal  
operation. Recommend that the WP/ACC ball must not be asserted at VHH except accelerated program operation, or the  
device may be damaged. In addition, the WP/ACC ball must not be in the state of floating or unconnected, otherwise the  
device may be led to malfunction.  
Software Reset  
The reset command provides that the device is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care  
state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a pro-  
gram command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be  
erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the  
sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode.  
If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read  
mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode  
if the bank was in the Erase Suspend state.  
Revision 1.0  
November 2001  
- 19 -  
K5A3x41YT(B)A  
MCP MEMORY  
Hardware Reset  
Flash memory offers a reset feature by driving the RESET ball to VIL. The RESET ball must be kept low (VIL) for at least 500ns.  
When the RESET ball is driven low, any operation in progress will be terminated and the internal state machine will be reset to the  
standby mode after 20us. If a hardware reset occurs during a program operation, the data at that particular location will be lost.  
Once the RESET ball is taken high, the device requires 50ns of wake-up time until outputs are valid for read access. Also, note that  
all the data output balls are tri-stated for the duration of the RESET pulse.  
The RESET ball may be tied to the system reset ball. If a system reset occurs during the Internal Program and Erase Routine, the  
device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from  
the Flash memory.  
Power-up Protection  
To avoid initiation of a write cycle during VccF Power-up, RESET low must be asserted during power-up. After RESET goes high, the  
device is reset to the read mode.  
Low Vcc Write Inhibit  
F
To avoid initiation of a write cycle during VccF power-up and power-down, a write cycle is locked out for VccF less than 1.8V. If VccF  
< VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the  
device will reset itself to the read mode. Subsequent writes will be ignored until the VccF level is greater than VLKO. It is the user¢s  
responsibility to ensure that the control balls are logically correct to prevent unintentional writes when VccF is above 1.8V.  
Write Pulse Glitch Protection  
Noise pulses of less than 5ns(typical) on CEF, OEF, or WEF will not initiate a write cycle.  
Logical Inhibit  
Writing is inhibited under any one of the following conditions : OEF = VIL, CEF = VIH or WEF = VIH. To initiate a write, CEF and WEF  
must be "0", while OEF is "1".  
Commom Flash Memory Interface  
Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific informa-  
tion of the device, such as memory size, word configuration, and electrical features. Once this information has been obtained, the  
system software will know which command sets to use to enable flash writes, block erases, and control the flash component.  
When the system writes the CFI command(98H) to address 55H, the device enters the CFI mode. And then if the system writes the  
address shown in Table 12, the system can read the CFI data. Query data are always presented on the lowest-order data out-  
puts(DQ0-7) only. The upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command.  
Revision 1.0  
November 2001  
- 20 -  
K5A3x41YT(B)A  
MCP MEMORY  
Table 12. Common Flash Memory Interface Code  
Description  
Addresses  
Data  
10H  
11H  
12H  
0051H  
0052H  
0059H  
Query Unique ASCII string "QRY"  
13H  
14H  
0002H  
0000H  
Primary OEM Command Set  
15H  
16H  
0040H  
0000H  
Address for Primary Extended Table  
17H  
18H  
0000H  
0000H  
Alternate OEM Command Set (00h = none exists)  
Address for Alternate OEM Extended Table (00h = none exists)  
19H  
1AH  
0000H  
0000H  
VccF Min. (write/erase)  
1BH  
1CH  
0027H  
0036H  
D7-D4: volt, D3-D0: 100 millivolt  
VccF Max. (write/erase)  
D7-D4: volt, D3-D0: 100 millivolt  
Vpp Min. voltage(00H = no Vpp ball present)  
1DH  
1EH  
1FH  
20H  
21H  
22H  
23H  
24H  
25H  
26H  
27H  
0000H  
0000H  
0004H  
0000H  
000AH  
0000H  
0005H  
0000H  
0004H  
0000H  
0016H  
Vpp Max. voltage(00H = no Vpp ball present)  
Typical timeout per single word write 2N us  
Typical timeout for Min. size buffer write 2N us(00H = not supported)  
Typical timeout per individual block erase 2N ms  
Typical timeout for full chip erase 2N ms(00H = not supported)  
Max. timeout for word write 2N times typical  
Max. timeout for buffer write 2N times typical  
Max. timeout per individual block erase 2N times typical  
Max. timeout for full chip erase 2N times typical(00H = not supported)  
Device Size = 2N byte  
28H  
29H  
0002H  
0000H  
Flash Device Interface description  
2AH  
2BH  
0000H  
0000H  
Max. number of byte in multi-byte write = 2N  
Number of Erase Block Regions within device  
2CH  
0002H  
2DH  
2EH  
2FH  
30H  
0007H  
0000H  
0020H  
0000H  
Erase Block Region 1 Information  
Erase Block Region 2 Information  
Erase Block Region 3 Information  
Erase Block Region 4 Information  
31H  
32H  
33H  
34H  
003EH  
0000H  
0000H  
0001H  
35H  
36H  
37H  
38H  
0000H  
0000H  
0000H  
0000H  
39H  
3AH  
3BH  
3CH  
0000H  
0000H  
0000H  
0000H  
Revision 1.0  
November 2001  
- 21 -  
K5A3x41YT(B)A  
MCP MEMORY  
Table 12. Common Flash Memory Interface Code  
Description  
Addresses  
Data  
40H  
41H  
42H  
0050H  
0052H  
0049H  
Query-unique ASCII string "PRI"  
Major version number, ASCII  
Minor version number, ASCII  
43H  
44H  
0031H  
0031H  
Address Sensitive Unlock(Bits 1-0)  
0 = Required, 1= Not Required  
Silcon Revision Number(Bits 7-2)  
45H  
0000H  
Erase Suspend  
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write  
46H  
47H  
0002H  
0001H  
Block Protect  
0 = Not Supported, 1 = Number of blocks in per group  
Block Temporary Unprotect 00 = Not Supported, 01 = Supported  
Block Protect/Unprotect scheme 04 = K8D1x16U Mode  
48H  
49H  
0001H  
0004H  
Simultaneous Operation (1)  
00 = Not Supported, XX = Number of Blocks in Bank2  
4AH  
4BH  
4CH  
00XXH  
0000H  
0000H  
Burst Mode Type 00 = Not Supported, 01 = Supported  
Page Mode Type  
00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page  
ACC(Acceleration) Supply Minimum  
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV  
4DH  
4EH  
4FH  
0085H  
00C5H  
000XH  
ACC(Acceleration) Supply Maximum  
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV  
Top/Bottom Boot Block Flag  
02H = Bottom Boot Device, 03H = Top Boot Device  
Note :  
1. The number of blocks in Bank2 is device dependent.  
K5A3A41Y(8Mb/24Mb) = 30h (48blocks)  
K5A3B41Y(16Mb/16Mb) = 20h (32blocks)  
Revision 1.0  
November 2001  
- 22 -  
K5A3x41YT(B)A  
MCP MEMORY  
DEVICE STATUS FLAGS  
Flash memory has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address  
must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag via cor-  
responding DQ balls. The corresponding DQ balls are DQ7, DQ6, DQ5, DQ3 and DQ2. The statuses are as follows :  
Table 13. Hardware Sequence Flags  
Status  
DQ7  
DQ7  
0
DQ6  
Toggle  
Toggle  
DQ5  
DQ3  
DQ2  
1
Programming  
0
0
0
1
Block Erase or Chip Erase  
Erase Suspend Read  
Toggle  
Erase Suspended  
Block  
Toggle  
(Note 1)  
1
1
0
Data  
0
0
Data  
0
In Progress  
Non-Erase Suspended  
Block  
Erase Suspend Read  
Data  
DQ7  
Data  
Toggle  
Data  
1
Erase Suspend  
Program  
Non-Erase Suspended  
Block  
No  
Toggle  
Programming  
DQ7  
0
Toggle  
Toggle  
Toggle  
1
1
1
0
1
0
Exceeded  
Time Limits  
Block Erase or Chip Erase  
Erase Suspend Program  
(Note 2)  
No  
Toggle  
DQ7  
Notes :  
1. DQ2 will toggle when the device performs successive read operations from the erase suspended block.  
2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.  
DQ7 : Data Polling  
When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as  
an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data  
written to DQ7. When a user attempts to read the device during the Erase operation, DQ7 will be low. If the device is placed in the  
Erase Suspend Mode, the status can be detected via the DQ7 ball. If the system tries to read an address which belongs to a block  
that is being erased, DQ7 will be high. If a non-erased block address is read, the device will produce the true data to DQ7. If an  
attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1ms and the device then  
returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs comple-  
ment data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block.  
DQ6 : Toggle Bit  
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state,  
DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase Suspend Mode,  
an attempt to read an address that belongs to a block that is being erased will produce a high output of DQ6. If an address belongs  
to a block that is not being erased, toggling is halted and valid data is produced at DQ6.  
If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read  
Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100ms  
and the device then returns to the Read Mode without erasing the data in the block.  
DQ5 : Exceed Timing Limits  
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.  
Revision 1.0  
November 2001  
- 23 -  
K5A3x41YT(B)A  
MCP MEMORY  
DQ3 : Block Erase Timer  
The status of the multi-block erase operation can be detected via the DQ3 ball. DQ3 will go High if 50ms of the block erase time win-  
dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write  
commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase  
time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been  
accepted, the software may check the status of DQ3 following each block erase command.  
DQ2 : Toggle Bit 2  
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the device  
executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the  
Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase  
Suspend mode, DQ2 toggles only if an address in the erasing block is read. If a non-erasing block address is read during the Erase  
Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the  
device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation  
from the program operation.  
Revision 1.0  
November 2001  
- 24 -  
K5A3x41YT(B)A  
MCP MEMORY  
Start  
Start  
Yes  
No  
DQ7 = Data ?  
No  
DQ6 = Toggle ?  
Yes  
No  
No  
DQ5 = 1 ?  
DQ5 = 1 ?  
Yes  
Yes  
No  
Yes  
DQ6 = Toggle ?  
DQ7 = Data ?  
Yes  
Fail  
No  
Pass  
Pass  
Fail  
Figure 11. Toggle Bit Algorithms  
Figure 10. Data Polling Algorithms  
Start  
RESET=VID  
(Note 1)  
Perform Erase or  
Program Operations  
RESET=VIH  
Temporary Block  
Unprotect Completed  
(Note 2)  
Notes :  
1. All protected block groups are unprotected.  
( If WP/ACC = VIL , the two outermost boot blocks remain protected )  
2. All previously protected block groups are protected once again.  
Figure 12. Temporary Block Group Unprotect Routine  
Revision 1.0  
November 2001  
- 25 -  
K5A3x41YT(B)A  
MCP MEMORY  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
Rating  
Unit  
Vcc  
VccF , VccS  
-0.3 to +3.6  
-0.3 to +12.5  
-0.3 to +12.5  
RESET  
Voltage on any ball relative to Vss  
WP/ACC  
V
VIN  
All Other Balls  
-0.3 to Vcc+0.3V(Max.3.6V)  
-40 to +125  
Temperature Under Bias  
Storage Temperature  
Operating Temperature  
Tbias  
Tstg  
TA  
°C  
°C  
°C  
-65 to +150  
-40 to +85  
Notes :  
1. Minimum DC voltage is -0.3V on Input/ Output balls. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on  
input / output balls is Vcc+0.3V(Max. 3.6V) which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.  
2. Minimum DC voltage is -0.3V on RESET and WP/ACC balls. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC  
voltage on RESET and WP/ACC balls are 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns.  
3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions  
detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
RECOMMENDED OPERATING CONDITIONS ( Voltage reference to Vss )  
Parameter  
Supply Voltage  
Symbol  
VccF , VccS  
Vss  
Min  
2.7  
0
Typ.  
3.0  
0
Max  
3.3  
0
Unit  
V
Supply Voltage  
V
DC CHARACTERISTICS  
Parameter  
Symbol  
Test Conditions  
Min  
Typ  
Max  
Unit  
Input Leakage Current  
ILI  
VIN=Vss to Vcc, Vcc=Vccmax  
-1.0  
-
1.0  
1.0  
0.6  
mA  
VOUT=Vss to Vcc, Vcc=Vccmax,  
OEF=OES=VIH  
Output Leakage Current  
ILO  
VIL  
VIH  
-1.0  
-0.3  
2.2  
-
-
-
mA  
V
Input Low Level  
Input High Level  
Com-  
mon  
Vcc  
+0.3  
V
Output Low Level  
VOL  
VOH  
ILIT  
IOL= 2.1mA, Vcc = Vccmin  
IOH= -1.0mA, Vcc = Vccmin  
VccF=Vccmax, RESET=12.5V  
-
2.4  
-
-
-
-
0.4  
-
V
V
Output High Level  
RESET Input Leakage Current  
35  
mA  
VccF=Vccmax, WP/ACC=12.5V  
WP/ACC Input Leakage Current  
Active Read Current (1)  
ILIW  
-
-
-
-
-
35  
20  
6
mA  
5MHz  
14  
3
CEF=VIL, OEF=VIH  
ICC1  
mA  
1MHz  
Active Write Current (2)  
CEF=VIL, OEF=VIH  
CEF=VIL, OEF=VIH  
CEF=VIL, OEF=VIH  
mA  
mA  
mA  
ICC2  
ICC3  
ICC4  
15  
30  
Read While Program Current (3)  
Read While Erase Current (3)  
-
-
25  
25  
50  
50  
Program While Erase Suspend  
Current  
Flash  
CEF=VIL, OEF=VIH  
CEF=VIL, OEF=VIH  
ICC5  
IACC  
-
15  
35  
mA  
mA  
ACC Ball  
VccF Ball  
-
-
5
10  
30  
ACC Accelerated Program  
Current  
15  
VccF=VccFmax, CEF=VccF± 0.3V,  
RESET=VccF± 0.3V,  
Standby Current  
ISB1  
ISB2  
-
-
0.2  
0.2  
10  
10  
mA  
mA  
WP/ACC=VccF± 0.3V or Vss± 0.3V  
VccF=VccFmax, RESET=Vss±0.3V,  
WP/ACC=VccF± 0.3V or Vss± 0.3V  
Standby Curren During Reset  
Revision 1.0  
November 2001  
- 26 -  
K5A3x41YT(B)A  
MCP MEMORY  
DC CHARACTERISTICS (Continued)  
Parameter  
Symbol  
Test Conditions  
Min Typ Max Unit  
VIH=VccF±0.3V, VIL=VSS±0.3V, OE=VIL, IOL=IOH=0  
Automatic Sleep Mode  
ISB3  
-
0.2  
10  
mA  
Voltage for WP/ACC Block  
Temporarily Unprotect and  
Program Acceleration (4)  
VccF = 3.0V ± 0.3V  
VccF = 3.0V ± 0.3V  
VHH  
8.5  
-
12.5  
V
Flash  
Voltage for Autoselect and  
Block Protect (4)  
VID  
8.5  
1.8  
-
-
12.5  
-
V
V
Low VccF Lock-out Voltage (5)  
VLKO  
Cycle time=1ms, 100% duty, CS1S£0.2V,  
CS2S³ VccS-0.2V, LB£0.2V and/or UB£0.2V  
All outputs open, VIN£0.2V or VIN³ VccS-0.2V  
ICC1  
-
-
3
mA  
Operating Current  
Cycle time=Min, 100% duty, CS1S=VIL, CS2S=VIH,  
SRAM  
ICC2  
ISB  
-
-
17  
22  
10  
mA  
LB=VIL and/or UB= VIL, All outputs open,  
VIN=VIL or VIH  
CS1S³ VccS-0.2V, CS2S³ VccS-0.2V(CS1S controlled)  
or CS2S£0.2V (CS2S controlled), Other input =0~VccS  
Standby Current  
0.5  
mA  
Notes :  
1. The ICC current listed includes both the DC operating current and the frequency dependent component(at 5 MHz).  
The read current is typically 14 mA (@ VccF=3.0V , OEF at VIH.)  
2. ICC active during Internal Routine(program or erase) is in progress.  
3. ICC active during Read while Write is in progress.  
4. The high voltage ( VHH or VID ) must be used in the range of VccF = 3.0V ± 0.3V  
5. Not 100% tested.  
6. Typical values are measured at VccF = VccS = 3.0V, Ta=25°C , not 100% tested.  
CAPACITANCE(TA = 25 °C, Vcc = Vcc = 3.3V, f = 1.0MHz)  
F
S
Item  
Symbol  
CIN  
Test Condition  
VIN=0V  
Min  
Max  
18  
Unit  
Input Capacitance  
-
-
-
pF  
pF  
pF  
Output Capacitance  
Control Ball Capacitance  
COUT  
CIN2  
VOUT=0V  
VIN=0V  
20  
18  
Note : Capacitance is periodically sampled and not 100% tested.  
AC TEST CONDITION  
Parameter  
Input Pulse Levels  
Value  
0V to 3V  
5ns  
Input Rise and Fall Times  
Input and Output Timing Levels  
Output Load  
1.5V  
1TTL and CL = 50pF  
3.3V  
2.7KW  
Device  
3V  
Input & Output  
6.2KW  
1.5V  
1.5V  
Test Point  
Diodes IN3064  
or Equivalent  
CL  
0V  
* CL= 50pF including Scope  
and Jig Capacitance  
Input Pulse and Test Point  
Output Load  
Revision 1.0  
November 2001  
- 27 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash AC CHARACTERISTICS  
Write(Erase/Program)Operations  
Alternate WEF Controlled Write  
80ns  
85ns  
90ns  
Unit  
Parameter  
Write Cycle Time (1)  
Symbol  
Min  
80  
0
Max  
Min  
85  
0
Max  
Min  
90  
0
Max  
tWC  
tAS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Setup Time  
tASO  
tAH  
55  
45  
0
55  
45  
0
55  
45  
0
Address Hold Time  
tAHT  
tDS  
Data Setup Time  
35  
0
45  
0
45  
0
Data Hold Time  
tDH  
Output Enable Setup Time (1)  
tOES  
tOEH1  
0
0
0
Output  
Read (1)  
0
0
0
Enable  
Hold Time  
Toggle and Data Polling (1)  
tOEH2  
tCS  
10  
0
-
-
10  
0
-
-
10  
0
-
-
ns  
ns  
CEF Setup Time  
CEF Hold Time  
tCH  
tWP  
0
-
-
-
0
-
-
-
0
-
-
-
ns  
ns  
Write Pulse Width  
35  
25  
45  
30  
45  
30  
Write Pulse Width High  
Programming Operation  
Accelerated Programming Operation  
Block Erase Operation (2)  
VccF Set Up Time  
tWPH  
ns  
tPGM  
11(typ.)  
9(typ.)  
11(typ.)  
9(typ.)  
11(typ.)  
ms  
tACCPGM  
tBERS  
9(typ.)  
ms  
0.7(typ.)  
0.7(typ.)  
0.7(typ.)  
sec  
tVCS  
tRH  
50  
-
-
-
-
-
-
-
-
-
-
50  
-
-
-
-
-
-
-
-
-
-
50  
-
-
-
-
-
-
-
-
-
-
ms  
ns  
ms  
ns  
ns  
ms  
ns  
ns  
ns  
ns  
RESET High Time Before Read  
RESET to Power Down Time  
VID Rising and Falling Time  
50  
20  
50  
20  
50  
20  
tRPD  
tVID  
500  
500  
1
500  
500  
1
500  
500  
1
RESET Pulse Width  
tRP  
RESET Setup Time for Temporary Unprotect  
RESET Low Setup Time  
tRSP  
tRSTS  
tRSTW  
tGHWL  
tCEPH  
500  
200  
0
500  
200  
0
500  
200  
0
RESET High to Address Valid  
Read Recovery Time Before Write  
CEF High during toggling bit polling  
20  
20  
20  
OEF High during toggling bit polling  
tOEPH  
20  
-
20  
-
20  
-
ns  
Notes : 1. Not 100% tested.  
2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.  
Revision 1.0  
November 2001  
- 28 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash AC CHARACTERISTICS  
Write(Erase/Program)Operations  
Alternate CEF Controlled Writes  
80ns  
85ns  
90ns  
Unit  
Parameter  
Symbol  
Min  
80  
0
Max  
Min  
85  
0
Max  
Min  
90  
0
Max  
Write Cycle Time (1)  
Address Setup Time  
Address Hold Time  
Data Setup Time  
tWC  
tAS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAH  
45  
35  
0
45  
45  
0
45  
45  
0
tDS  
Data Hold Time  
tDH  
Output Enable Setup Time (1)  
tOES  
tOEH1  
0
0
0
Output  
Read (1)  
0
0
0
Enable  
Hold Time  
Toggle and Data Polling (1)  
tOEH2  
10  
-
10  
-
10  
-
ns  
WEF Setup Time  
WEF Hold Time  
tWS  
tWH  
tCP  
0
-
-
-
-
0
0
-
-
-
-
0
0
-
-
-
-
ns  
ns  
ns  
0
CEF Pulse Width  
CEF Pulse Width High  
35  
25  
45  
30  
45  
30  
tCPH  
ns  
ms  
ms  
Programming Operation  
tPGM  
11(typ.)  
9(typ.)  
11(typ.)  
9(typ.)  
11(typ.)  
9(typ.)  
Accelerated Programming Operation  
tACCPGM  
RESET Low to Valid Data  
(During Internal Routine)  
tREADY  
-
-
20  
500  
0.7(typ.)  
-
-
20  
500  
0.7(typ.)  
-
-
20  
ms  
RESET Low to Valid Data  
(Not during Internal Routine)  
tREADY  
tBERS  
500  
ns  
Block Erase Operation (2)  
0.7(typ.)  
sec  
Notes : 1. Not 100% tested.  
2.This does not include the preprogramming time.  
Flash ERASE AND PROGRAM PERFORMANCE  
Limits  
Parameter  
Unit  
Comments  
Min  
Typ  
Max  
Excludes 00H programming  
prior to erasure  
Block Erase Time  
-
0.7  
15  
sec  
Chip Erase Time  
-
-
-
-
49  
11  
9
-
sec  
ms  
Programming Time  
330  
210  
66  
Excludes system-level overhead  
Excludes system-level overhead  
Excludes system-level overhead  
Accelerated Program Time  
Chip Programming Time  
ms  
22  
sec  
Minimum 100,000 cycles guaran-  
teed  
Erase/Program Endurance  
100,000  
-
-
cycles  
Notes : 1. 25 °C, VccF = 3.0 V 100,000 cycles, typical pattern.  
2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each word.  
In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure.  
Revision 1.0  
November 2001  
- 29 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash SWITCHING WAVEFORMS  
Read Operations  
tRC  
Address Stable  
Address  
tAA  
CEF  
tOE  
tDF  
OEF  
tOEH1  
WEF  
tCE  
tOH  
HIGH-Z  
HIGH-Z  
Outputs  
Output Valid  
80ns  
Max  
85ns  
90ns  
Max  
Parameter  
Symbol  
Unit  
Min  
Min  
Max  
Min  
Read Cycle Time  
tRC  
tAA  
80  
-
-
85  
-
-
90  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Enable Access Time  
Output Enable Time  
80  
80  
25  
25  
-
85  
85  
35  
30  
-
90  
tCE  
-
-
-
90  
35  
30  
tOE  
-
-
-
CEF & OEF Disable Time (1)  
tDF  
-
-
-
Output Hold Time from Address, CEF or OEF  
OEF Hold Time  
tOH  
0
0
0
0
0
0
-
-
tOEH1  
-
-
Revision 1.0  
November 2001  
- 30 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash SWITCHING WAVEFORMS  
Hardware Reset/Read Operations  
tRC  
Address Stable  
Address  
tAA  
CEF  
tRH  
tRP  
tRH  
tCE  
RESET  
tOH  
High-Z  
Output Valid  
Outputs  
80ns  
85ns  
90ns  
Unit  
Parameter  
Symbol  
Min  
80  
-
Max  
Min  
Max  
Min  
90  
-
Max  
Read Cycle Time  
tRC  
tAA  
tCE  
tOH  
tRP  
tRH  
-
80  
80  
-
85  
-
-
85  
85  
-
-
90  
90  
-
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Enable Access Time  
-
-
-
Output Hold Time from Address, CEF or OEF  
0
0
0
RESET Pulse Width  
500  
50  
-
500  
50  
-
500  
50  
-
RESET High Time Before Read  
-
-
-
Revision 1.0  
November 2001  
- 31 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash SWITCHING WAVEFORMS  
Alternate WEF Controlled Program Operations  
tAS  
Data Polling  
555H  
PA  
PA  
Address  
CEF  
tRC  
tAH  
tOES  
OEF  
WEF  
tWC  
tCH  
tPGM  
tWP  
tWPH  
tDH  
tCS  
tOE  
tDF  
A0H  
PD  
Status  
DOUT  
DATA  
tCE  
tOH  
tDS  
Notes : 1. DQ7 is the output of the complement of the data written to the device.  
2. DOUT is the output of the data written to the device.  
3. PA : Program Address, PD : Program Data  
4. The illustration shows the last two cycles of the program command sequence.  
80ns  
85ns  
90ns  
Parameter  
Symbol  
Unit  
Min  
80  
0
Max  
Min  
85  
0
Max  
Min  
90  
0
Max  
Write Cycle Time  
tWC  
tAS  
tAH  
tDS  
tDH  
tCS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Data Hold Time  
45  
35  
0
45  
45  
0
45  
45  
0
CEF Setup Time  
0
0
0
CEF Hold Time  
OEF Setup Time  
tCH  
0
-
0
-
0
-
ns  
tOES  
tWP  
0
-
-
-
0
-
-
-
0
-
-
-
ns  
ns  
ns  
us  
ms  
ns  
ns  
ns  
ns  
Write Pulse Width  
35  
25  
45  
30  
45  
30  
Write Pulse Width High  
Programming Operation  
Accelerated Programming Operation  
Read Cycle Time  
tWPH  
tPGM  
tACCPGM  
tRC  
11(typ.)  
9(typ.)  
11(typ.)  
9(typ.)  
11(typ.)  
9(typ.)  
80  
-
85  
-
90  
-
Chip Enable Access Time  
Output Enable Time  
tCE  
-
-
-
80  
25  
25  
-
-
-
85  
35  
30  
-
-
-
90  
35  
30  
tOE  
CEF & OEF Disable Time  
tDF  
Output Hold Time from Address, CEF or OEF  
tOH  
0
-
0
-
0
-
ns  
Revision 1.0  
November 2001  
- 32 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash SWITCHING WAVEFORMS  
Alternate CEF Controlled Program Operations  
tAS  
Data Polling  
555H  
PA  
PA  
Address  
WEF  
tAH  
tOES  
OEF  
CEF  
tWC  
tPGM  
tCP  
tCPH  
tDH  
tWS  
PD  
DOUT  
Status  
A0H  
DATA  
tDS  
Notes :  
1. DQ7 is the output of the complement of the data written to the device.  
2. DOUT is the output of the data written to the device.  
3. PA : Program Address, PD : Program Data  
4. The illustration shows the last two cycles of the program command sequence.  
80ns  
85ns  
90ns  
Parameter  
Symbol  
Unit  
Min  
80  
0
Max  
Min  
85  
0
Max  
Min  
90  
0
Max  
Write Cycle Time  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Data Hold Time  
tWC  
tAS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
tAH  
45  
35  
0
45  
45  
0
45  
45  
0
tDS  
tDH  
tOES  
OEF Setup Time  
0
0
0
WEF Setup Time  
WEF Hold Time  
tWS  
tWH  
tCP  
0
0
-
-
-
-
0
-
-
-
-
0
0
-
-
-
-
ns  
ns  
ns  
0
CEF Pulse Width  
CEF Pulse Width High  
35  
25  
45  
30  
45  
30  
tCPH  
ns  
ms  
ms  
Programming Operation  
tPGM  
11(typ.)  
9(typ.)  
11(typ.)  
9(typ.)  
11(typ.)  
9(typ.)  
Accelerated Programming Operation  
tACCPGM  
Revision 1.0  
November 2001  
- 33 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash SWITCHING WAVEFORMS  
Chip/Block Erase Operations  
tAS  
555H for Chip Erase  
555H  
2AAH  
555H  
555H  
2AAH  
BA  
Address  
CEF  
tAH  
tRC  
tOES  
OEF  
WEF  
tWC  
tWP  
tWPH  
tDH  
tCS  
10H for Chip Erase  
30H  
AAH  
55H  
80H  
AAH  
55H  
DATA  
VccF  
tDS  
tVCS  
Note : BA : Block Address  
80ns  
85ns  
90ns  
Parameter  
Symbol  
Unit  
Max  
Min  
80  
0
Max  
Min  
Max  
Min  
90  
0
Write Cycle Time  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Data Hold Time  
tWC  
tAS  
-
-
-
-
-
-
85  
0
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
tAH  
45  
35  
0
45  
45  
0
45  
45  
0
tDS  
tDH  
tOES  
OEF Setup Time  
0
0
0
CEF Setup Time  
tCS  
tWP  
tWPH  
tRC  
0
-
-
-
-
0
-
-
-
-
0
-
-
-
-
ns  
ns  
ns  
ns  
Write Pulse Width  
Write Pulse Width High  
Read Cycle Time  
35  
25  
80  
45  
30  
85  
45  
30  
90  
VccF Set Up Time  
tVCS  
50  
-
50  
-
50  
-
ms  
Revision 1.0  
November 2001  
- 34 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash SWITCHING WAVEFORMS  
Read While Write Operations  
Read  
tRC  
Command  
tWC  
Read  
tRC  
Command  
tWC  
Read  
tRC  
Read  
tRC  
DA2  
(555H)  
DA2  
(PA)  
DA2  
(PA)  
Address  
DA1  
DA1  
DA1  
tAS  
tAS  
tAH  
tAA  
tCE  
tAHT  
CEF  
OEF  
tOE  
tCEPH  
tDF  
tOES  
tOEH2  
tWP  
WEF  
DQ  
t
DF  
tDH  
tDS  
Valid  
Output  
Valid  
Input  
Valid  
Output  
Valid  
Input  
Valid  
Output  
Status  
(A0H)  
(PD)  
Note : This is an example in the program-case of the Read While Write function.  
DA1 : Address of Bank1, DA2 : Address of Bank 2  
PA = Program Address at one bank , RA = Read Address at the other bank, PD = Program Data In , RD = Read Data Out  
80ns  
85ns  
90ns  
Parameter  
Symbol  
Unit  
Min  
80  
35  
25  
0
Max  
Min  
85  
45  
30  
0
Max  
Min  
90  
45  
30  
0
Max  
Write Cycle Time  
tWC  
tWP  
tWPH  
tAS  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Write Pulse Width  
Write Pulse Width High  
Address Setup Time  
Address Hold Time  
Data Setup Time  
-
-
-
-
-
-
tAH  
45  
35  
0
-
45  
45  
0
-
45  
45  
0
-
DS  
t
-
-
-
Data Hold Time  
tDH  
tRC  
tCE  
-
-
-
Read Cycle Time  
80  
-
-
85  
-
-
90  
-
-
Chip Enable Access Time  
Address Access Time  
Output Enable Access Time  
OEF Setup Time  
80  
80  
25  
-
85  
85  
35  
-
90  
90  
35  
-
tAA  
-
-
-
tOE  
tOES  
-
-
-
0
0
0
OEF Hold Time  
tOEH2  
tDF  
10  
-
-
25  
-
10  
-
-
30  
-
10  
-
-
30  
-
ns  
ns  
ns  
ns  
CEF & OEF Disable Time  
Address Hold Time  
tAHT  
tCEPH  
0
0
0
CEF High during toggle bit polling  
20  
-
20  
-
20  
-
Revision 1.0  
November 2001  
- 35 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash SWITCHING WAVEFORMS  
Data Polling During Internal Routine Operation  
CEF  
tDF  
tOE  
OEF  
tOEH2  
WEF  
tCE  
tOH  
HIGH-Z  
Data In  
Data In  
DQ7  
*DQ7 = Valid Data  
DQ7  
tPGM or tBERS  
HIGH-Z  
DQ0-DQ6  
Valid Data  
Status Data  
Note : *DQ7=Vaild Data (The device has completed the internal operation).  
80ns  
85ns  
90ns  
Parameter  
Symbol  
Unit  
Min  
Max  
80  
Min  
Max  
85  
Min  
Max  
90  
Chip Enable Access Time  
Output Enable Time  
tCE  
tOE  
tDF  
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
25  
35  
35  
CEF & OEF Disable Time  
25  
30  
30  
Output Hold Time from Address, CEF or OEF  
OEF Hold Time  
tOH  
0
-
-
0
-
-
0
-
-
ns  
ns  
tOEH2  
10  
10  
10  
Revision 1.0  
November 2001  
- 36 -  
K5A3x41YT(B)A  
MCP MEMORY  
SWITCHING WAVEFORMS  
Toggle Bit During an Internal Routine Operation  
tAHT  
tAS  
Address*  
tAHT  
tASO  
CEF  
tOEH2  
tCEPH  
WEF  
OEF  
tOEPH  
tDH  
E
tO  
Status  
Data  
Status  
Data  
Status  
Data  
Data In  
DQ6/DQ2  
Array Data Out  
Note : Address for the write operation must include a bank address where the data is written.  
Enter  
Embedded  
Erasing  
Erase  
Suspend  
Enter Erase  
Suspend Program  
Erase  
Resume  
Erase  
Erase Suspend  
Read  
Erase Suspend  
Read  
Erase  
Erase  
Complete  
WEF  
DQ6  
DQ2  
Erase  
Suspend  
Program  
Toggle  
DQ2 and DQ6  
with OEF or CEF  
Note : DQ2 is read from the erase-suspended block.  
80ns  
85ns  
90ns  
Parameter  
Symbol  
Unit  
Min  
-
Max  
Min  
-
Max  
Min  
Max  
Output Enable Access Time  
OEF Hold Time  
tOE  
tOEH2  
tAHT  
tASO  
tAS  
25  
-
35  
-
-
35  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10  
0
10  
0
10  
0
Address Hold Time  
Address Setup  
-
-
-
55  
0
-
55  
0
-
55  
0
-
Address Setup Time  
Data Hold Time  
-
-
-
tDH  
0
-
0
-
0
-
CEF High during toggle bit polling  
tCEPH  
20  
-
20  
-
20  
-
OEF High during toggle bit polling  
tOEPH  
20  
-
20  
-
20  
-
ns  
Revision 1.0  
November 2001  
- 37 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash SWITCHING WAVEFORMS  
RESET Timing Diagram  
CEF or OEF  
RESET  
tRH  
tRP  
Power-up and RESET Timing Diagram  
tRSTS  
RESET  
VccF  
Address  
DATA  
tAA  
80ns  
85ns  
90ns  
Unit  
Parameter  
RESET Pulse Width  
Symbol  
Min  
500  
50  
Max  
Min  
Max  
Min  
500  
50  
Max  
tRP  
tRH  
-
-
-
-
500  
50  
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
RESET High Time Before Read  
RESET High to Address Valid  
RESET Low Set-up Time  
tRSTW  
tRSTS  
200  
500  
200  
500  
200  
500  
Revision 1.0  
November 2001  
- 38 -  
K5A3x41YT(B)A  
MCP MEMORY  
Flash SWITCHING WAVEFORMS  
Block Group Protect & Unprotect Operations  
VID  
RESET  
Vss,VIL,  
or VIH  
Vss,VIL,  
or VIH  
BGA,A6  
A1,A0  
Valid  
Valid  
Valid  
Verify  
Block Group Protect / Unprotect  
DATA  
40H  
Status*  
60H  
60H  
Block Group Protect:150ms  
Block Group Unprotect:15ms  
1ms  
CEF  
WEF  
tRB  
OEF  
Notes : Block Group Protect (A6=VIL , A1=VIH , A0=VIL) , Status=01H  
Block Group Unprotect (A6=VIH , A1=VIH, A0=VIL) , Status=00H  
BGA = Block Group Address (A12 ~ A20)  
Temporary Block Group Unprotect  
VID  
RESET  
CEF  
Vss,VIL,  
or VIH  
Vss,VIL,  
or VIH  
WEF  
Program or Erase Command Sequence  
tRSP  
tVID  
tVID  
Revision 1.0  
November 2001  
- 39 -  
K5A3x41YT(B)A  
MCP MEMORY  
SRAM AC CHARACTERISTICS  
70ns  
Parameter List  
Symbol  
Units  
Min  
Max  
Read cycle time  
tRC  
tAA  
70  
-
-
70  
70  
35  
70  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
Chip select to output  
Output enable to valid output  
UB, LB Access Time  
tCO1, tCO2  
tOE  
-
-
tBA  
-
Chip select to low-Z output  
Read  
tLZ1, tLZ2  
tBLZ  
10  
10  
5
UB, LB enable to low-Z output  
Output enable to low-Z output  
Chip disable to high-Z output  
UB, LB disable to high-Z output  
Output disable to high-Z output  
Output hold from address change  
Write cycle time  
-
tOLZ  
-
tHZ1, tHZ2  
tBHZ  
tOHZ  
tOH  
0
25  
25  
25  
-
0
0
10  
70  
60  
0
tWC  
-
Chip select to end of write  
Address set-up time  
tCW  
-
tAS  
-
Address valid to end of write  
UB, LB Valid to End of Write  
tAW  
60  
60  
55  
0
-
tBW  
-
Write  
Write pulse width  
tWP  
-
Write recovery time  
tWR  
-
Write to output high-Z  
Data to write time overlap  
Data hold from write time  
End write to output low-Z  
tWHZ  
tDW  
0
25  
-
30  
0
tDH  
-
tOW  
5
-
SRAM DATA RETENTION CHARACTERISTICS  
Item  
Symbol  
VDR  
Test Condition  
CS1S³ VccS-0.2V  
Min  
1.5  
-
Typ  
Max  
3.3  
10  
-
Unit  
VccS for data retention  
Data retention current  
Data retention set-up time  
Recovery time  
-
0.5  
-
V
IDR  
VccS=3.0V, CS1S³ VccS-0.2V  
mA  
tSDR  
0
See data retention waveform  
ns  
tRDR  
tRC  
-
-
1. CS1S³ VccS-0.2V, CS2S³ VccS-0.2V(CS1S controlled) or CS2S£0.2V(CS2S controlled)  
2. Typical values are measured at Ta=25°C , not 100% tested.  
Revision 1.0  
November 2001  
- 40 -  
K5A3x41YT(B)A  
MCP MEMORY  
SRAM TIMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1S=OES=VIL, CS2S=WES=VIH, UB or/and LB=VIL)  
tRC  
Address  
tAA  
tOH  
Data Valid  
Data Out  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WES=VIH)  
tRC  
Address  
tOH  
tAA  
tCO1  
CS1S  
CS2S  
tCO2  
tHZ  
tBA  
UB, LB  
tBHZ  
tOHZ  
tOE  
OES  
tOLZ  
tBLZ  
tLZ  
Data out  
High-Z  
Data Valid  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
Revision 1.0  
November 2001  
- 41 -  
K5A3x41YT(B)A  
MCP MEMORY  
SRAM TIMING DIAGRAMS  
TIMING WAVEFORM OF WRITE CYCLE(1) (WES Controlled)  
tWC  
Address  
CS1S  
tCW(2)  
tWR(4)  
tAW  
CS2S  
tCW(2)  
tBW  
UB, LB  
tWP(1)  
WES  
tAS(3)  
tDW  
tDH  
High-Z  
High-Z  
Data in  
Data out  
Data Valid  
tWHZ  
tOW  
Data Undefined  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1S Controlled)  
tWC  
Address  
tCW(2)  
tAW  
tAS(3)  
tWR(4)  
CS1S  
CS2S  
tBW  
UB, LB  
tWP(1)  
WES  
tDW  
tDH  
Data Valid  
Data in  
Data out  
High-Z  
High-Z  
Revision 1.0  
November 2001  
- 42 -  
K5A3x41YT(B)A  
MCP MEMORY  
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)  
tWC  
Address  
CS1S  
tCW(2)  
tAW  
tWR(4)  
CS2S  
tCW(2)  
tBW  
UB, LB  
tAS(3)  
tWP(1)  
WES  
tDH  
tDW  
Data Valid  
Data in  
High-Z  
Data out  
High-Z  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap(tWP) of low CS1S and low WES. A write begins when CS1S goes low and WES goes low with assert-  
ing UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest  
transition when CS1S goes high and WES goes high. The tWP is measured from the beginning of write to the end of write.  
2. tCW is measured from the CS1S going low to the end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1S or WES going high.  
SRAM DATA RETENTION WAVE FORM  
CS1 controlled  
S
Data Retention Mode  
tSDR  
tRDR  
VccS  
2.7V  
2.2V  
VDR  
CS1S³ VccS - 0.2V  
CS1S  
Vsss  
CS2 controlled  
S
Data Retention Mode  
VccS  
2.7V  
CS2S  
tSDR  
tRDR  
VDR  
CS2S£0.2V  
0.4V  
Vsss  
Revision 1.0  
November 2001  
- 43 -  
K5A3x41YT(B)A  
MCP MEMORY  
PACKAGE DIMENSION  
66-Ball Tape Ball Grid Array Package (measured in millimeters)  
11.00±0.10  
Top View  
#A1  
11.00±0.10  
A
Bottom View  
0.80x11=8.80  
(Datum A)  
B
12 11 10  
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
(Datum B)  
G
H
0.80  
4.40  
66-  
Æ
0.45±0.05  
0.20  
M A B  
Æ
0.45±0.05  
Side View  
0.08MAX  
11.00±0.10  
Revision 1.0  
November 2001  
- 44 -  

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