K5C6481NTM-T355 [SAMSUNG]
Memory Circuit, 4MX16, CMOS, PBGA81, 10.80 X 10.40 MM, 0.80 MM PITCH, TBGA-81;
| 型号： | K5C6481NTM-T355 |
| 厂家： | 
SAMSUNG |
| 描述： | Memory Circuit, 4MX16, CMOS, PBGA81, 10.80 X 10.40 MM, 0.80 MM PITCH, TBGA-81 静态存储器 内存集成电路 |
| 文件： | 总39页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
K5C6481NT(B)M
MCP MEMORY
Document Title
Multi-Chip Package MEMORY
64M Bit (4Mx16) Dual Bank NOR Flash Memory / 8M(512Kx16) Full CMOS SRAM
Revision History
Revision No. History
Draft Date
Remark
0.0 Advance Information
Sep. 7, 2001
Advance
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 0.0
September 2001
- 1 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Multi-Chip Package MEMORY
64M Bit (4Mx16) Dual Bank NOR Flash Memory / 8M(512Kx16) Full CMOS SRAM
FEATURES
GENERAL DESCRIPTION
· Power Supply voltage : 2.7 to 3.0 V
· Organization
- Flash : 4,194,304 x 16 bit
- SRAM : 524,288 x 16 bit
· Access Time (@2.7V)
The K5C6481N(B)M featuring single 3.0V power supply is a Multi
Chip Package Memory which combines 64Mbit Dual Bank Flash
and 8Mbit fCMOS SRAM.
The 64Mbit Flash memory is organized as 4M x16 bit and 8Mbit
SRAM is organized as 1M x16 bit. The 64Mbit Flash memory is
the high performance non-volatile memory fabricated by CMOS
technology for peripheral circuit and DINOR IV(Diveded bit-line
NOR IV) architecture for the memory cell. All memory blocks are
locked and can be programmed or erased, when F-WP is low.
Using Software Lock Release function, program erase operation
can be executed.
- Flash : 85 ns, SRAM : 55 ns
· Power Consumption
- Flash Read Current : 20 mA (Typ.@5MHz)
Sequential Page Read Current : 5 mA (Typ.@5MHz)
Program/Erase Current : 35 mA (Max.)
Standby mode/Deep Power mode : 0.1 mA (Typ.)
- SRAM Operating Current : 28 mA (Max.)
Standby Current : 0.5 mA (Typ.)
· Secode(Security Code) Block : Extra 32KW Block (Flash)
· Block Group Protection / Unprotection (Flash)
· 128 words Page Program (Flash)
· Flash Bank Size : 4Mb / 4Mb / 28Mb / 28Mb
· SRAM Data Retention : 1.5 V (min.)
· Industrial Temperature : -40°C ~ 85°C
· Package :81 - ball TBGA Type - 10.8 x 10.4 mm, 0.8 mm pitch
The 8Mbit SRAM supports low data retention voltage for battery
backup operation with low data retention current.
The K5C6481N(B)M is suitable for use in program and data
memory of mobile communication system to reduce mount area.
This device is available in 81-ball TBGA Type package.
BALL CONFIGURATION
BALL DESCRIPTION
Ball Name
A0 to A18
A19 to A21
DQ0 to DQ15
F-RP
Description
11
12
7
8
9
10
5
6
2
3
4
1
Address Input Balls (Common)
Address Input Balls (Flash Memory)
Data Input/Output Balls (Common)
Hardware Reset (Flash Memory)
Write Protect (Flash Memory)
N.C N.C N.C
N.C N.C N.C
N.C N.C N.C
A
B
N.C
N.C N.C
N.C
F-WP
F-RP
A11
A8
A7
LB
UB
WE
C
D
E
F-WP
12 A15
A
A19
CS2
A3
A2
A1
A6
A5
A4
F-Vcc
Vcc
Power Supply (Flash Memory)
Power Supply (SRAM))
A13 A21
-RY/BY A20
F
A9
A18
A17
A14
N.C
.C
N
A10
F
G
H
J
Vss
Ground (Common)
DQ1
A16
VSS
DQ6
A0
UB
Upper Byte Enable (SRAM)
Lower Byte Enable (SRAM)
Chip Enable (Flash Memory)
Chip Enable (SRAM Low Active)
Chip Enable (SRAM High Active)
Write Enable (Common)
Output Enable (Common)
Ready/Busy (Flash memory)
No Connection
LB
DQ15 F-Vcc
13
DQ9 DQ3 DQ4 DQ
F-CE OE
F-CE
CS1
CS2
WE
Vss
12 DQ7
Vcc DQ
DQ0 DQ10 F-Vcc
CS1
DQ14
11 N.C DQ5
DQ8 DQ2 DQ
K
L
N.C
N.C N.C N.C
N.C N.C
N.C
OE
N.C N.C N.C
N.C N.C
M
F-RY/BY
N.C
81 Ball TBGA , 0.8mm Pitch
Top View (Ball Down)
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 0.0
September 2001
- 2 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
ORDERING INFORMATION
K 5 C 64 81 N T M - T 3 5 5
Samsung
MCP Memory
SRAM Access Time
55 = 55 ns
Device Type
Mitsubishi NOR Flash
+ fCMOS SRAM
Flash Access Time
3 = 85 ns
Package
T = 81 TBGA
NOR Flash Density
(Organization) , (BankSize)
64 : 64Mbit (x16 Selectable)
(4Mb, 4Mb, 28Mb,2 8Mb)
Version
M = 1st Generation
SRAM Density , Organization
8Mbit , x16 Selectable
Block Architecture
T = Top Boot Block
B = Bottom Boot Block
Operating Voltage Range
2.7V to 3.0V
Revision 0.0
September 2001
- 3 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Flash Memory Part
128-word Page Buffer
Main Block 134 32K-word
A21
A20
A19
A18
A17
F-Vcc
Vss
Bank4
56 blocks
Main Block 79 32K-word
Main Block 78 32K-word
Bank3
56 blocks
A16
Address
Input
A15
X-decorder
Main Block 23 32K-word
Main Block 22 32K-word
A14
A13
A12
A11
A10
A9
Bank2
8 blocks
Main Block 15 32K-word
Main Block 14 32K-word
Main Block 8 32K-word
Parameter Block 7 4K-word
Bank1
15 blocks
A8
Parameter Block 2 4K-word
Boot Block 1 4K-word
Bppt Block 0 4K-word
A7
A6
A5
A4
A3
Y-Decorder
Y-Gate / Sense Amp.
A2
A1
A0
Status/ ID Register
Multi Plexer
I/O Buffer
Chip Enable
F-CE
OE
Output Enable
Command
Write
State
Machine
User
Write Enable
Write Protect
WE
Interface
F-WP
F-RP
Reset
/PowerDown
DQ15 DQ14
DQ1
DQ0
Data I/O
FUNCTIONAL BLOCK DIAGRAM (64Mbit Flash Memory)
Revision 0.0
September 2001
- 4 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Table 1. Flash Memory Top Boot Block Address (K5C6481NT)
Address Range
K5C6481NT
Block
Block Size
Word Mode (x16)
3FF000H-3FFFFFH
3FE000H-3FEFFFH
3FD000H-3FDFFFH
3FC000H-3FCFFFH
3FB000H-3FBFFFH
3FA000H-3FAFFFH
3F9000H-3F9FFFH
3F8000H-3F8FFFH
3F0000H-3F7FFFH
3E8000H-3EFFFFH
3E0000H-3E7FFFH
3D8000H-3DFFFFH
3D0000H-3D7FFFH
3C8000H-3CFFFFH
3C0000H-3C7FFFH
3B8000H-3BFFFFH
3B0000H-3B7FFFH
3A8000H-3AFFFFH
3A0000H-3A7FFFH
398000H-39FFFFH
390000H-397FFFH
388000H-38FFFFH
380000H-387FFFH
378000H-37FFFFH
370000H-377FFFH
368000H-36FFFFH
360000H-367FFFH
358000H-35FFFFH
350000H-357FFFH
348000H-34FFFFH
340000H-347FFFH
338000H-33FFFFH
330000H-337FFFH
328000H-32FFFFH
320000H-327FFFH
318000H-31FFFFH
310000H-317FFFH
208000H-20FFFFH
300000H-307FFFH
2F8000H-2FFFFFH
2F0000H-2F7FFFH
2E8000H-2EFFFFH
2E0000H-2E7FFFH
2D8000H-2DFFFFH
2D0000H-2D7FFFH
BA134
BA133
BA132
BA131
BA130
BA129
BA128
BA127
BA126
BA125
BA124
BA123
BA122
BA121
BA120
BA119
BA118
BA117
BA116
BA115
BA114
BA113
BA112
BA111
BA110
BA109
BA108
BA107
BA106
BA105
BA104
BA103
BA102
BA101
BA100
BA99
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
Bank4
4 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
Bank3
Bank2
BA98
BA97
BA96
BA95
BA94
BA93
BA92
BA91
BA90
Revision 0.0
September 2001
- 5 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Table 1. Flash Memory Top Boot Block Address (K5C6481NT)
Address Range
K5C6481NT
Block
Block Size
Word Mode (x16)
2C8000H-2CFFFFH
2C0000H-2C7FFFH
2B8000H-2BFFFFH
2B0000H-2B7FFFH
2A8000H-2AFFFFH
2A0000H-2A7FFFH
298000H-29FFFFH
290000H-297FFFH
288000H-28FFFFH
280000H-287FFFH
278000H-27FFFFH
270000H-277FFFH
268000H-26FFFFH
260000H-267FFFH
258000H-25FFFFH
250000H-257FFFH
248000H-24FFFFH
240000H-247FFFH
238000H-23FFFFH
230000H-237FFFH
228000H-22FFFFH
220000H-227FFFH
218000H-21FFFFH
210000H-217FFFH
208000H-20FFFFH
200000H-207FFFH
1F8000H-1FFFFFH
1F0000H-1F7FFFH
1E8000H-1EFFFFH
1E0000H-1E7FFFH
1D8000H-1DFFFFH
1D0000H-1D7FFFH
1C8000H-1CFFFFH
1C0000H-1C7FFFH
1B8000H-1BFFFFH
1B0000H-1B7FFFH
1A8000H-1AFFFFH
1A0000H-1A7FFFH
198000H-19FFFFH
190000H-197FFFH
188000H-18FFFFH
180000H-187FFFH
178000H-17FFFFH
170000H-177FFFH
168000H-16FFFFH
BA89
BA88
BA87
BA86
BA85
BA84
BA83
BA82
BA81
BA80
BA79
BA78
BA77
BA76
BA75
BA74
BA73
BA72
BA71
BA70
BA69
BA68
BA67
BA66
BA65
BA64
BA63
BA62
BA61
BA60
BA59
BA58
BA57
BA56
BA55
BA54
BA53
BA52
BA51
BA50
BA49
BA48
BA47
BA46
BA45
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
Bank2
Bank1
Revision 0.0
September 2001
- 6 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Table 1. Flash Memory Top Boot Block Address (K5C6481NT)
Address Range
K5C6481NT
Block
Block Size
Word Mode (x16)
160000H-167FFFH
158000H-15FFFFH
150000H-157FFFH
148000H-14FFFFH
140000H-147FFFH
138000H-13FFFFH
130000H-137FFFH
128000H-12FFFFH
120000H-127FFFH
118000H-11FFFFH
110000H-117FFFH
108000H-10FFFFH
100000H-107FFFH
F8000H-FFFFFH
F0000H-F7FFFH
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
00000H-07FFFH
BA44
BA43
BA42
BA41
BA40
BA39
BA38
BA37
BA36
BA35
BA34
BA33
BA32
BA31
BA30
BA29
BA28
BA27
BA26
BA25
BA24
BA23
BA22
BA21
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
Bank1
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
Revision 0.0
September 2001
- 7 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Table 2. Flash Memory Bottom Boot Block Address (K5C6481NB)
Address Range
K5C6481NB
Block
Block Size
Word Mode (x16)
3F8000H-3FFFFFH
3F0000H-3F7FFFH
3E8000H-3EFFFFH
3E0000H-3E7FFFH
3D8000H-3DFFFFH
3D0000H-3D7FFFH
3C8000H-3CFFFFH
3C0000H-3C7FFFH
3B8000H-3BFFFFH
3B0000H-3B7FFFH
3A8000H-3AFFFFH
3A0000H-3A7FFFH
398000H-39FFFFH
390000H-397FFFH
388000H-38FFFFH
380000H-387FFFH
378000H-37FFFFH
370000H-377FFFH
368000H-36FFFFH
360000H-367FFFH
358000H-35FFFFH
350000H-357FFFH
348000H-34FFFFH
340000H-347FFFH
338000H-33FFFFH
330000H-337FFFH
328000H-32FFFFH
320000H-327FFFH
318000H-31FFFFH
310000H-317FFFH
208000H-20FFFFH
300000H-307FFFH
2F8000H-2FFFFFH
2F0000H-2F7FFFH
2E8000H-2EFFFFH
2E0000H-2E7FFFH
2D8000H-2DFFFFH
2D0000H-2D7FFFH
2C8000H-2CFFFFH
2C0000H-2C7FFFH
2B8000H-2BFFFFH
2B0000H-2B7FFFH
2A8000H-2AFFFFH
2A0000H-2A7FFFH
298000H-29FFFFH
BA134
BA133
BA132
BA131
BA130
BA129
BA128
BA127
BA126
BA125
BA124
BA123
BA122
BA121
BA120
BA119
BA118
BA117
BA116
BA115
BA114
BA113
BA112
BA111
BA110
BA109
BA108
BA107
BA106
BA105
BA104
BA103
BA102
BA101
BA100
BA99
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
Bank4
BA98
BA97
BA96
BA95
BA94
BA93
BA92
BA91
BA90
Revision 0.0
September 2001
- 8 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Table 2. Flash Memory Bottom Boot Block Address (K5C6481NB)
Address Range
K5C6481NB
Block
Block Size
Word Mode (x16)
290000H-297FFFH
288000H-28FFFFH
280000H-287FFFH
278000H-27FFFFH
270000H-277FFFH
268000H-26FFFFH
260000H-267FFFH
258000H-25FFFFH
250000H-257FFFH
248000H-24FFFFH
240000H-247FFFH
238000H-23FFFFH
230000H-237FFFH
228000H-22FFFFH
220000H-227FFFH
218000H-21FFFFH
210000H-217FFFH
208000H-20FFFFH
200000H-207FFFH
1F8000H-1FFFFFH
1F0000H-1F7FFFH
1E8000H-1EFFFFH
1E0000H-1E7FFFH
1D8000H-1DFFFFH
1D0000H-1D7FFFH
1C8000H-1CFFFFH
1C0000H-1C7FFFH
1B8000H-1BFFFFH
1B0000H-1B7FFFH
1A8000H-1AFFFFH
1A0000H-1A7FFFH
198000H-19FFFFH
190000H-197FFFH
188000H-18FFFFH
180000H-187FFFH
178000H-17FFFFH
170000H-177FFFH
168000H-16FFFFH
160000H-167FFFH
158000H-15FFFFH
150000H-157FFFH
148000H-14FFFFH
140000H-147FFFH
138000H-13FFFFH
130000H-137FFFH
BA89
BA88
BA87
BA86
BA85
BA84
BA83
BA82
BA81
BA80
BA79
BA78
BA77
BA76
BA75
BA74
BA73
BA72
BA71
BA70
BA69
BA68
BA67
BA66
BA65
BA64
BA63
BA62
BA61
BA60
BA59
BA58
BA57
BA56
BA55
BA54
BA53
BA52
BA51
BA50
BA49
BA48
BA47
BA46
BA45
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
Bank4
Bank3
Revision 0.0
September 2001
- 9 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Table 2. Flash Memory Bottom Boot Block Address (K5C6481NB)
Address Range
K5C6481NB
Block
Block Size
Word Mode (x16)
128000H-12FFFFH
120000H-127FFFH
118000H-11FFFFH
110000H-117FFFH
108000H-10FFFFH
100000H-107FFFH
F8000H-FFFFFH
F0000H-F7FFFH
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
07000H-07FFFH
06000H-06FFFH
05000H-05FFFH
04000H-04FFFH
03000H-03FFFH
02000H-02FFFH
01000H-01FFFH
00000H-00FFFH
BA44
BA43
BA42
BA41
BA40
BA39
BA38
BA37
BA36
BA35
BA34
BA33
BA32
BA31
BA30
BA29
BA28
BA27
BA26
BA25
BA24
BA23
BA22
BA21
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
Bank3
Bank2
BA8
Bank1
BA7
BA6
4 Kwords
BA5
4 Kwords
BA4
4 Kwords
BA3
4 Kwords
BA2
4 Kwords
BA1
4 Kwords
BA0
4 Kwords
Revision 0.0
September 2001
- 10 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Flash MEMORY COMMAND DEFINITION
Table 3. Command List (F-WP = VIH or VIL)
1st Cycle
2nd Cycle
Address
3rd Cycle
Command
Data1)
Data1)
(DQ0-15)
Data1)
(DQ0-15)
Mode
Address
Mode
Mode
Address
(DQ0-15)
A21-A18
A0
Read Array
Write
Write
Write
Write
Write
Write
FFH
F3H
90H
70H
50H
B0H
X
X
SA5)
SA+i6)
Sequential Page Read
Device Identifier
Read Status Register
Clear Status Register
Suspend
Read
Read
Read
RD0
ID
Read
RDi
IA3)
Bank2)
Bank2)
SRD4)
Bank2)
X
Bank2)
Bank2)
Bank2)
Resume
Write
D0H
Notes : 1. Upper byte data (DQ15-DQ8) is ignored.
2. Bank=Bank address (bank1-Bank4:A21-18)
3. IA=ID code address:A0=VIL (Manufacture’s code):A0=VIH (Device code), ID=ID code
4. SRD=Status Register Data
5. SA=Sequential page Address:A21-A3, A2-A0:0h
6. SA+i;A21-A3 must be flxed and A2-A0 must be incremented from 0h to 7h.
Table 4. Command List (F-WP = VIH)
1st Cycle
2nd Cycle
Address
3rd Cycle
Address
Command
Data1)
(DQ0-15)
Data1)
(DQ0-15)
Data1)
(DQ0-15)
Mode
Address
Mode
Mode
WA2)
WA03)
WA4)
BA5)
X
WD2)
WD03)
D01)
Word Program
Write
Write
Write
Write
Write
Bank
Bank
Bank
Bank
X
40H
41H
0EH
20H
A7H
Write
Write
Write
Write
Write
WAn3)
WDn3)
Page Program
Write
Page Buffer to Flash
Block Erase / Confirm
Erase All Unlocked Blocks
D01)
D01)
D01)
WD
Clear Page Buffer
Write
Write
Write
X
55H
74H
F1H
Write
Write
Write
X
Single Date Load to Page Buffer
Flash to Page Buffer
Bank
Bank
WA
RA6)
D01)
Notes : 1. Upper byte data (DQ15-DQ8) is ignored.
2. WA=Write Address, WD=Write Data
3. WA0, WAn=Write Address, WD0, WDn=Write Data, Write address and write data must be provided sequentially from 00H to 7FH
for A6-A0. Page size is 128 words (128-word x 16-bit), and also A21-A7(block address, page address) must be valid.
4. WA=Write Address:A21-A7 (block address, page address) must be valid.
5. BA=Block Address:A21-A12(Bank1), A21-A15(Bank2, Bank3, Bank4)
6. RA=Read Address:A21-A7 (block address, page address) must be valid.
Revision 0.0
September 2001
- 11 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Flash MEMORY COMMAND DEFINITION
Software lock release operation needs following consecutive 7bus cycles. Moreover, additional 127 bus cycles are needed for page
program operation.
Table 5. Command List (F-WP = VIH or VIL)
1st Cycle
2nd Cycle
Address
3rd Cycle
Address
Setup Command for
Software Lock Release
Data1)
(DQ0-15)
Data1)
(DQ0-15)
Data1)
(DQ0-15)
Mode
Address
Mode
Mode
Block6)
Block6)
Block6)
Block6)
Block6)
Block6)
Block6)
Block6)
Word Program
Write
Write
Write
Write
Write
Write
Write
Write
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
60H
60H
60H
60H
60H
60H
60H
60H
Write
Write
Write
Write
Write
Write
Write
Write
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Write
Write
Write
Write
Write
Write
Write
Write
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
ACH
ACH
ACH
ACH
ACH
ACH
ACH
ACH
Page Program3)
Page Buffer to Flash
Block Erase / Confirm
Erase All Unlocked Blocks
Clear Page Buffer
Single Data Load to Page Buffer
Flash to Page Buffer
4th Cycle
Address
5th Cycle
Address
Setup Command for
Software Lock Release
Data1)
(DQ0-15)
Data1)
(DQ0-15)
Mode
Mode
Block6)
Block6)
Block6)
Block6)
Block6)
Block6)
Block6)
Block6)
Word Program
Write
Write
Write
Write
Write
Write
Write
Write
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Write
Write
Write
Write
Write
Write
Write
Write
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
78H
78H
78H
78H
78H
78H
78H
78H
Page Program3)
Page Buffer to Flash
Block Erase / Confirm
Erase All Unlocked Blocks
Clear Page Buffer
Single Data Load to Page Buffer
Flash to Page Buffer
6th Cycle
Address
7th Cycle
Address
8th-134th Cycle
Data1)
Address
Setup Command for
Software Lock Release
Data1)
(DQ0-15)
Data1)
(DQ0-15)
Mode
Mode
Mode
(DQ0-15)
WA2)
WA03)
WA4)
BA5)
X
WD2)
WD03)
D01)
Word Program
Write
Write
Write
Write
Write
Bank
Bank
Bank
Bank
X
40h
41h
0Eh
20H
A7H
Write
Write
Write
Write
Write
Page Program3)
WAn3)
WDn3)
Write
Page Buffer to Flash
D01)
Block Erase / Confirm
D01)
Erase All Unlocked Blocks
D01)
WD
Clear Page Buffer
Write
Write
Write
X
55H
74H
F1H
Write
Write
Write
X
Single Data Load to Page Buffer
Flash to Page Buffer
Bank
Bank
WA
RA7)
D01)
Notes : 1. Upper byte data (DQ15-DQ8) is ignored.
2. WA=Write Address, WD=Write Data
3. WA0, WAn=Write Address, WD0, WDn=Write Data, Write address and write data must be provided sequentially from 00H to 7FH
for A6-A0. Page size is 128 words (128 word x 16 bit), and also A21-A7(block address, page address) must be valid.
4. WA=Write Address:A21-A7 (block address, page address) must be valid.
5. BA=Block Address:A21-A12(Bank1), A21-A15(Bank2, Bank3, Bank4)
6. Block=Block Address:A21-A15, Block=A21-A15
Address
Block
DQ7
DQ6
A21
A21
DQ5
A20
A20
DQ4
A19
A19
DQ3
A18
A18
DQ2
A17
A17
DQ1
A16
A16
DQ0
A15
A15
Fixed0
Fixed0
Block
7. RA=Read Address: A21-A7 (block address, page address) must be valid.
- 12 -
Revision 0.0
September 2001
Advance Information
K5C6481NT(B)M
MCP MEMORY
Table 6. Device ID Code
Code \ Pins
A0
VIL
VIH
VIH
DQ7
"0"
DQ6
"0"
DQ5
"0"
DQ4
"1"
DQ3
"1"
DQ2
"1"
DQ1
"0"
DQ0
"0"
Hex Date
1CH
Manufacturer Code
Devide Code (Bottom Boot)
Devide Code (Top Boot)
"0"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
2AH
"0"
"0"
"1"
"0"
"1"
"0"
"1"
"1"
2BH
The output of upper byte data (DQ15-DQ7) is "0".
Table 7. Block Locking
Write Protection Provided
Bank2
F-RP
F-WP
Bank1
Bank3
Main
Bank4
Notes
Boot
Parameter/Main
Main
Main
VIL
x
Locked
Locked
Locked
Locked
Locked
Deep Power Down Mode
All Blocks Locked
(Valid to operate Software Lock Release)
Locked
Locked
Locked
Locked
VIL
VIH
Locked
VIH
Unlocked
Unlocked
Unlocked
Unlocked
Unlocked
All Blocks Unlocked
F-WP pin must not be switched during performing Read / Write operations or WSM busy (WSMS=0).
Table 8. Status Register
Definition
Symbol
Status
(I/O Pin)
"1"
"0"
S.R.7 (AQ7)
S.R.6 (DQ6)
S.R.5 (DQ5)
S.R.4 (DQ4)
S.R.3 (DQ3)
S.R.2 (DQ2)
S.R.1 (DQ1)
S.R.0 (DQ0)
Write State Machine Status
Suspend Status
Erase Status
Ready
Busy
Suspended
Operation in Progress/Completed
Error
Successful
Program Status
Block Status after Program
Reserved
Error
Successful
Error
Successful
-
-
-
-
-
-
Reserved
Reserved
Table 9. Flash Memory Operation Table
Mode \ Pins
Array
F-CE
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
X
OE
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
WE
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
X
F-RP
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
DQ0-15
Data-Output
Data-Output
Status Register Data
Identifier Code
High-Z
Sequential
Read
Write
Status Register
Identifier Code
Output Disable
Program
Erase
Command / Data-In
Command
Others
Command
X1)
X
Standby
Deep Power Down
High-Z
X
High-z
Notes : 1. X cab be VIH or VIL for control pins
Revision 0.0
September 2001
- 13 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Flash DEVICE OPERATION
The 64Mbit DINOR IV Flash Memory includes on-chip program/erase control circuitry. The Write State Machine(WSM) control block
erase and word/page program operations. Operational modes are selected by the commands written to the Command User Inter-
face (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or
block erase operation.
A Deep Power Down mode is enabled when the F-RP pin is at Vss, minimizing power consumption.
Read Mode
The 64Mbit DINOR IV Flash Memory has four read modes, which accesses to the memory array, the Sequential Page Read, the
Device Identifier and the Status Register. The appropriate read commands are required to be written to the CUI. Upon initial device
power up or after exit from deep power down, the 64Mbit DINOR IV Flash Memory automatically resets to read array mode. In the
read array mode and in the conditions are low level input to OE, high level input to WE and F-RP, low level input to F-CE and
address signals to the address inputs (A21 - A0) the data of the addressed location to the data input/output (DQ15-DQ0) is output.
Standby Mode
When F-CE is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-
impedance (High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and
the device consumes normal active power until the operation completes.
Output Disable
When OE is at VIH, output from the devices is disabled. Data input/output are in a high-impedance (High-Z) state.
Automatic Power Down (APD)
The Automatic Power Down minimizes the power consumption during read mode. The device automatically turns to this mode when
any addresses or F-CE isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the
stand-by mode. During this mode, the output data is latched and can be read out. New data is read out correctly when addresses
are changed.
Deep Power Down
When F-RP is at VIL, the device is in the deep power down mode and its power consumption is substantially low. During read
modes, the memory is deselected and the data input/output are in a high-impedance (High-Z) state. After return from power down,
the CUI is reset to Read Array, and the Status Register is cleared to value 80H. During block erase or program modes, F-RP low will
abort either operation. Memory array data of the block being altered become invalid.
Write Mode
Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by bringing WE to low level and OE is at high level, while F-CE is at low
level. Address and data are latched on the earlier rising edge of WE and F-CE. Standard micro processor write timings are used.
Alternating Background Operation (BGO)
The 64Mbit DINOR IV Flash Memory allows to read array from one bank while the other bank operates in software command write
cycling or the erasing / programming operation in the background. Array Read operation with the other bank in BGO is performed by
changing the bank address without any additional command. When the bank address points the bank in software command write
cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same
as the normal read operation. BGO must be between Bank1, Bank2, Bank3, and Bank4.
Back Bank array Read (BBR)
In the 64Mbit DINOR IV Flash Memory , when one memory address is read according to a Read Mode in the case of the same as an
access when a Read Mode command is input, an another Bank memory data can be read out (Random or Sequential Mode) by
changing an another Bank address.
Revision 0.0
September 2001
- 14 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Software Command Definitions
TThe device operations are selected by writing specific software command into the Commnad User Interface.
Read Array Command (FFH)
The device is in Read Array mode on initial device power up and after exit from deep power down, or by writing FFH to the Com-
mand User Interface. After starting the internal operation the device is set to the read status register mode automatically.
Sequential Page Read Command (F3H)
The Sequential Page Read command (F3H) timing can be used by writing the first command. This command is fast sequential 8
words read. During the read it is necessary to fix F-CE low and increase the addresses sequentially from 0h to 7h. The mode is kept
until Read Array command is input. The first read of Seq. Page Read timing is the same as normal read (ta(CE)). F-CE should be
fallen “L”. The read timing after the first is fast read (ta(PAD)). When an another sequential page (A21-A3) is accessed before one
sequential page (one 8-word) read is not finished, once F-CE is at VIH and A2-A0 data are 0h, after that F-CE is at VIL we can use
the first read of Seq. Page Read or normal read (ta(CE)).
Read Device Indentifier Command (90H)
We can normally read device identifier codes when Read Device Identifier Code Command (90H) is written to the command latch.
Following the command write, the manufacturer code and the device code can be read from address 0000H and 0001H, respec-
tively.
Read Status Register Command (70H)
The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after
starting the internal operation the device is set to the Read Status Register mode automatically. The contents of Status Register are
latched on the later falling edge of OE must be toggled every status read.
Clear Status Register Command (50H)
The Erase Status, Program Status and Block Status bits are set to "1"s by the Write State Machine and can only be reset by the
Clear Status Register command of 50H. These bits indicate various failure conditions. status read.
Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation.
Program Commands
1) Word Program (40H)
Word program is executed by a two-command sequence. The Word program Setup command of 40H is written to the Command
Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application
and verify operation.
2) Page Program for Data Blocks (41H)
Page Program allows fast programming of 128words of data. Writing of 41H initiates the page program operation for the Data area.
From 2nd cycle to 129th cycle, write data must be serially inputted. Address A6-A0 have to be incremented from 00H to 7FH. After
completion of data loading, the WSM controls the program pulse application and verify operation.
3) Single Data Load to Page Buffer (74H) / Page Buffer to Flash (0EH/D0H)
Single data load to the page buffer is performed by writing 74H followed by a second write specifying the column address and data.
Distinct data up to 128word can be loaded to the page buffer by this two-command sequence. On the other hand, all of the loaded
data to the page buffer is programmed simultaneously by writing Page Buffer to Flash command of 0EH followed by the
confirm command of D0H. After completion of programming the data on the page buffer is cleared automatically.
Revision 0.0
September 2001
- 15 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Flash to Page Buffer Command (F1H/D0H)
Array data load to the page buffer is performed by writing the Flash to Page Buffer command of F1H followed by the Confirm com-
mand of D0H. An address within the page to be loaded is required. Then the array data can be copied into the other pages within the
same bank by using the Page Buffer to Flash command.
Clear Page Buffer Command (55H/D0H)
Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of
D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command.
Suspend/Resume Command (B0H/D0H)
Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from
another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and
allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The
device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and
Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the
Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume com-
mand of D0H is written to the CUI, the WSM will continue with the erase or program processes.
Data Protection
The 64M-bit DINOR(IV) Flash Memory has a master Write Protect pin (F-WP). When F-WP is at VIH, all blocks can be programmed
or erased. When F-WP is low, all blocks are in locked mode which prevents any modifications to memory blocks. Software Lock
Release function is only command which allows to program or erase. See the BLOCK LOCKING table on 13 page for details.
Power Supply Voltage
When the power supply voltage is less than VLKO, Low Vcc Lock-Out voltage, the device is set to the Read-only mode. Regarding
DC electrical characteristics of VLKO, see 18 page. A delay time of 2us is required before any device operation is initiated. The delay
time is measured from the time Vcc reaches Vccmin (2.7V). During power up, F-RP = Vss is recommended. Falling in Busy status is
not recommended for possibility of damaging the device.
Memory Organization
The 64Mbit DINOR IV Flash Memory is constructed by 2 boot blocks of 4K words, 6 parameter blocks of 4K words and 7 main
blocks of 32K words in Bank1, by 8 main blocks of 32K words in Bank2 and by 56 main blocks of 32K words in Bank3 and Bank4.
CAPACITANCE
Item
A21-A0, OE, WE, CS2.
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
TA=25°C,
f=1MHz,
Vin=Vout=0V
Input Capacitance
Output Capacitance
F-CE, F-WP, F-RP
DQ15-DQ0, F-RY/BY
COUT
12
pF
Revision 0.0
September 2001
- 16 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
F-Vcc
VI1
Conditions
Rating
Unit
F-Vcc Voltage
With Respect to Vss
-0.2 to +4.6
-0.6 to +4.6
-20 to +85
-50 to +95
-65 to +125
100 (Max.)
V
All input or Output Voltage1)
Ambient Temperature
Ta
°C
Temperature under Bias
Storage Temperature
Tbs
Tstg
Iout
Outputs Short Circuit Current
mA
Notes : 1. Minimum DC voltage is -0.5V on input / output pins. During transitions, the level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input / output pins is F-Vcc+0.5V which, during transitions, may overshoot to F-Vcc+1.5V for periods <20ns.
DC CHARACTERISTICS
Sym-
bol
Typ1)
Parameter
Test Conditions
0V<VIN<F-Vcc
Min
Max
Unit
Input Leakage Current
ILI
mA
mA
mA
±1.0
±1.0
Output Leackage Current
ILO
0V<VOUT<F-Vcc
F-Vcc=3.0V, VIN=VIL/VIH,
F-CE=F-RP=F-WP=VIH
ISB1
50
200
Vcc Standby Current
F-Vcc=3.0V, VIN=Vss/F-Vcc,
F-CE=F-RP=F-WP=F-Vcc±0.3V
ISB2
ISB3
ISB4
0.1
5
5
15
5
mA
mA
mA
F-Vcc=3.0V, VIN/VIH, F-RP=VIL
Vcc Deep Power Down Current
Vcc Read Current for Word
F-Vcc=3.0V, VIN=Vss or F-Vcc,
F-RP=F-Vss±0.3V
0.1
5MHz
20
4
30
8
mA
mA
mA
F-Vcc=3.0V, VIN=VIL/VIH,
F-RP=WE=VIH,
F-CE=OE=VIL, Iout=0mA
ICC1
1MHz
5MHz
Vcc Sequential Page Read Current
Vcc Write Current for Word
ICC1P
ICC2
5
10
F-Vcc=3.0V, VIN=VIL/VIH,
F-RP=OE=VIH, F-CE=WE=VIL
15
35
35
mA
mA
mA
mA
F-Vcc=3.0V, VIN=VIL/VIH,
F-CE=F-RP=F-WP=VIH
Vcc Program Current
Vcc Erase Current
ICC3
ICC4
F-Vcc=3.0V, VIN=VIL/VIH,
F-CE=F-RP=F-WP=VIH
Vcc Suspend Current
F-Vcc=3.0V, VIN=VIL/VIH,
F-CE=F-RP=F-WP=VIH
ICC5
VIL
200
0.8
-0.5
2.0
Input Low Voltage
Input High Voltage
V
V
F-Vcc
+0.5
VIH
Output Low Voltage
Output High Voltage
VOL
VOH1
IOL=4.0mA
0.45
V
V
0.85x
F-Vcc
IOH=-2.0mA
F-Vcc
-0.4
VOH2
VLKO
IOL=4-100mA
V
V
Low F-Vcc Lock Out Voltage2)
1.5
2.2
Notes : All currents are in RMS unless otherwise noted
1. Typical values at F-Vcc=2.85V, Ta=25°C.
2. To protect initiation of write cycle during F-Vcc power up / down, a write cycle is locked out for F-Vcc less than VLKO, Write State Machine
is in Busy state, if F-Vcc is less than VLKO, the alteration of memory contents may occur.
Revision 0.0
September 2001
- 17 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC CHARACTERISTICS
Read Only Mode
Vcc=2.7V~3.0V
Unit
Parameter
Symbol
tAVAV
Min
Typ
Max
Read Cycle Time
tRC
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
ta(AD)
ta(CE)
ta(OE)
ta(PAD)
tASPR
tCEHRR
tRPCRR
tCLZ
tAVQV
tELQV
tGLQV
85
85
30
45
Chip Enable Access Time
Output Enable Access Time
Sequential Page Access Time (After 2nd Cycle)
Sequential Page Setup Time
-20
15
Sequential Page Read F-CE "H" Time
Maximum Valid Time of Sequential Page Read
Chip Enable to Output in Low-Z
Chip Enable High to Output in High-Z
Output Enablr to Output in Low-Z
Output Enable to High to Output in High-Z
F-RP Low to Output High-Z
20
25
tELQX
tEHQZ
tGLQX
tGHQZ
tPLQZ
tOH
0
0
tDF(CE)
tOLZ
tDF(OE)
tPHZ
25
150
Output Hold from F-CE , OE and Address
tOH
0
OE hold from WE High
tOEH
tPS
tWHGL
tPHEL
10
ns
ns
F-RP Recovery to CE Low
150
Notes : 1. Timing measurements are made under AC waveforms for read operation.
Read / Write Mode (WE Control)
Vcc=2.7V~3.0V
Typ
Parameter
Symbol
tAVAV
Unit
Min
85
35
0
Max
Wrie Cycle Time
tWC
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
Address Setup Time
tAVWH
tWHAX
tDVWH
tWHDX
tWHGL
tELWL
Address Hold Time
tAH
Data Setup time
tDS
35
0
Data Hold time
tDH
OE Holf from WE High
Chip Enable Setup Time
Chip Enable Hold Time
Write Pulse Width
tOEH
tCS
10
0
tCH
tWHEH
tWLWH
tWHWL
tGHWL
tPHHWH
tQVPH
0
tWP
tWPH
tGHWL
tBLS
tBLH
35
30
0
Write Pulse Width High
OE Hold to WE Low
Block Lock Setup to Write Enable High
Block Lock Hold from Valid SRD
85
0
Duration of Auto Program Operation (Word Mode) tDAP
Duration of Auto Program Operation (Page Mode) tDAP
tWHRH1
tWHRH1
30
4
300
80
Duration of Auto Block Erase Operation
Delay Time to Begin Internal Operation
F-RP Recovery to F-CE Low
tDAE
tWHRL
tPS
tWHRH2
tWHRL
tPHWL
150
ms
ns
ns
600
85
150
Notes : 1. Read timing parameters during command write operations mode are the same as during read only operation mode.
2. Typical values at F-Vcc=2.85V and Ta=25°C.
Revision 0.0
September 2001
- 18 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC CHARACTERISTICS
Read / Write Mode (CE Control)
Vcc=2.7V~3.0V
Unit
Parameter
Symbol
tAVAV
Min
85
35
0
Typ
Max
Write Cycle Time
tWC
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
Address Setup Time
Address Hold Time
tAVWH
tWHAX
tDVWH
tWHDX
tWHGL
tWLEL
tAH
Data Setup Time
tDS
35
0
Data Hold Time
tDH
OE Hold from WE High
Write Enable Setup Time
Write Enable Hold Time
F-CE Pulse Width
tOEH
tWS
10
0
tWH
tCEP
tCEPH
tGHEL
tBLS
tBLH
tEHWH
tELEH
0
35
30
85
85
0
F-CE "H" Pulse Width
OE Hold to WE Low
tEHEL
tGHEL
Block Lock Setup to Write Enable High
Block Lock Hold from Valid SRD
tPHHWH
tQVPH
tWHRH1
tWHRH1
Duration of Auto Program Operation (Word Mode) tDAP
Duration of Auto Program Operation (Page Mode) tDAP
30
4
300
80
Duration of Auto Block Erase Operation
Delay Time to Begin Internal Operation
F-RP Recovery to F-CE Low
tDAE
tEHRL
tPS
tWHRH2
tEHRL
150
ms
ns
ns
600
90
tPHWL
150
Notes : 1. Timing measurements are made under AC waveforms for read operations
2. Typical values at F-Vcc=2.85V and Ta=25°C.
Program / Erase Time
Parameter
Block Erase Time
Min
Typ
150
1
Max
Unit
600
4
ms
sec
ms
ms
Main Block Write Time
Page Write Time
4
80
Flash to Page Buffer Time
100
150
Program Suspend / Erase Suspend Time
Parameter
Program Suspend Time
Erase Suspend Time
Min
Typ
Max
15
Unit
ms
15
ms
F-Vcc Power up / Down timing
Parameter
Min
Typ
Max
Unit
ms
tVCS
F-RP=VIH Setup Time from F-Vcc min.
2
15
Please see 21 page.
During power up / down, by the noise pulses on control pins, the device has possibility of accidental erase of programming. The device must be
protected against initiation of write cycle for memory contents during power up / down. The delay time of min. 2 micro sec is always required
before read operation or write operation is initiated from the time F-Vcc reaches F-Vcc min. during power up /down. By holding F-RP=VIL, the
contents of memory is protected during F-Vcc power up / down. During power up, F-RP must be held VIL for min. 2us form the time F-Vcc
reaches F-Vcc min.. During power down, F-RP must be held VIL until F-Vcc reaches Vss. F-RP doesn’t have latch mode, therefore F-RP must be
held VIH during read operation or erase / program operation.
Revision 0.0
September 2001
- 19 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
F-Vcc Power up / dowm Timing
Read /Write Inhibit
Read /Write Inhibit
Read /Write Inhibit
2.85V
VCC
Vss
tVCS
VIH
F-RP
VIL
VIH
F-CE
VIL
tPS
tPS
VIH
WE
VIL
AC Waveforms for Read Operation and Test Conditions
tRC
VIH
Address
Address
VIL
ta(AD)
VIH
F-CE
VIL
ta(CE)
tDF(CE)
VIH
OE
or
VIL
tOEH
tDF(OE)
VIH
ta(OE)
WE
VIL
tOH
tOLZ
tCLZ
VIH
VIL
High-Z
High-Z
DATA
F-RP
tPS
tPHZ
VIH
VIL
1.3V
1N914
TEST CONDITIONS
FOR AC CHARACTERISTICS
Input Voltage: VIL=0V, VIH=Flash VCC
Input Rise and Fall Times: £5ns
Reference Voltage
3.3kohm
DUT
at timing measurement: (Flash VCC)/2
Output Load: 1TTL gate + CL(30pF)
Revision 0.0
September 2001
- 20 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC Waveforms for Sequential Page Read Operation
VIH
Address
A21 ~ A3
Address
Address
VIL
VIH
Address
0H
1H
2H
3H
4H
5H
6H
7H
A2 ~ A0
F-CE
OE
VIL
VIH
VIL
VIH
VIL
VIH
VIL
WE
ta(AD)
ta(CE)
ta(PAD)
ta(PAD)
ta(PAD)
ta(PAD)
ta(PAD)
Valid
ta(PAD)
ta(PAD)
VIH
VIL
High-Z
F3H
DOUT
Valid
Valid
Valid
Valid
Valid
Valid
DATA
Revision 0.0
September 2001
- 21 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC Waveforms for Word Program Operation(WE Control)
Address
A21 ~ A0
VIH
VIL
Bank Address
Valid
Address Vaild
tAS
Bank Address
Program
Read Status Register
Write Read Register
tWC
tAH
VIH
VIL
F-CE
OE
tCS
tCH
ta(CE)
VIH
VIL
tWPH
tOEH
tWP
ta(OE)
VIH
VIL
WE
tWHRL
tDH
tDS
VIH
VIL
High-Z
SR
Busy
SR
Ready
40H
DIN
FFH
DATA
F-RP
F-WP
tPS
VIH
VIL
tDAP
tBLH
tBLS
VIH
VIL
AC Waveforms for Word Program Operation(CE Control)
Address
A21 ~ A0
VIH
VIL
Bank Address
Valid
Address Vaild
tAS
Bank Address Valid
Write Read Register
Program
Read Status Register
tWC
tAH
VIH
VIL
F-CE
OE
ta(CE)
ta(OE)
VIH
VIL
tCEP
tOEH
tWS
tWH
tDS
VIH
VIL
WE
tEHRL
VIH
VIL
High-Z
SR
Busy
SR
Ready
40H
DIN
FFH
DATA
F-RP
F-WP
tPS
tDH
VIH
VIL
tDAP
tBLH
tBLS
VIH
VIL
Revision 0.0
September 2001
- 22 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC Waveforms for Page Program Operation(WE Control)
Address
A21 ~ A7
VIH
VIL
Bank Address
Vaild
The Other Bank
Address Vaild
Address Vaild
Address Vaild
Bank Address Vaild
Read Status Register
Write Read Register
VIH
VIL
A6 ~ A0
F-CE
OE
00H
tAS
Vaild
tAH
01H-7EH
7FH
tWC
ta(CE)
VIH
VIL
tCS
tCH
ta(CE)
ta(OE)
VIH
VIL
tGHWL
tWP
tWPH
tOEH
tOEH
ta(OE)
VIH
VIL
WE
tWHRL
tDH
VIH
VIL
High-Z
SR
SR
Ready
41H
DIN
DOU
DIN
DIN
FFH
DATA
F-RP
F-WP
Busy
tDS
tDAP
VIH
VIL
tBLH
tBLS
VIH
VIL
AC Waveforms for Page Program Operation(CE Control)
Address
A21 ~ A7
VIH
VIL
Bank Address
Vaild
The Other Bank
Address Vaild
Address Vaild
Address Vaild
Bank Address Vaild
Read Status Register
Write Read Register
VIH
VIL
A6 ~ A0
00H
tAS
Vaild
tAH
01H-7EH
7FH
tWC
ta(CE)
VIH
VIL
F-CE
OE
tWS
tWH
ta(CE)
ta(OE)
VIH
VIL
tGHWL
tCEPH
tCEP
tOEH
tOEH
ta(OE)
VIH
VIL
WE
tEHRL
tDH
VIH
VIL
High-Z
SR
SR
Ready
DOU
41H
DIN
DIN
DIN
FFH
DATA
F-RP
F-WP
Busy
tPS
tDS
tDAP
VIH
VIL
tBLH
tBLS
VIH
VIL
Revision 0.0
September 2001
- 23 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC Waveforms for Erase Operation(WE Control)
Address
A21 ~ A0
VIH
VIL
Bank Address
Vaild
Address Vaild
tAS
Bank Address
Erase
Read Status Register
Write Read Register
tWC
tAH
VIH
VIL
F-CE
OE
tCS
tCH
ta(CE)
VIH
VIL
tWP
tWPH
tOEH
ta(OE)
VIH
VIL
WE
tWHRL
tDH
tDS
VIH
VIL
High-Z
SR
Busy
SR
Ready
20H
DOH
FFH
DATA
F-RP
F-WP
tPS
VIH
VIL
tBLH
tDAE
tBLS
VIH
VIL
AC Waveforms for Erase Operation(CE Control)
Address
A21 ~ A0
VIH
VIL
Bank Address
Vaild
Address Vaild
tAS
Bank Address
Erase
Read Status Register
Write Read Register
tWC
tAH
VIH
VIL
F-CE
OE
ta(CE)
VIH
VIL
tCEP
tOEH
ta(OE)
tWS
tWH
VIH
VIL
WE
tWHRL
tDH
tDS
VIH
VIL
High-Z
SR
Busy
SR
Ready
20H
DOH
FFH
DATA
F-RP
F-WP
tPS
VIH
VIL
tBLH
tDAE
tBLS
VIH
VIL
Revision 0.0
September 2001
- 24 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC Waveforms for Word Program Operation with BGO(WE Control)
Change Bank Address
Program in one bank
Read Status Register
Read Array in another bank
Address
A21 ~ A7
VIH
VIL
Bank Address
Vaild
Address Vaild
Address Vaild
Address Vaild
Address Vaild
Address Vaild
VIH
VIL
A6 ~ A0
F-CE
OE
Address Vaild
tAS
Program
tWC
tAH
VIH
VIL
tCS
tCH
ta(CE)
VIH
VIL
tWP
tWPH
tOEH
ta(OE)
VIH
VIL
WE
tWHRL
tDS
VIH
VIL
High-Z
SR
Busy
40H
DIN
DOUT
DOUT
DATA
tDH
AC Waveforms for Word Program Operation with BGO(CE Control)
Change Bank Address
Program in one bank
Read Status Register
Read Array in another bank
Address
A21 ~ A7
VIH
VIL
Bank Address
Vaild
Address Vaild
Address Vaild
Address Vaild
Address Vaild
VIH
VIL
Address Vaild
A6 ~ A0
Address Vaild
tAS
Program
tWC
tAH
VIH
VIL
F-CE
OE
ta(CE)
VIH
VIL
tCEP
tOEH
tWS
tWH
ta(OE)
VIH
VIL
WE
tEHRL
tDS
VIH
VIL
High-Z
SR
Busy
40H
DIN
DOUT
DOUT
DATA
tDH
Revision 0.0
September 2001
- 25 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC Waveforms for Page Program Operatio with BGO(WE Control)
Change Bank Address
Program in one bank
Read Array in another bank
VIH
VIL
Address
A21 ~ A7
Bank Address
Vaild
Address Vaild
Address Vaild
Address Vaild
VIH
VIL
Address Vaild
Address Vaild
A6 ~ A0
F-CE
OE
00H
tAS
Valid
tAH
01H-7EH
7FH
tWC
ta(CE)
VIH
VIL
tCS
tCH
ta(CE)
ta(OE)
VIH
VIL
tGHWL
ta(OE)
tWP
tWPH
tOEH
tOEH
VIH
VIL
WE
tWHRL
tDH
VIH
VIL
High-Z
SR
Busy
41H
DIN
DOU
DIN
DIN
DOUT
DOUT
DATA
tDS
AC Waveforms for Page Program Operatio with BGO(CE Control)
Change Bank Address
Program in one bank
Read Array in another bank
VIH
VIL
Address
A21 ~ A7
Bank Address
Vaild
Address Vaild
Address Vaild
Address Vaild
VIH
VIL
A6 ~ A0
00H
tAS
Valid
tAH
01H-7EH
7FH
tWC
ta(CE)
VIH
VIL
F-CE
OE
tWS
tWH
ta(CE)
ta(OE)
VIH
VIL
tGHEL
ta(OE)
tCEP
tCEPH
tOEH
VIH
VIL
WE
tEHRL
tEHRL
tDH
VIH
VIL
High-Z
SR
Busy
41H
DIN
DOUT
DIN
DIN
DOUT
DOUT
DATA
tDS
Revision 0.0
September 2001
- 26 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC Waveforms for Erase Operation with BGO(WE Control)
Change Bank Address
Program in one bank
Read Status Register
Read Array in another bank
VIH
VIL
Address
A21 ~ A0
Bank Address
Vaild
Address Vaild
Address Vaild
Address Vaild
tWC
tAS
tAH
VIH
VIL
F-CE
OE
tCS
tCH
ta(CE)
VIH
VIL
tWP
tWPH
tOEH
ta(OE)
VIH
VIL
WE
tWHRL
tDS
VIH
VIL
High-Z
SR
Busy
20H
DOH
DOUT
DOUT
DATA
tDH
AC Waveforms for Erase Operation with BGO(CE Control)
Change Bank Address
Read Array in another bank
Program in one bank
Read Status Register
Address
A21 ~ A0
VIH
VIL
Bank Address
Vaild
Address Vaild
Address Vaild
Address Vaild
tWC
tAS
tAH
VIH
VIL
F-CE
OE
ta(CE)
ta(OE)
VIH
VIL
tCEP
tOEH
tWS
tWH
VIH
VIL
WE
tEHRL
tDS
VIH
VIL
High-Z
SR
Busy
20H
DOH
DOUT
DOUT
DATA
tDH
Revision 0.0
September 2001
- 27 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
AC Waveforms for Suspend Operation(WE Control)
Address
A21 ~ A0
VIH
VIL
Bank Address Vaild
tAS
Bank Address Vaild
Read Status Register
tAH
tCH
VIH
VIL
F-CE
OE
ta(CE)
ta(OE)
tCS
VIH
VIL
tOEH
tWP
VIH
VIL
WE
Suspend Time
S.R.6,7=1
SR
Busy
VIH
VIL
High-Z
B0H
DATA
F-RP
F-WP
VIH
VIL
tBLS
tBLH
VIH
VIL
AC Waveforms for Suspend Operation(CE Control)
Address
A21 ~ A0
VIH
VIL
Bank Address Vaild
tAS
Bank Address Vaild
Read Status Register
tAH
VIH
VIL
F-CE
OE
tOEH
ta(CE)
ta(OE)
VIH
VIL
tCEP
tWS
tWH
VIH
VIL
WE
Suspend Time
S.R.6,7=1
SR
Busy
VIH
VIL
High-Z
B0H
DATA
F-RP
F-WP
VIH
VIL
tBLS
tBLH
VIH
VIL
Revision 0.0
September 2001
- 28 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Word Program Flow Chart
Page Program Flow Chart
START
START
Write 41H
n = 0
Write 40H
Write Address,
Data
Write Address n,
DATA n
n = 0
Status Register
Read
No
No
n=7FH?
Yes
No
No
Write
SR.7=1?
Yes
BOH?
Yes
Status Register
Read
Full Status Check
If Desired
Suspend Loop
Write D0H
No
Write
SR.7=1?
Yes
Word Program
Completed
BOH?
Yes
Yes
Full Status Check
If Desired
Suspend Loop
Write D0H
Page Program
Completed
Yes
Block Erase Flow Chart
START
Write 20H
Status Register Check Flow Chart
START
Write D0H
Block Address
YES
Command
Sequence Error
SR.4,5=1?
Status Register
Read
No
No
Block Erase
No
No
Write
BOH?
SR.5=0?
Error
SR.7=1?
YES
Yes
Yes
No
Program Error
Full Status Check
SR.4=0?
(Page Program)
If Desired
Suspend Loop
Write D0H
YES
Erase
Completed
No
Block Erase Error
SR.3=0?
Yes
(Block Fail)
YES
Pass
(Block Erase, Program)
Revision 0.0
September 2001
- 29 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Single Data Load to Page Buffer
Flow Chart
Suspend / Resume Flow Chart
START
START
Suspend
Write B0H
Write 74H
Status Register
Read
Write Address,
Data
No
No
S.R.7=1?
Yes
Load
No
Finished?
Erase/Program
Finished
S.R.6=1?
Yes
Single Data Load
To Page Buffer
Completed
Write FFH
Read Array
Data
No
Read
Finished?
Yes
Resume
Write D0H
Page Buffer to Flash Flow Chart
START
Operation
Restart
Write 0H
Write D0H
Page Address
Clear Page Buffer Flow Chart
Status Register
Read
START
No
No
Write
SR.7=1?
BOH?
Write 55H
Write D0H
Yes
Yes
Full Status Check
If Desired
Suspend Loop
Write D0H
Page Buffer
To Flash
Completed
Clear Page Buffer
Completed
Yes
Revision 0.0
September 2001
- 30 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Operation Status (WP=VIH)
F3H
FFH
Read/Standby State
(Sequential Page Read Mode)
Read/Standby State
(Read Array Mode)
Read
Status Register
50H
Clear
70H
70H
Status Register
90H
Read
FFH (Read Array)
F3H (Seq. Page)
Device Identifier
90H
Seq. Page Read
Change Bank
FFH (Read Array)
F3H (Seq. Page)
Read Array
Address
Read Array
(From the other Bank)
D0H
WD D0H
55H
74H
F1H
0EH
41H
40H
20H
A7H
Setup State
Clear Page Bufer
Setup
Single Data Load
to Page Bufer Setup
Flash Page Burrer
Setup
Page Buffer to Flash
Setup
Page Program
Setup
Word Program
Setup
Block Erase
Setup
Erase All Unlocked
Blocks Setup
Wdi
D0H I=0-127
Other
WD
D0H
D0H
Other
Internal State
B0H
D0H
B0H
D0H
Program &
Verift
Erase &
Verift
Ready
Read
Status Register
Read
Status Register
Change Bank
Address
Read
Suspend
State
Status Register
70H
Read State
with BGO
FFH (Read Array)
F3H (Seq. Page)
Change Bank
Address
Read Array
(From the other Bank)
Read Array
Seq. Page Read
Revision 0.0
September 2001
- 31 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
Operation Status (WP=VIL)
F3H
Seq. Page Read
FFH
Read/Standby State
(Sequential Page Read Mode)
Read Array
(From the other Bank)
Read/Standby State
(Read Array Mode)
Read
Change Bank
Address
Status Register
70H
70H
BA
*
BA
*
90H
ACH
60H
Single Data Load
Single Data Load
Single Data Load
Single Data Load
Read
FFH (Read Array)
F3H (Seq. Page)
to Page Bufer Setup
to Page Bufer Setup
to Page Bufer Setup
to Page Bufer Setup
Device Identifier
90H
7BH
FFH (Read Array)
F3H (Seq. Page)
Read Array
Single Data Load
Other
to Page Bufer Setup
50H
D0H
WD D0H
Clear
Status Register
55H
74H
F1H
0EH
41H
40H
20H
A7H
Setup State
Clear Page Bufer
Setup
Single Data Load
Flash Page Burrer
Setup
Page Buffer to Flash
Setup
Page Program
Setup
Word Program
Setup
Block Erase
Setup
Erase All Unlocked
Blocks Setup
to Page Bufer Setup
Wdi
D0H i=0-127
WD
D0H
D0H
Internal State
B0H
D0H
B0H
D0H
Program &
Verift
Erase &
Verift
Ready
Read
Status Register
Read
Status Register
Change Bank
Address
Read
Suspend
State
Status Register
70H
Read State
with BGO
FFH (Read Array)
F3H (Seq. Page)
Change Bank
Address
Read Array
(From the other Bank)
Read Array
Seq. Page Read
Revision 0.0
September 2001
- 32 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
SRAM Part
Clk gen.
Precharge circuit.
Vcc
Vss
Row
Addresses
Memory array
1024 rows
512´ 16 columns
Row
select
I/O Circuit
Column select
Data
cont
I/O1~I/O8
Data
cont
I/O9~I/O16
Data
cont
Column Addresses
CS1
CS2
OE
WE
UB
Control Logic
LB
FUNCTIONAL BLOCK DIAGRAM (8Mbit SRAM)
FUNCTIONAL DESCRIPTION
CS1
H
CS2
X1)
L
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
Deselected
X1)
X1)
L
Deselected
X1)
H
Deselected
X1)
L
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
L
H
H
H
Active
L
H
L
H
H
Active
L
H
L
H
H
L
High-Z
Dout
Active
L
H
L
H
L
L
Dout
Active
X1)
X1)
X1)
L
H
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
H
L
H
L
High-Z
Din
Active
L
H
L
L
L
Din
Active
1. X means don¢t care. (Must be low or high state)
Revision 0.0
September 2001
- 33 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
-0.5 to VCC+0.3V(Max. 3.6V)
-0.3 to 3.6
Unit
V
V
PD
1.0
W
Storage temperature
TSTG
-65 to 150
°C
°C
Operating Temperature
TA
-40 to 85
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions over 1 seconds may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
2.7
0
Typ
Max
3.3
0
Unit
V
Supply voltage
Ground
3.0
Vss
0
-
V
Vcc+0.32)
0.6
Input high voltage
Input low voltage
Note:
VIH
2.2
V
-0.33)
VIL
-
V
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: VCC+2.0V in case of pulse width £20ns.
3. Undershoot: -2.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTIC
Typ1)
Item
Symbol
Test Conditions
Min
Max Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-
1
1
mA
mA
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or
LB=UB=VIH, VIO=Vss to Vcc
Output leakage current
ILO
-1
-
-
-
Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V,
LB£0.2V or/and UB£0.2V, CS2³ Vcc-0.2V, VIN£0.2V or
VIN³ VCC-0.2V
ICC1
ICC2
-
2
mA
mA
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL,
CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH
55ns
-
28
Output low voltage
Output high voltage
VOL
VOH
IOL = 2.1mA
-
-
-
0.4
-
V
V
IOH = -1.0mA
2.4
Other input =0~Vcc
Standby Current(CMOS)
ISB1
1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or
2) 0V£CS2£0.2V(CS2 controlled)
-
0.5
15
mA
1. Typical value are measured at VCC=3.0V, TA=25°C and not 100% tested.
Revision 0.0
September 2001
- 34 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
3)
VTM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
2)
R1
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
1)
2)
CL
R2
1. Including scope and jig capacitance
2. R1=3070W, R2=3150W
3. VTM =2.8V
AC CHARACTERISTICS
55ns
Parameter List
Symbol
Units
Min
55
-
Max
Read Cycle Time
tRC
tAA
-
55
55
25
55
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
tCO
tOE
-
-
tBA
-
Chip Select to Low-Z Output
Read
tLZ
10
10
5
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tBLZ
tOLZ
tHZ
-
-
0
20
20
20
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
10
55
45
0
-
Chip Select to End of Write
Address Set-up Time
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
40
0
-
-
Write
Write Pulse Width
-
Write Recovery Time
-
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
0
20
-
25
0
-
tOW
5
-
DATA RETENTION CHARACTERISTICS
Typ2)
Item
Symbol
Test Condition
Min
Max
Unit
V
CS1³ Vcc-0.2V1)
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
VDR
1.5
-
-
0.5
-
3.3
Vcc=1.5V, CS1³ Vcc-0.2V1)
IDR
6
-
mA
tSDR
0
See data retention waveform
ns
tRDR
tRC
-
-
1. 1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or
2) 0£CS2£0.2V(CS2 controlled)
2. Typical value are measured at TA=25°C and not 100% tested.
Revision 0.0
September 2001
- 35 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
SRAM TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 0.0
September 2001
- 36 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
SRAM TIMING DIAGRAMS
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS1
tCW(2)
tWR(4)
CS2
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tCW(2)
tAW
tAS(3)
tWR(4)
CS1
CS2
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
Revision 0.0
September 2001
- 37 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS1
tCW(2)
tAW
tWR(4)
CS2
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CS1³ VCC - 0.2V
CS1
Vss
CS2 controlled
Data Retention Mode
VCC
2.7V
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
Vss
Revision 0.0
September 2001
- 38 -
Advance Information
K5C6481NT(B)M
MCP MEMORY
PACKAGE DIMENSION
81-Ball Tape Ball Grid Array Package (measured in millimeters)
Top View
Bottom View
10.8.00±0.10
A
0.80x11=8.80
10.80±0.10
(Datum A)
B
12 11
10
9
8
7
6
5
4
3
2
1
0.80
A
B
C
D
E
F
#A1
(Datum B)
G
H
J
K
L
M
4.40
81-
Æ 0.45±0.05
Æ
0.20
M A B
Side View
0.45±0.05
0.08MAX
10.40±0.10
Revision 0.0
September 2001
- 39 -
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