K6E1008C1B-JC20 [SAMSUNG]
Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32;
| 型号： | K6E1008C1B-JC20 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
K6E1008C1B-C
CMOS SRAM
Document Title
128Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out.
Revision History
Rev.No.
Rev. 0.0
Rev. 1.0
History
Draft Data
Remark
Initial release with Design Target.
Feb. 1st 1997
Jun. 1st 1997
Design Target
Preliminary
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Rev. 2.0
Release to Final Data Sheet.
Feb. 6th 1998
Final
2.1. Delete Preliminary.
2.2. Delete 17ns, L-version and Industrial Temperature Part.
2.3. Delete VOH1=3.95V.
2.4. Delete Data Retention Characteristics and Wave form.
2.5. Relex operating current.
Speed
15ns
17ns
20ns
Previous
130mA
120mA
110mA
Now
125mA
-
123mA
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev 2.0
February 1998
- 1 -
PRELIMINARY
K6E1008C1B-C
CMOS SRAM
128K x 8 Bit High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 15, 20ns(Max.)
• Low Power Dissipation
The K6E1008C1B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
K6E1008C1B uses 8 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG¢s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
Standby (TTL)
: 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6E1008C1B-15 : 125mA(Max.)
K6E1008C1B-20 : 123mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
high-density
high-speed
system
applications.
The
K6E1008C1B is packaged in a 400 and 300 mil 32-pin plastic
SOJ.
- No Clock or Refresh required
• Three State Outputs
• Standard Pin Configuration
K6E1008C1B-J : 32-SOJ-400
K6E1008C1B-S : 32-SOJ-300
PIN CONFIGURATION(Top View)
N.C
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
32 Vcc
31 A16
30 CS2
29 WE
28 A15
27 A14
26 A13
25 A12
24 OE
23 A11
22 CS1
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
SOJ
A0
A1
A2
A3
A8 10
A9 11
A10 12
I/O1 13
I/O2 14
I/O3 15
Vss 16
Memory Array
512 Rows
256x8 Columns
A4
A5
A6
A7
A8
Data
Cont.
I/O Circuit
Column Select
I/O1 ~ I/O8
CLK
Gen.
PIN FUNCTION
A9 A10 A11 A12 A13 A14 A15 A16
Pin Name
A0 - A16
WE
Pin Function
CS2
CS1
WE
Address Inputs
Write Enable
Chip Selects
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
CS1, CS2
OE
OE
I/O1 ~ I/O8
VCC
VSS
N.C
No Connection
Rev 2.0
February 1998
- 2 -
PRELIMINARY
K6E1008C1B-C
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
-0.5 to 7.0
-0.5 to 7.0
1.0
Unit
V
V
PD
W
Storage Temperature
TSTG
-65 to 150
0 to 70
°C
°C
Operating Temperature
TA
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter
Supply Voltage
Symbol
Min
4.5
0
Typ
Max
Unit
V
VCC
5.0
5.5
0
Ground
VSS
0
-
V
V
Input High Voltage
Input Low Voltage
VIH
2.2
-0.5*
VCC+0.5**
0.8
V
VIL
-
*
VIL(Min) = -2.0V a.c(Pulse Width £ 10ns) for I £ 20mA.
** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 10ns) for I £ 20mA
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
-2
Max
2
Unit
mA
Input Leakage
ILI
VIN = VSS to VCC
Output Leakage
Current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL,
VOUT = VSS to VCC
-2
2
mA
Operating Current
ICC
Min. Cycle, 100% Duty CS1=VIL, CS2=VIH,
VIN=VIH or VIL, IOUT=0mA
15ns
20ns
-
-
-
-
125
123
20
mA
mA
Standby Current
ISB
Min. Cycle, CS1=VIH or CS2=VIL
ISB1
f=0MHz, CS1³ VCC-0.2V or CS2£0.2V,
VIN³ VCC-0.2V or VIN£0.2V
5
Output Low Volt-
Output High Volt-
VOL
VOH
IOL=8mA
-
0.4
-
V
V
IOH=-4mA
2.4
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
Test Conditions
VI/O=0V
MIN
Max
8
Unit
Input/Output Capacitance
Input Capacitance
CI/O
-
-
pF
pF
CIN
VIN=0V
6
* Capacitance is sampled and not 100% tested.
Rev 2.0
February 1998
- 3 -
PRELIMINARY
K6E1008C1B-C
CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
+5.0V
480W
480W
DOUT
DOUT
255W
255W
30pF*
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
K6E1008C1B-15
K6E1008C1B-20
Unit
Symbol
Min
15
-
Max
Min
20
-
Max
Read Cycle Time
tRC
tAA
-
15
15
8
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
20
20
10
-
Chip Select to Output
tCO*
tOE
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
-
-
tLZ*
tOLZ
tHZ*
tOHZ
tOH
tPU
3
-
3
0
-
0
-
0
6
0
8
0
6
0
8
3
-
3
-
0
-
0
-
tPD
-
15
-
20
* tCO=tCO1, tCO2 / tLZ=tLZ1, tLZ2 / tHZ=tHZ1, tHZ2
Rev 2.0
February 1998
- 4 -
PRELIMINARY
K6E1008C1B-C
CMOS SRAM
WRITE CYCLE*
Parameter
K6E1008C1B-15
K6E1008C1B-20
Symbol
Unit
Min
15
10
0
Max
Min
20
12
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
8
-
-
-
-
-
Chip Select to End of Write
Address Set-up Time
-
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR*
tWHZ
tDW
tDH
10
10
15
0
12
12
20
0
-
-
-
-
Write to Output High-Z
0
0
10
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
7
9
0
0
-
tOW
3
3
-
* tWR = tWR1, tWR2
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Valid Data
Data Out
Previous Valid Data
Rev 2.0
February 1998
- 5 -
PRELIMINARY
K6E1008C1B-C
CMOS SRAM
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
CS1
tCO
CS2
tOHZ
tOE
OE
tOLZ
tOH
tLZ(4,5)
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS1=VIL and CS2=VIH.
7. Address valid prior to coincident with CS1 transition low and CS2 transition high.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
OE
tWR(5)
tAW
tCW(3)
CS1
CS2
tAS(4)
WE
tWP(2)
tDW
tDH
High-Z
Data in
Valid Data
tOHZ(6)
High-Z(8)
Data out
Rev 2.0
February 1998
- 6 -
PRELIMINARY
K6E1008C1B-C
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
CS1
tWR(5)
tAW
tCW(3)
CS2
tAS(4)
tWP1(2)
WE
tDH
tDW
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS1
tAS(4)
CS2
tWP(2)
WE
tDH
tDW
High-Z
High-Z
High-Z
Data in
Data out
Valid Data
tLZ
tWHZ(6)
High-Z(8)
Rev 2.0
February 1998
- 7 -
PRELIMINARY
K6E1008C1B-C
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(4) (CS2 = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS1
tAS(4)
CS2
tWP(2)
WE
tDH
tDW
Data in
Data out
Valid Data
tLZ
tWHZ(6)
High-Z
High-Z
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition CS1 going low,
CS2 going high and WE going low ; A write ends at the earliest transition CS1 going high or CS2 going low or WE going high.
tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS1 going low or CS2 going high to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high. tWR2
applied in case a write ends as CS2 going low.
6. If OE, CS1, CS2 and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS1 goes low and CS2 goes high simultaneously with WE going or after WE going low, the outputs remain high impedance
state.
9. Dout is the read data of the new address.
10.When CS1 is low and CS2 is high : I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
CS1
H
CS2
X
WE
X
OE
X*
X
Mode
Not Select
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
High-Z
DOUT
Supply Current
ISB, ISB1
ISB, ISB1
ICC
X
L
X
L
H
H
H
L
H
H
L
ICC
L
H
L
X
Write
DIN
ICC
* X means Don¢t Care.
Rev 2.0
February 1998
- 8 -
PRELIMINARY
K6E1008C1B-C
CMOS SRAM
Units:millimeters/Inches
PACKAGE DIMENSIONS
32-SOJ-300
#32
#17
8.64 ±0.12
0.340 ±0.005
6.86 ±0.25
0.270 ±0.010
+0.10
-0.05
0.20
0.008 +0.004
#1
#16
-0.002
0.69
MIN
0.027
21.36
0.841
MAX
20.95 ±0.12
0.825 ±0.005
1.14
0.045
(
)
0.10
0.004
3.76
0.148
MAX
MAX
1.32
0.052
(
)
+0.10
-0.05
+0.10
-0.05
+0.004
-0.002
0.71
0.43
0.95
0.0375
1.27
0.050
(
)
0.017 +0.004
0.028
-0.002
32-SOJ-400
#32
#17
9.40 ±0.25
0.370 ±0.010
11.18 ±0.12
0.440 ±0.005
+0.10
-0.05
0.20
0.008 +0.004
#1
#16
-0.002
0.69
0.027
21.36
MAX
0.841
MIN
20.95 ±0.12
0.825 ±0.005
1.30
(
(
)
)
0.051
0.10
0.004
3.76
0.148
MAX
MAX
1.30
0.051
+0.10
+0.10
0.71
0.43
-0.05
-0.05
1.27
0.050
0.95
0.0375
(
)
0.028 +0.004
+0.004
-0.002
0.017
-0.002
Rev 2.0
February 1998
- 9 -
相关型号：
K6F1008R2A-FI10
Standard SRAM, 128KX8, 100ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG
©2020 ICPDF网 联系我们和版权申明