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K6F2008U2E-EF700 [SAMSUNG]

Standard SRAM, 256KX8, 70ns, CMOS, PBGA36, 6 X 7 MM, 0.75 MM PITCH, TBGA-36/48;
K6F2008U2E-EF700
型号： K6F2008U2E-EF700
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 256KX8, 70ns, CMOS, PBGA36, 6 X 7 MM, 0.75 MM PITCH, TBGA-36/48

静态存储器 内存集成电路
文件： 总10页 (文件大小：175K)
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K6F2008U2E Family  
CMOS SRAM  
Document Title  
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM  
Revision History  
Revision No. History  
Draft Date  
February 28, 2001  
Remark  
0.0  
1.0  
2.0  
Initial Draft  
Finalize  
Preliminary  
September 27, 2001 Final  
April 30, 2002 Final  
Revise  
- Added 48(36)-TBGA-6.00x7.00 products.  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.  
Revision 2.0  
1
April 2002  
K6F2008U2E Family  
CMOS SRAM  
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
• Process Technology: Full CMOS  
• Organization: 256Kx8  
The K6F2008U2E families are fabricated by SAMSUNG¢s  
advanced Full CMOS process technology. The families support  
various operating temperature ranges and have various pack-  
age types for user flexibility of system design. The families also  
supports low data retention voltage for battery back-up opera-  
tion with low data retention current.  
• Power Supply Voltage: 2.7~3.3V  
• Low Data Retention Voltage: 1.5V(Min)  
• Three State Outputs  
• Package Type: 32-TSOP1-0813.4F, 48(36)-TBGA-6.00x7.00  
PRODUCT FAMILY  
Power Dissipation  
Product Family Operating Temperature Vcc Range Speed(ns)  
PKG Type  
Standby  
Operating  
(ISB1, Typ.) (ICC1, Max)  
32-TSOP1-0813.4F  
48(36)-TBGA-6.00x7.00  
551)/70ns  
0.5mA2)  
K6F2008U2E-F  
Industrial(-40~85°C)  
2.7~3.3V  
2mA  
1. The parameter is measured with 30pF test load.  
2. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested.  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
Clk gen.  
Precharge circuit.  
A11  
A9  
A8  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
OE  
A10  
CS1  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
VSS  
I/O3  
I/O2  
I/O1  
A0  
A13  
WE  
CS2  
A15  
VCC  
A17  
A16  
A14  
A12  
A7  
Memory array  
1024 rows  
256x8 columns  
32-sTSOP  
Row  
select  
9
Type1-Forward  
10  
11  
12  
13  
14  
15  
16  
A6  
A5  
A4  
A1  
A2  
A3  
I/O Circuit  
I/O  
I/O  
1
8
Data  
cont  
1
2
3
4
5
6
Column select  
A
B
C
D
E
F
A
0
A
1
CS  
2
A
3
A
6
A8  
Data  
cont  
I/O  
5
A2  
WE  
DNU  
A4  
A7  
I/O1  
I/O  
6
A5  
I/O2  
Address  
VSS  
VCC  
48(36)-TBGA  
CS1  
VCC  
VSS  
Control  
logic  
CS2  
WE  
OE  
I/O  
7
DNU  
A17  
I/O3  
G
H
I/O  
8
OE  
CS  
1
A
16  
A
15  
I/O4  
Name  
Function  
Name  
Function  
A9  
A10  
A11  
A12  
A13  
A14  
CS1, CS2 Chip Select Input  
I/O1~I/O8 Data Inputs/Outputs  
OE  
Output Enable  
Vcc  
Vss  
Power  
WE  
Write Enable Input  
Ground  
A0~A17 Address Inputs  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
Revision 2.0  
April 2002  
2
K6F2008U2E Family  
PRODUCT LIST  
Part Name  
CMOS SRAM  
Industrial Temperature Products(-40~85°C)  
Function  
K6F2008U2E-YF55  
K6F2008U2E-YF70  
32-sTSOP1-F, 55ns, 3.0V, LL  
32-sTSOP1-F, 70ns, 3.0V, LL  
K6F2008U2E-EF55  
K6F2008U2E-EF70  
48(36)-TBGA, 55ns, 3.0V, LL  
48(36)-TBGA, 70ns, 3.0V, LL  
FUNCTIONAL DESCRIPTION  
CS1  
CS2  
OE  
WE  
I/O  
Mode  
Deselected  
Deselected  
Output Disable  
Read  
Power  
Standby  
Standby  
Active  
X1)  
L
X1)  
X1)  
H
High-Z  
High-Z  
High-Z  
Dout  
X1)  
L
X1)  
H
X1)  
H
H
H
H
L
L
L
H
L
Active  
X1)  
Din  
Write  
Active  
1. X means don¢t care (Must be high or low states)  
ABSOLUTE MAXIMUM RATINGS1)  
Item  
Voltage on any pin relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
Symbol  
VIN, VOUT  
VCC  
Ratings  
-0.2 to VCC+0.3V  
-0.2 to 3.6V  
1.0  
Unit  
V
V
PD  
W
°C  
°C  
Storage temperature  
TSTG  
-65 to 150  
-40 to 85  
Operating Temperature  
TA  
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be  
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
Revision 2.0  
3
April 2002  
K6F2008U2E Family  
CMOS SRAM  
RECOMMENDED DC OPERATING CONDITIONS1)  
Item  
Symbol  
Vcc  
Min  
2.7  
0
Typ  
Max  
3.3  
0
Unit  
V
Supply voltage  
Ground  
3.0  
Vss  
0
-
V
Vcc+0.22)  
0.6  
Input high voltage  
Input low voltage  
Note:  
VIH  
2.2  
V
-0.23)  
VIL  
-
1. Industrial Product: TA=-40 to 85°C, unless otherwise specified  
2. Overshoot: Vcc+2.0V in case of pulse width£20ns  
3. Undershoot: -2.0V in case of pulse width£20ns  
4. Overshoot and undershoot are sampled, not 100% tested.  
CAPACITANCE1) (f=1MHz, TA=25°C)  
Item  
Input capacitance  
Symbol  
CIN  
Test Condition  
VIN=0V  
Min  
Max  
8
Unit  
-
-
pF  
pF  
Input/Output capacitance  
CIO  
VIO=0V  
10  
1. Capacitance is sampled, not 100% tested.  
DC AND OPERATING CHARACTERISTICS  
Typ1)  
Item  
Symbol  
ILI  
Test Conditions  
Min  
-1  
Max Unit  
Input leakage current  
Output leakage current  
VIN=Vss to Vcc  
-
-
1
1
mA  
mA  
ILO  
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc  
-1  
Cycle time=1ms, 100% duty, IIO=0mA, CS1£0.2V,  
CS2³ VCC-0.2V, VIN£0.2V or VIN³ VCC-0.2V  
ICC1  
ICC2  
-
-
2
mA  
Average operating current  
70ns  
55ns  
-
-
-
-
-
-
15  
20  
0.4  
-
mA  
mA  
V
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL,  
CS2=VIH, VIN=VIL or VIH  
Output low voltage  
Output high voltage  
VOL  
VOH  
IOL=2.1mA  
-
IOH =-1.0mA  
2.4  
V
Other inputs=Vss to Vcc  
Standby Current(CMOS)  
ISB1  
1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or  
2) 0V£CS2£0.2V CS2 controlled)  
-
0.5  
10  
mA  
1. Typical value are measured at VCC=3.0V, TA=25°C, and not 100% tested.  
Revision 2.0  
April 2002  
4
K6F2008U2E Family  
CMOS SRAM  
3)  
AC OPERATING CONDITIONS  
VTM  
TEST CONDITIONS(Test Load and Test Input/Output Reference)  
Input pulse level: 0.4 to 2.2V  
Input rising and falling time: 5ns  
Input and output reference voltage: 1.5V  
Output load (See right): CL=100pF+1TTL  
CL=30pF+1TTL  
2)  
3)  
R1  
R2  
1)  
CL  
1. Including scope and jig capacitance  
2. R1=3070W, R2=3150W  
3. VTM =2.8V  
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product: TA=-40 to 85°C)  
Speed Bins  
55ns1)  
Parameter List  
Symbol  
Units  
70ns  
Min  
55  
-
Max  
Min  
70  
-
Max  
Read Cycle Time  
tRC  
tAA  
-
55  
55  
25  
-
-
70  
70  
35  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
tLZ  
-
-
Output Enable to Valid Output  
Chip Select to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Write Cycle Time  
-
-
Read  
10  
5
10  
5
tOLZ  
tHZ  
-
-
0
20  
20  
-
0
25  
25  
-
tOHZ  
tOH  
tWC  
tCW  
tAS  
0
0
10  
55  
45  
0
10  
70  
60  
0
-
-
Chip Select to End of Write  
Address Set-up Time  
-
-
-
-
Address Valid to End of Write  
Write Pulse Width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
tOW  
45  
40  
0
-
60  
50  
0
-
-
-
Write  
Write Recovery Time  
-
-
Write to Output High-Z  
0
20  
-
0
20  
-
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Output Low-Z  
25  
0
30  
0
-
-
5
-
5
-
1. The parameter is measured with 30pF test load.  
DATA RETENTION CHARACTERISTICS  
Typ2)  
Item  
Vcc for data retention  
Data retention current  
Data retention set-up time  
Recovery time  
Symbol  
VDR  
Test Condition  
CS1³ Vcc-0.2V1)  
Min  
Max  
Unit  
V
1.5  
-
-
0.5  
-
3.3  
Vcc=1.5V, CS1³ Vcc-0.2V1)  
2
-
IDR  
mA  
tSDR  
0
See data retention waveform  
ns  
tRDR  
tRC  
-
-
1. 1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or  
2) 0£CS2£0.2V(CS2 controlled).  
2. Typical value are measured at TA=25°C and not 100% tested.  
Revision 2.0  
April 2002  
5
K6F2008U2E Family  
CMOS SRAM  
TIMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)  
tRC  
Address  
tAA  
tOH  
Data Valid  
Data Out  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tOH  
tAA  
tCO1  
CS1  
tHZ(1,2)  
CS2  
tCO2  
tOE  
OE  
tOHZ  
tOLZ  
tLZ  
High-Z  
Data out  
Data Valid  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
Revision 2.0  
April 2002  
6
K6F2008U2E Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
Address  
tWR(4)  
tCW(2)  
CS1  
tAW  
CS2  
tCW(2)  
tWP(1)  
WE  
tAS(3)  
tDW  
tDH  
Data Valid  
Data in  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)  
tWC  
Address  
CS1  
tCW(2)  
tAS(3)  
tWR(4)  
tAW  
CS2  
tWP(1)  
WE  
tDW  
tDH  
Data in  
Data out  
Data Valid  
High-Z  
High-Z  
Revision 2.0  
April 2002  
7
K6F2008U2E Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)  
tWC  
Address  
CS1  
tAS(3)  
tCW(2)  
tWR(4)  
tAW  
CS2  
tWP(2)  
tWP(1)  
WE  
tDH  
tDW  
Data in  
Data Valid  
High-Z  
High-Z  
Data out  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,  
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,  
tWP is measured from the begining of write to the end of write.  
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)  
applied in case a write ends as CS2 going to low.  
DATA RETENTION WAVE FORM  
CS1 controlled  
Data Retention Mode  
tSDR  
tRDR  
VCC  
2.7V  
2.2V  
VDR  
CS1³ VCC - 0.2V  
CS1  
GND  
CS2 controlled  
Data Retention Mode  
VCC  
2.7V  
CS2  
tSDR  
tRDR  
VDR  
CS2£0.2V  
0.4V  
GND  
Revision 2.0  
April 2002  
8
K6F2008U2E Family  
CMOS SRAM  
PACKAGE DIMENSIONS  
Units: millimeters(inches)  
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)  
13.40 ±0.20  
0.528 ±0.008  
+0.10  
-0.05  
+0.004  
-0.002  
0.20  
0.008  
#1  
#32  
0.25  
0.010  
(
)
0.50  
0.0197  
#16  
#17  
1.00 ±0.10  
0.039 ±0.004  
0.25  
0.010  
0.05  
0.002  
TYP  
MIN  
11.80 ±0.10  
0.465 ±0.004  
+0.10  
-0.05  
+0.004  
-0.002  
0.15  
1.20  
MAX  
0.047  
0.006  
0~8°  
0.50  
0.020  
0.45~0.75  
0.018~0.030  
(
)
Revision 2.0  
April 2002  
9
K6F2008U2E Family  
CMOS SRAM  
PACKAGE DIMENSIONS  
Units: millimeters  
48(36) TAPE BALL GRID ARRAY(0.75mm ball pitch)  
Top View  
B
Bottom View  
B
B1  
6
5
4
3
2
1
A
B
#A1  
C
D
E
F
G
H
B/2  
Detail A  
A
Side View  
D
Y
C
Min  
Typ  
0.75  
6.00  
3.75  
7.00  
5.25  
0.45  
0.90  
0.55  
0.35  
-
Max  
-
A
B
-
5.90  
-
Notes.  
6.10  
-
1. Bump counts: 48(8 row x 6 column)  
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)  
3. All tolerence are +/-0.050 unless  
otherwise specified.  
B1  
C
6.90  
-
7.10  
-
C1  
D
4. Typ: Typical  
0.40  
0.80  
-
0.50  
1.00  
-
5. Y is coplanarity: 0.08(Max)  
E
E1  
E2  
Y
0.30  
-
0.40  
0.08  
Revision 2.0  
April 2002  
10  

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