K6F2016R4A-ZI700 [SAMSUNG]

Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 0.75 MM PITCH, CSP-48;


型号：	K6F2016R4A-ZI700
厂家：	SAMSUNG
描述：	Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 0.75 MM PITCH, CSP-48 静态存储器
文件：	总9页 (文件大小：161K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Advance

K6F2016R4A Family

CMOS SRAM

Document Title

128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No. History

0.0 Initial Draft

Draft Date

Remark

August 6, 1998

Advance

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications and products. SAMSUNG Electronics will answer to your requests and questions about device. If you

have any questions, please contact the SAMSUNG branch office.

Revision 0.0

August 1998

- 1 -

Advance

K6F2016R4A Family

CMOS SRAM

128K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology : Full CMOS

· Organization : 128K x16 bit

· Power Supply Voltage : 1.7 ~ 2.2V

· Low Data Retention Voltage : 1.0V(Min)

· Three state output status and TTL Compatible

· Package Type : 48 - CSP with 0.75mm ball pitch

The K6F2016R4A families are fabricated by SAMSUNG¢s

advanced full CMOS process technology. The families support

industrial temperature range and 48 ball Chip Scale Package

for user flexibility of system design. The families also support

low data retention voltage for battery back-up operation with

low data retention current.

PRODUCT FAMILY

Power Dissipation

Product Family

Operating Temperature

Vcc Range

Speed(ns)

PKG Type

Standby

(ISB1, Typ.)

Operating

(ICC1, Max)

70¹⁾/100

K6F2016R4A-I

Industrial(-40 ~ 85°C)

1.7 ~ 2.2V

0.5mA

3mA

48-CSP

1. The parameter is measured with 30pF test load.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Precharge circuit.

N.C

I/O1

I/O3

Vcc

Vss

I/O7

I/O8

N.C

Vcc

Vss

I/O9

Row

Addresses

Memory array

1024 rows

128 ´ 16 columns

Row

select

I/O10

Vss

I/O11

I/O12

I/O13

I/O14

N.C

I/O2

I/O4

I/O5

I/O6

A11

N.C

A14

A12

Vcc

I/O15

I/O16

N.C

A16

A15

A13

A10

Data

cont

I/O Circuit

Column select

I/O1~I/O8

Data

cont

I/O9~I/O16

Data

cont

Column Addresses

48-ball CSP - Top View (Ball Down)

Control Logic

Name

Function

Name

Vcc

Vss

Function

Power

Chip Select Input

Output Enable Input

Write Enable Input

Address Inputs

Ground

Upper Byte(I/O9~16)

Lower Byte(I/O1~8)

No Connection

A0~A16

I/O1~I/O16 Data Inputs/Outputs

N.C.

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 0.0

August 1998

- 2 -

Advance

K6F2016R4A Family

CMOS SRAM

PRODUCT LIST

Industrial Temperature Product (-40~85°C)

Function

Part Name

K6F2016R4A-ZI70

K6F2016R4A-ZI10

48-CSP with 48 ball, 70ns, 1.8//2.0V

48-CSP with 48 ball, 100ns, 1.8/2.0V

FUNCTIONAL DESCRIPTION

X¹⁾

I/O1~8

High-Z

Dout

I/O9~16

High-Z

Dout

Mode

Power

Standby

Active

Deselected

X¹⁾

Output Disabled

Lower Byte Read

Upper Byte Read

Word Read

X¹⁾

High-Z

Dout

X¹⁾

Din

High-Z

Din

Lower Byte Write

Upper Byte Write

Word Write

High-Z

Din

1. X means don¢t care. (Must be low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

Symbol

Ratings

-0.2 to 3.0V

-0.2 to 3.6V

1.0

Unit

VIN,VOUT

VCC

Storage temperature

TSTG

-55 to 150

-40 to 85

°C

Operating Temperature

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 0.0

August 1998

- 3 -

Advance

K6F2016R4A Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Vcc

Min

1.7

Typ

Max

2.2

Unit

Supply voltage

Ground

1.8/2.0

Vss

Vcc+0.2²⁾

0.4

Input high voltage

Input low voltage

VIH

1.4

-0.2³⁾

VIL

Note :

1. Industrial Product : TA=-40 to 85°C, otherwise specified

2.Overshoot : Vcc + 1.0 V in case of pulse width £ 20ns

3.Undershoot : -1.0 V in case of pulse width £ 20ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

Min

Max

Unit

VIN=0V

VIO=0V

Input/Output capacitance

CIO

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Symbol

ILI

Item

Test Conditions

Min Typ Max Unit

Input leakage current

Output leakage current

Operating power supply current

VIN=Vss to Vcc

-1

ILO

CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS=VIL, VIN=VIH or VIL

-1

ICC

ICC1

ICC2

VOL

VOH

ISB

Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V, VIN£0.2V or VIN³ VCC-0.2V

Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIH or VIL

IOL = 0.1mA

Average operating current

25 mA

Output low voltage

1.6

0.2

Output high voltage

Standby Current(TTL)

Standby Current (CMOS)

IOL = -0.1mA

CS=VIH or LB=UB=VIH, Other inputs=VIH or VIL

CS³ Vcc-0.2V or LB=UB³ Vcc-0.2V, CS£0.2V, Other inputs=0~Vcc

0.3 mA

3¹⁾

ISB1

0.5

1. Super low power product=1mA with special handling.

Revision 0.0

August 1998

- 4 -

Advance

K6F2016R4A Family

CMOS SRAM

AC OPERATING CONDITIONS

VTM

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level : 0.2 to Vcc-0.2V

Input rising and falling time : 5ns

Input and output reference voltage : 0.9V

Output load (See right) :CL= 100pF+1TTL

CL=30pF+1TTL

1. Including scope and jig capacitance

2. R1=3070W, R2=3150W

3. VTM =1.8V

AC CHARACTERISTICS(TA=-40 to 85°C, Vcc=1.7~2.2V )

Speed Bins

Parameter List

Symbol

Units

70ns

100ns

Min

Max

Min

100

Max

Read cycle time

tRC

tAA

Address access time

100

Chip select to output

tCO

tOE

100

Output enable to valid output

UB, LB Access Time

tBA

100

Chip select to low-Z output

UB, LB enable to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

UB, LB disable to high-Z output

Output disable to high-Z output

Output hold from address change

Write cycle time

tLZ

Read

tBLZ

tOLZ

tHZ

tBHZ

tOHZ

tOH

tWC

tCW

tAS

100

Chip select to end of write

Address set-up time

Address valid to end of write

UB, LB Valid to End of Write

Write pulse width

tAW

tBW

tWP

tWR

tWHZ

tDW

tDH

Write

Write recovery time

Write to output high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

tOW

DATA RETENTION CHARACTERISTICS

Item

Symbol

VDR

Test Condition

Min

1.0

Typ

Max

Unit

CS³ Vcc-0.2V¹⁾

Vcc for data retention

Data retention current

Data retention set-up time

Recovery time

2.2

Vcc= 1.2V, CS³ Vcc-0.2V¹⁾

IDR

tSDR

tRDR

See data retention waveform

tRC

1. CS³ Vcc-0.2V(CS controlled) or LB=UB³ Vcc-0.2V, CS£0.2V(LB, UB controlled)

Revision 0.0

August 1998

- 5 -

Advance

K6F2016R4A Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO

tHZ

tBA

UB, LB

tBHZ

tOHZ

tOE

tOLZ

tBLZ

tLZ

Data out

High-Z

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 0.0

August 1998

- 6 -

Advance

K6F2016R4A Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

tAW

tBW

UB, LB

tWP(1)

tAS(3)

tDW

tDH

High-Z

Data in

Data Valid

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

tWC

Address

tAS(3)

tCW(2)

tWR(4)

tAW

tBW

UB, LB

tWP(1)

tDW

tDH

Data Valid

Data in

Data out

High-Z

Revision 0.0

August 1998

- 7 -

Advance

K6F2016R4A Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

tWC

Address

tCW(2)

tWR(4)

tAW

tBW

UB, LB

tAS(3)

tWP(1)

tDH

tDW

Data in

Data Valid

Data out

High-Z

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

Data Retention Mode

tSDR

tRDR

VCC

1.7V

1.4V

VDR

CS³ VCC - 0.2V or LB=UB³ Vcc-0.2V

CS, LB/UB

GND

Revision 0.0

August 1998

- 8 -

Advance

K6F2016R4A Family

CMOS SRAM

PACKAGE DIMENSIONS (Units : millimeter)

Top View

Bottom View

Ball #A1

B/2

SRAM Die

Elastomer

Detail A

Side View

Detail A

Elastomer

0.3/Typ.

Die

Min

Typ

0.75

6.00

3.75

8.00

5.25

0.35

0.93

0.68

0.25

Max

6.10

Notes.

1. Bump counts : 48(8row x 6column)

5.90

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

7.90

8.10

4. Typ : Typical

0.30

0.40

0.94

5. Y is coplanarity : 0.08(Max)

0.08

Revision 0.0

August 1998

- 9 -

K6F2016R4A-ZI700 [SAMSUNG]

相关型号：

K6F2016R4D-FF70

K6F2016R4D-FF85

K6F2016R4D-FF850

K6F2016R4E-EF70

K6F2016R4E-EF85

K6F2016R4E-EF850

K6F2016R4G

K6F2016R4G-F

K6F2016R4G-FF70

K6F2016R4G-FF700

K6F2016R4G-FF85

K6F2016R4G-FF850