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K6F2016U4G-FF55 [SAMSUNG]

2Mb(128K x 16 bit) Low Power SRAM; 2MB （ 128K ×16位）低功耗SRAM
K6F2016U4G-FF55
型号： K6F2016U4G-FF55
厂家： SAMSUNG    SAMSUNG
描述：

2Mb(128K x 16 bit) Low Power SRAM
2MB （ 128K ×16位）低功耗SRAM

静态存储器
文件： 总10页 (文件大小：161K)
中文：  中文翻译
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Preliminary  
K6F2016U4G Family  
CMOS SRAM  
2Mb(128K x 16 bit) Low Power SRAM  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,  
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.  
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,  
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROP-  
ERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.  
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT  
GUARANTEE OR WARRANTY OF ANY KIND.  
1. For updates or additional information about Samsung products, contact your nearest Samsung office.  
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-  
lar applications where Product failure could result in loss of life or personal or physical harm, or any military  
or defense application, or any governmental procurement to which special terms or provisions may apply.  
* Samsung Electronics reserves the right to change products or specification without notice.  
Revision 0.0  
April 2005  
- 1 -  
Preliminary  
K6F2016U4G Family  
CMOS SRAM  
Document Title  
128Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM  
Revision History  
Revision No. History  
Draft Date  
Remark  
0.0  
Initial Draft  
April 25, 2005  
Preliminary  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.  
Revision 0.0  
April 2005  
- 2 -  
Preliminary  
K6F2016U4G Family  
CMOS SRAM  
128K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
• Process Technology: Full CMOS  
• Organization: 128K x16 bit  
• Power Supply Voltage: 2.7~3.3V  
• Low Data Retention Voltage: 1.5V(Min)  
• Three State Outputs  
The K6F2016U4G families are fabricated by SAMSUNG′s  
advanced full CMOS process technology. The families support  
industrial temperature range and 48 ball Chip Scale Package  
for user flexibility of system design. The family also supports  
low data retention voltage for battery back-up operation with  
low data retention current.  
• Package Type: 48-FBGA-6.00x7.00  
PRODUCT FAMILY  
Power Dissipation  
Product Family Operating Temperature Vcc Range  
Speed  
PKG Type  
Standby  
(ISB1, Typ.)  
Operating  
(ICC1, Max)  
551)/70ns  
3µA2)  
K6F2016U4G-F  
Industrial(-40~85°C)  
2.7~3.3V  
4mA  
48-FBGA-6.00x7.00  
1. The parameter is measured with 30pF test load.  
2. Typical value is measured at VCC=3.0V, TA=25°C and not 100% tested.  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
1
2
3
4
5
6
Clk gen.  
Precharge circuit.  
A
B
C
D
E
F
LB  
OE  
UB  
A0  
A3  
A1  
A4  
A2  
DNU  
I/O1  
I/O3  
Vcc  
Vcc  
Vss  
I/O9  
CS  
Row  
Addresses  
Memory  
Cell  
Array  
Row  
select  
I/O10  
Vss  
I/O11  
I/O12  
I/O13  
I/O14  
DNU  
A8  
A5  
A6  
I/O2  
I/O4  
I/O5  
I/O6  
WE  
A11  
DNU  
DNU  
A14  
A12  
A9  
A7  
I/O Circuit  
Column select  
Data  
cont  
Vcc  
A16  
A15  
A13  
A10  
Vss  
I/O1~I/O8  
Data  
cont  
I/O9~I/O16  
I/O15  
I/O16  
DNU  
I/O7  
I/O8  
DNU  
Data  
cont  
G
H
Column Addresses  
48-FBGA: Top View (Ball Down)  
CS  
OE  
WE  
UB  
LB  
Control Logic  
Name  
CS  
Function  
Name  
Vcc  
Vss  
UB  
Function  
Power  
Chip Select Inputs  
Output Enable Input  
Write Enable Input  
Address Inputs  
OE  
Ground  
WE  
Upper Byte(I/O9~16)  
Lower Byte(I/O1~8)  
Do Not Use  
A0~A16  
LB  
I/O1~I/O16 Data Inputs/Outputs  
DNU  
Revision 0.0  
April 2005  
- 3 -  
Preliminary  
K6F2016U4G Family  
CMOS SRAM  
PRODUCT LIST  
Industrial Temperature Products(-40~85°C)  
Part Name  
Function  
K6F2016U4G-FF55  
K6F2016U4G-XF55  
K6F2016U4G-FF70  
K6F2016U4G-XF70  
48-FBGA, 55ns, 3.0V  
48-FBGA, 55ns, 3.0V, LF1)  
48-FBGA, 70ns, 3.0V  
48-FBGA, 70ns, 3.0V, LF1)  
1. LF : Lead Free Product  
FUNCTIONAL DESCRIPTION  
CS  
H
X1)  
L
OE  
X1)  
X1)  
H
WE  
X1)  
X1)  
H
LB  
X1)  
H
L
UB  
X1)  
H
I/O1~8  
High-Z  
High-Z  
High-Z  
High-Z  
Dout  
I/O9~16  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Dout  
Mode  
Power  
Standby  
Standby  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Deselected  
Deselected  
X1)  
L
Output Disabled  
Output Disabled  
Lower Byte Read  
Upper Byte Read  
Word Read  
X1)  
L
L
H
H
L
L
H
H
L
L
H
H
L
L
High-Z  
Dout  
L
L
H
L
Dout  
X1)  
X1)  
X1)  
L
L
L
H
Din  
High-Z  
Din  
Lower Byte Write  
Upper Byte Write  
Word Write  
L
L
H
L
L
High-Z  
Din  
L
L
L
Din  
1. X means don′t care. (Must be low or high state)  
ABSOLUTE MAXIMUM RATINGS1)  
Item  
Voltage on any pin relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
Symbol  
Ratings  
-0.3 to VCC+0.3V(Max. 3.6V)  
-0.3 to 3.6  
Unit  
V
VIN, VOUT  
VCC  
V
PD  
1.0  
W
Storage temperature  
TSTG  
TA  
-65 to 150  
°C  
°C  
Operating Temperature  
-40 to 85  
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be  
restricted within recommended operating condition. Exposure to absolute maximum rating conditions for extended period may affect reliability.  
Revision 0.0  
April 2005  
- 4 -  
Preliminary  
K6F2016U4G Family  
CMOS SRAM  
RECOMMENDED DC OPERATING CONDITIONS1)  
Item  
Symbol  
Vcc  
Min  
2.7  
0
Typ  
Max  
3.3  
Unit  
V
Supply voltage  
Ground  
3.0  
Vss  
0
-
0
V
Vcc+0.32)  
0.6  
Input high voltage  
Input low voltage  
VIH  
2.2  
-0.33)  
V
VIL  
-
V
Note:  
1. Industrial Product: TA=-40 to 85°C, otherwise specified.  
2. Overshoot: Vcc+2.0V in case of pulse width ≤20ns.  
3. Undershoot: -2.0V in case of pulse width ≤20ns.  
4. Overshoot and undershoot are sampled, not 100% tested.  
CAPACITANCE1) (f=1MHz, TA=25°C)  
Item  
Input capacitance  
Symbol  
CIN  
Test Condition  
Min  
Max  
8
Unit  
pF  
VIN=0V  
VIO=0V  
-
-
Input/Output capacitance  
CIO  
10  
pF  
1. Capacitance is sampled, not 100% tested  
DC AND OPERATING CHARACTERISTICS  
Typ1)  
Symbol  
Item  
Test Conditions  
Min  
Max  
Unit  
Input leakage current  
ILI  
VIN=Vss to Vcc  
-1  
-1  
-
1
1
µA  
CS=VIH or OE=VIH or WE=VIL or LB=UB=VIH,  
VIO=Vss to Vcc  
Output leakage current  
ILO  
-
-
µA  
Cycle time=1µs, 100%duty, IIO=0mA, CS≤0.2V,  
LB≤0.2V or/and UB≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V  
ICC1  
-
4
mA  
Average operating current  
Cycle time=Min, IIO=0mA, 100% duty, CS=VIL,  
LB=VIL or/and UB=VIL, VIN=VIL or VIH  
70ns  
55ns  
-
-
-
-
-
-
22  
27  
0.4  
-
mA  
ICC2  
Output low voltage  
Output high voltage  
VOL  
VOH  
IOL = 2.1mA  
IOH = -1.0mA  
-
V
V
2.4  
Other input =0~Vcc  
Standby Current (CMOS)  
ISB1  
1) CS≥Vcc-0.2V(CS controlled) or  
2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled)  
-
3
10  
µA  
1. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested.  
Revision 0.0  
April 2005  
- 5 -  
Preliminary  
K6F2016U4G Family  
CMOS SRAM  
3)  
VTM  
AC OPERATING CONDITIONS  
TEST CONDITIONS(Test Load and Test Input/Output Reference)  
Input pulse level: 0.4 to 2.2V  
2)  
2)  
R1  
Input rising and falling time: 5ns  
Input and output reference voltage: 1.5V  
Output load (See right): CL= 100pF+1TTL  
CL= 30pF+1TTL  
1)  
CL  
R2  
1. Including scope and jig capacitance  
2. R1=3070Ω, R2=3150Ω  
3. VTM =2.8V  
AC CHARACTERISTICS ( Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C )  
Speed  
Parameter List  
Symbol  
Units  
55ns  
70ns  
Min  
55  
-
Max  
Min  
70  
-
Max  
Read cycle time  
tRC  
tAA  
-
55  
55  
25  
55  
-
-
70  
70  
35  
70  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
Chip select to output  
tCO  
tOE  
-
-
Output enable to valid output  
UB, LB Access Time  
-
-
tBA  
-
-
Chip select to low-Z output  
UB, LB enable to low-Z output  
Output enable to low-Z output  
Chip disable to high-Z output  
UB, LB disable to high-Z output  
Output disable to high-Z output  
Output hold from address change  
Write cycle time  
tLZ  
10  
10  
5
10  
10  
5
Read  
tBLZ  
tOLZ  
tHZ  
-
-
-
-
0
20  
20  
20  
-
0
25  
25  
25  
-
tBHZ  
tOHZ  
tOH  
tWC  
tCW  
tAS  
0
0
0
0
10  
55  
45  
0
10  
70  
60  
0
-
-
Chip select to end of write  
Address set-up time  
-
-
-
-
Address valid to end of write  
UB, LB Valid to End of Write  
Write pulse width  
tAW  
tBW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
45  
45  
40  
0
-
60  
60  
50  
0
-
-
-
Write  
-
-
Write recovery time  
-
-
Write to output high-Z  
0
20  
-
0
20  
-
Data to write time overlap  
Data hold from write time  
End write to output low-Z  
25  
0
30  
0
-
-
tOW  
5
-
5
-
DATA RETENTION CHARACTERISTICS  
Item  
Symbol  
VDR  
Test Condition  
CS≥Vcc-0.2V1), VIN≥0V  
Min  
Typ  
Max  
Unit  
V
Vcc for data retention  
Data retention current  
Data retention set-up time  
Recovery time  
1.5  
-
-
-
-
-
3.3  
Vcc=1.5V, CS≥Vcc-0.2V1), VIN≥0V  
IDR  
3
-
µA  
tSDR  
tRDR  
0
See data retention waveform  
ns  
tRC  
-
1. 1) CS≥Vcc-0.2V(CS controlled) or  
2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled)  
Revision 0.0  
April 2005  
- 6 -  
Preliminary  
K6F2016U4G Family  
CMOS SRAM  
TIMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)  
tRC  
Address  
tAA  
tOH  
Data Valid  
Data Out  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tOH  
tAA  
tCO  
CS  
tHZ  
tBA  
UB, LB  
OE  
tBHZ  
tOHZ  
tOE  
tOLZ  
tBLZ  
tLZ  
Data out  
High-Z  
Data Valid  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
Revision 0.0  
April 2005  
- 7 -  
Preliminary  
K6F2016U4G Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
Address  
CS  
tWR(4)  
tCW(2)  
tAW  
tBW  
UB, LB  
tWP(1)  
WE  
tAS(3)  
tDW  
tDH  
High-Z  
High-Z  
Data in  
Data Valid  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)  
tWC  
Address  
tAS(3)  
tCW(2)  
tWR(4)  
CS  
tAW  
tBW  
UB, LB  
WE  
tWP(1)  
tDW  
tDH  
Data Valid  
Data in  
Data out  
High-Z  
High-Z  
Revision 0.0  
April 2005  
- 8 -  
Preliminary  
K6F2016U4G Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)  
tWC  
Address  
CS  
tCW(2)  
tWR(4)  
tAW  
tBW  
UB, LB  
WE  
tAS(3)  
tWP(1)  
tDH  
tDW  
Data in  
Data Valid  
High-Z  
Data out  
High-Z  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB  
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition  
when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.  
2. tCW is measured from the CS going low to the end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
DATA RETENTION WAVE FORM  
CS or LB/UB controlled  
Data Retention Mode  
tSDR  
tRDR  
VCC  
2.7V  
2.2V  
VDR  
CS≥VCC-0.2V or LB=UB≥VCC-0.2V  
CS or LB/UB  
GND  
Revision 0.0  
April 2005  
- 9 -  
Preliminary  
K6F2016U4G Family  
CMOS SRAM  
Unit: millimeters  
PACKAGE DIMENSION  
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)  
Top View  
B
Bottom View  
B
B1  
6
5
4
3
2
1
A
B
#A1  
C
D
E
F
G
H
B/2  
Detail A  
A
Side View  
D
Y
C
Min  
Typ  
0.75  
6.00  
3.75  
7.00  
5.25  
0.45  
Max  
-
A
B
-
Notes.  
5.90  
6.10  
-
1. Bump counts: 48(8 row x 6 column)  
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)  
3. All tolerence are +/-0.050 unless  
otherwise specified.  
B1  
C
-
6.90  
7.10  
-
C1  
D
-
0.40  
-
4. Typ: Typical  
0.50  
1.00  
5. Y is coplanarity: 0.10(Max)  
E
E1  
Y
0.25  
-
-
0.10  
Revision 0.0  
April 2005  
- 10 -  

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