K6F4008U2C-FF55 [SAMSUNG]
Standard SRAM, 512KX8, 55ns, CMOS, PBGA48, 6.50 X 8.50 MM, 0.75 MM PITCH, FBGA-48;型号: | K6F4008U2C-FF55 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 512KX8, 55ns, CMOS, PBGA48, 6.50 X 8.50 MM, 0.75 MM PITCH, FBGA-48 静态存储器 |
文件: | 总9页 (文件大小:145K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K6F4008U2C Family
CMOS SRAM
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
1.0
Initial Draft
July 28, 1999
Preliminary
Finalize
March 22, 2000
Final
- Adopt new code.
- Improve VIN, VOUT max. on ¢ABSOLUTE MAXIMUM RATINGS¢ from
3.6V to VCC+0.5V.
2.0
Change for AC parameter
April 24, 2000
Final
- Change for tWHZ: 25 to 20ns for 70ns product
- Change for tDW: 20 to 25ns for 55ns product
25 to 30ns for 70ns product
- Errata correction
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 2.0
April 2000
- 1 -
K6F4008U2C Family
CMOS SRAM
512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: Full CMOS
· Organization: 512K x8 bit
The K6F4008U2C families are fabricated by SAMSUNG¢s
advanced full CMOS process technology. The families support
industrial temperature range and Chip Scale Package for user
flexibility of system design. The families also supports low data
retention voltage for battery back-up operation with low data
retention current.
· Power Supply Voltage: 2.7~3.3V
· Low Data Retention Voltage: 1.5V(Min)
· Three state output status and TTL Compatible
· Package Type: 48-FBGA-6.50x8.50
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Typ.)
Operating
(ICC1, Max)
551)/70ns
K6F4008U2C-F
Industrial(-40~85°C)
2.7~3.3V
0.5mA
3mA
48-FBGA-6.50x8.50
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Precharge circuit.
A
B
C
D
E
F
A0
A1
A2
CS2
WE
A3
A4
A5
A6
A7
A8
I/O5
I/O1
I/O2
VCC
VSS
I/O3
I/O4
A14
Memory array
1024 rows
512´ 8 columns
Row
select
I/O6
VSS
DNU
48(36)-FBGA
VCC
I/O7
I/O8
A9
Data
cont
I/O Circuit
I/O1
I/O8
Column select
A18
CS1
A11
A17
A16
A12
Data
cont
G
H
OE
A10
A15
A13
CS1
Control
logic
CS2
WE
OE
Name
Function
Name
Function
CS1, CS2 Chip Select Inputs
I/O1~I/O8 Data Inputs/Outputs
OE
Output Enable Input
Write Enable Input
Vcc
Vss
Power
WE
Ground
A0~A18 Address Inputs
DNU
Do Not Use
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 2.0
April 2000
- 2 -
K6F4008U2C Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K6F4008U2C-FF55
K6F4008U2C-FF70
48-FBGA, 55ns, 3.0V
48-FBGA, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Deselected
Deselected
Output Disabled
Read
Power
Standby
Standby
Active
X1)
L
X1)
X1)
H
High-Z
High-Z
High-Z
Dout
X1)
L
X1)
H
X1)
H
H
H
H
L
L
L
H
L
Active
X1)
Din
Write
Active
1. X means don¢t care (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Ratings
-0.2 to VCC+0.5V
-0.2 to 4.0V
1.0
Unit
VIN, VOUT
VCC
V
V
PD
W
°C
°C
Storage temperature
TSTG
TA
-65 to 150
-40 to 85
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 2.0
April 2000
- 3 -
K6F4008U2C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
2.7
0
Typ
Max
3.3
Unit
V
Supply voltage
Ground
3.0
Vss
0
-
0
V
Vcc+0.22)
0.6
Input high voltage
Input low voltage
VIH
2.2
-0.23)
V
VIL
-
V
Note:
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width £20ns.
3. Undershoot: -2.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN=0V
VIO=0V
-
-
Input/Output capacitance
CIO
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Symbol
ILI
Item
Test Conditions
Min
Typ
Max
Unit
mA
Input leakage current
Output leakage current
Operating power supply
VIN=Vss to Vcc
-1
-1
-
-
-
-
1
1
2
ILO
CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, WE=VIH, VIN=VIH or VIL
mA
ICC
mA
Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V,
CS2³ Vcc-0.2V, VIN£0.2V or VIN³ VCC-0.2V
ICC1
ICC2
-
-
-
-
3
mA
mA
Average operating current
Cycle time=Min, IIO=0mA, 100% duty,
CS1=VIL, CS2=VIH, VIN=VIL or VIH
30
Output low voltage
Output high voltage
Standby Current(TTL)
VOL
VOH
ISB
IOL = 2.1mA
-
2.4
-
-
-
-
0.4
-
V
V
IOH = -1.0mA
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
0.3
mA
CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or
CS2£0.2V(CS2 controlled), Other inputs=0~Vcc
121)
Standby Current (CMOS)
ISB1
-
0.5
mA
1. Super low power product=5mA with special handling.
Revision 2.0
April 2000
- 4 -
K6F4008U2C Family
CMOS SRAM
3)
VTM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
2)
R1
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL= 100pF+1TTL
CL=30pF+1TTL
1)
2)
CL
R2
1. Including scope and jig capacitance
2. R1=3070W, R2=3150W
3. VTM =2.8V
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
55ns
70ns
Min
55
-
Max
Min
70
-
Max
Read Cycle Time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
-
-
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
-
-
Read
tLZ
10
5
10
5
tOLZ
tHZ
-
-
0
20
20
-
0
25
25
-
tOHZ
tOH
tWC
tCW
tAS
0
0
10
55
45
0
10
70
60
0
-
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
-
60
50
0
-
-
-
Write
Write Recovery Time
-
-
Write to Output High-Z
0
20
-
0
20
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
25
0
30
0
-
-
tOW
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
Test Condition
Min
Typ
Max
Unit
V
CS1³ Vcc-0.2V1)
1.5
-
-
0.5
-
3.3
Vcc=1.5V, CS1³ Vcc-0.2V1)
32)
-
IDR
mA
tSDR
tRDR
0
See data retention waveform
ns
tRC
-
-
1. CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or CS2£0.2V(CS2 controlled).
2. Super low power product=2mA with special handling.
Revision 2.0
April 2000
- 5 -
K6F4008U2C Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 2.0
April 2000
- 6 -
K6F4008U2C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
CS1
tCW(2)
tAS(3)
tWR(4)
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
Revision 2.0
April 2000
- 7 -
K6F4008U2C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
CS1
tAS(3)
tCW(2)
tWR(4)
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP
is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CS1³ VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
2.7V
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
Revision 2.0
April 2000
- 8 -
K6F4008U2C Family
CMOS SRAM
Units: millimeters
PACKAGE DIMENSIONS
48 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View
B
Bottom View
A1 INDEX MARK
0.50
B
B1
0.50
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.50
3.75
8.50
5.25
0.35
1.10
0.85
0.25
-
Max
-
A
B
-
Notes.
6.40
6.60
-
1. Bump counts: 48(8row x 6column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
B1
C
-
8.40
8.60
-
C1
D
-
4. Typ: Typical
0.30
0.40
1.20
-
5. Y is coplanarity: 0.08(Max)
E
-
E1
E2
Y
-
0.20
-
0.30
0.08
Revision 2.0
April 2000
- 9 -
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