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K6F4008V1D-YF55T [SAMSUNG]

Standard SRAM, 512KX8, 55ns, CMOS, PDSO32;
K6F4008V1D-YF55T
型号： K6F4008V1D-YF55T
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 512KX8, 55ns, CMOS, PDSO32

静态存储器 光电二极管
文件： 总8页 (文件大小：105K)
中文：  中文翻译
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K6F4008V1D Family  
CMOS SRAM  
Document Title  
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM  
Revision History  
Revision No. History  
Draft Date  
Remark  
0.0  
1.0  
Initial Draft  
March 16, 2000  
Preliminary  
Finalized  
April 24, 2000  
Final  
- Change for tWHZ: 25 to 20ns for 70ns product  
- Change for tDW: 20 to 25ns for 55ns product  
25 to 30ns for 70ns product  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.  
Revision 1.0  
April 2000  
- 1 -  
K6F4008V1D Family  
CMOS SRAM  
512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
· Process Technology: Full CMOS  
· Organization: 512K x8 bit  
The K6F4008V1D families are fabricated by SAMSUNG¢s  
advanced full CMOS process technology. The families support  
small package type for user flexibility of system design. The  
families also supports low data retention voltage for battery  
back-up operation with low data retention current.  
· Power Supply Voltage: 3.0~3.6V  
· Low Data Retention Voltage: 1.5V(Min)  
· Three state output status and TTL Compatible  
· Package Type: 32-TSOP1-0813.4F  
PRODUCT FAMILY  
Power Dissipation  
Product Family Operating Temperature Vcc Range  
Speed  
PKG Type  
Standby  
(ISB1, Typ.)  
Operating  
(ICC1, Max)  
551)/70ns  
K6F4008V1D-F  
Industrial(-40~85°C)  
3.0~3.6V  
0.5mA  
3mA  
32-TSOP1-0813.4F  
1. The parameter is measured with 30pF test load.  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
A11  
A9  
A8  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
OE  
A10  
CS  
Clk gen.  
Precharge circuit.  
A13  
WE  
A18  
A15  
VCC  
A17  
A16  
A14  
A12  
A7  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
VSS  
I/O3  
I/O2  
I/O1  
A0  
32-STSOP1  
(Forward)  
9
10  
11  
12  
13  
14  
15  
16  
Memory array  
2048 rows  
256´ 8 columns  
Raw  
Address  
Row  
select  
A6  
A5  
A4  
A1  
A2  
A3  
Name Function  
Name Function  
CS  
WE  
OE  
Chip Select Input  
Write Enable Input  
Vcc  
Vss  
Power  
I/O1  
I/O8  
Data  
cont  
I/O Circuit  
Column select  
Ground  
Output Enable Input I/O1~I/O8 Data Inputs/Outputs  
Data  
cont  
A0~A18 Address Inputs  
Column Address  
CS  
Control  
logic  
WE  
OE  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
Revision 1.0  
April 2000  
- 2 -  
K6F4008V1D Family  
CMOS SRAM  
PRODUCT LIST  
Industrial Temperature Products(-40~85°C)  
Part Name  
Function  
K6F4008V1D-YF55  
K6F4008V1D-YF70  
32-sTSOP1-F 55ns, 3.3V  
32-sTSOP1-F 70ns, 3.3V  
FUNCTIONAL DESCRIPTION  
CS  
H
L
OE  
WE  
I/O  
High-Z  
High-Z  
Dout  
Mode  
Deselected  
Output Disabled  
Read  
Power  
Standby  
Active  
X1)  
H
X1)  
H
L
L
H
L
Active  
X1)  
L
Din  
Write  
Active  
1. X means don¢t care (Must be in low or high state)  
ABSOLUTE MAXIMUM RATINGS1)  
Item  
Voltage on any pin relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
Symbol  
Ratings  
-0.2 to VCC+0.5V  
-0.2 to 4.6V  
1.0  
Unit  
V
VIN, VOUT  
VCC  
V
PD  
W
Storage temperature  
TSTG  
TA  
-65 to 150  
-40 to 85  
°C  
°C  
Operating Temperature  
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be  
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
Revision 1.0  
April 2000  
- 3 -  
K6F4008V1D Family  
CMOS SRAM  
RECOMMENDED DC OPERATING CONDITIONS1)  
Item  
Symbol  
Vcc  
Min  
3.0  
0
Typ  
Max  
3.6  
Unit  
V
Supply voltage  
Ground  
3.3  
Vss  
0
-
0
V
Vcc+0.32)  
0.6  
Input high voltage  
Input low voltage  
VIH  
2.2  
-0.23)  
V
VIL  
-
V
Note:  
1. TA=-40 to 85°C, otherwise specified.  
2. Overshoot: Vcc+2.0V in case of pulse width £20ns.  
3. Undershoot: -2.0V in case of pulse width £20ns.  
4. Overshoot and undershoot are sampled, not 100% tested.  
CAPACITANCE1) (f=1MHz, TA=25°C)  
Item  
Input capacitance  
Symbol  
CIN  
Test Condition  
Min  
Max  
Unit  
VIN=0V  
VIO=0V  
-
-
8
pF  
pF  
Input/Output capacitance  
CIO  
10  
1. Capacitance is sampled, not 100% tested.  
DC AND OPERATING CHARACTERISTICS  
Item  
Symbol  
ILI  
Test Conditions  
Min Typ Max Unit  
Input leakage current  
Output leakage current  
Operating power supply current  
VIN=Vss to Vcc  
-1  
-
1
1
2
3
mA  
mA  
ILO  
CS=VIH, or OE=VIH or WE=VIL, VIO=Vss to Vcc  
IIO=0mA, CS=VIL, WE=VIH, VIN=VIL or VIH, Reed  
-1  
-
ICC  
-
-
mA  
mA  
Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V, VIN£0.2V or VIN³ VCC-0.2V  
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIL or VIH  
IOL = 2.1mA  
ICC1  
ICC2  
VOL  
VOH  
ISB  
-
-
Average operating current  
-
-
35 mA  
Output low voltage  
-
2.4  
-
-
-
0.4  
-
V
V
Output high voltage  
Standby Current(TTL)  
Standby Current (CMOS)  
IOH = -1.0mA  
CS=VIH, Other inputs=VIL or VIH  
-
0.3 mA  
mA  
151)  
ISB1  
CS³ Vcc-0.2V, Other input =0~Vcc  
-
0.5  
1. Super low power product=7mA with special handling.  
Revision 1.0  
April 2000  
- 4 -  
K6F4008V1D Family  
CMOS SRAM  
3)  
VTM  
AC OPERATING CONDITIONS  
TEST CONDITIONS (Test Load and Test Input/Output Reference)  
Input pulse level: 0.4 to 2.2V  
2)  
R1  
Input rising and falling time: 5ns  
Input and output reference voltage:1.5V  
Output load (See right): CL= 100pF+1TTL  
CL=30pF+1TTL  
1)  
2)  
CL  
R2  
1. Including scope and jig capacitance  
2. R1=3070W, R2=3150W  
3. VTM =2.8V  
AC CHARACTERISTICS(Vcc=3.0~3.6V, Industrial product: TA=-40 to 85°C)  
Speed Bins  
Parameter List  
Symbol  
Units  
55ns  
70ns  
Min  
55  
-
Max  
Min  
70  
-
Max  
Read Cycle Time  
tRC  
tAA  
-
55  
55  
25  
-
-
70  
70  
35  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
tLZ  
-
-
Output Enable to Valid Output  
Chip Select to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Write Cycle Time  
-
-
Read  
10  
5
10  
5
tOLZ  
tHZ  
-
-
0
20  
20  
-
0
25  
25  
-
tOHZ  
tOH  
tWC  
tCW  
tAS  
0
0
10  
55  
45  
0
10  
70  
60  
0
-
-
Chip Select to End of Write  
Address Set-up Time  
-
-
-
-
Address Valid to End of Write  
Write Pulse Width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
tOW  
45  
40  
0
-
60  
50  
0
-
-
-
Write  
Write Recovery Time  
-
-
Write to Output High-Z  
0
20  
-
0
20  
-
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Output Low-Z  
25  
0
30  
0
-
-
5
-
5
-
DATA RETENTION CHARACTERISTICS  
Item  
Vcc for data retention  
Data retention current  
Data retention set-up time  
Recovery time  
Symbol  
VDR  
Test Condition  
Min  
1.5  
-
Typ  
Max  
Unit  
V
-
0.5  
-
3.6  
CS³ Vcc-0.2V  
31)  
-
IDR  
Vcc=1.5V, CS³ Vcc-0.2V  
mA  
tSDR  
0
See data retention waveform  
ns  
tRDR  
tRC  
-
-
1. Super low power product=2mA with special handling.  
Revision 1.0  
April 2000  
- 5 -  
K6F4008V1D Family  
CMOS SRAM  
TIMMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)  
tRC  
Address  
tAA  
tOH  
Data Out  
Data Valid  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tOH  
tAA  
tCO  
CS  
tHZ  
tOE  
OE  
tOHZ  
tOLZ  
tLZ  
High-Z  
Data out  
Data Valid  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
Revision 1.0  
April 2000  
- 6 -  
K6F4008V1D Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
Address  
tCW(2)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tAS(3)  
tDW  
tDH  
Data Valid  
Data in  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)  
tWC  
Address  
tCW(2)  
tAS(3)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tDW  
tDH  
Data in  
Data Valid  
High-Z  
Data out  
High-Z  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE  
going low: A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write  
to the end of write.  
2. tCW is measured from the CS going low to end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
DATA RETENTION WAVE FORM  
CS controlled  
Data Retention Mode  
tSDR  
tRDR  
VCC  
3.0V  
2.2V  
VDR  
CS³ VCC - 0.2V  
CS  
GND  
Revision 1.0  
April 2000  
- 7 -  
K6F4008V1D Family  
CMOS SRAM  
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)  
Unit: millimeters(inches)  
+0.10  
-0.05  
+0.004  
0.20  
13.40±0.10  
0.528±0.008  
0.008  
-0.002  
#1  
#32  
0.25  
0.010  
(
)
8.40  
0.331  
MAX  
0.50  
0.0197  
#17  
#16  
1.00±0.10  
0.039±0.004  
0.05  
0.002  
MIN  
1.20  
MAX  
0.047  
0.25  
0.010  
TYP  
11.80±0.10  
0.465±0.004  
+0.10  
-0.05  
0.15  
0.006+0.004  
-0.002  
0~8°  
0.50  
0.020  
0.45 ~0.75  
0.018 ~0.030  
(
)
Revision 1.0  
April 2000  
- 8 -  

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