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K6F8016U6A-EF55 [SAMSUNG]

Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 7 X 9 MM, 0.75 MM PITCH, TBGA-48;
K6F8016U6A-EF55
型号： K6F8016U6A-EF55
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 7 X 9 MM, 0.75 MM PITCH, TBGA-48

静态存储器 内存集成电路
文件： 总9页 (文件大小：158K)
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K6F8016U6A Family  
CMOS SRAM  
Document Title  
512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM  
Revision History  
Revision No. History  
Draft Date  
Remark  
0.0  
Initial draft  
August 14, 2000  
Preliminary  
0.1  
Revise  
September 28, 2000 Preliminary  
- Change Package type from FBGA to TBGA  
1.0  
Finalize  
- Improved ICC1 from 4 to 3mA  
- Removed ICC, ISB  
March 14, 2001  
April 3, 2001  
Final  
1.01  
2.0  
Revise  
- Errata correction for finalized year from 2000 to 2001  
Revise  
September 27, 2001 Revise  
- ISB1 change : 25mA to 15mA  
- ICC2 change : 40mA to 35mA for 55ns product  
35mA to 28mA for 70ns product  
- Remove "A1 Index Mark" of 48-TBGA package bottom side  
- Changed 48-TBGA vertical dimension  
E1(typical) 0.55mm to 0.58mm  
E2(typical) 0.35mm to 0.32mm  
3.0  
Revise  
January 17, 2002  
Final  
- ICC2 change : 35mA to 40mA for 55ns product  
28mA to 30mA for 70ns product  
- Changed 48-TBGA vertical dimension  
E1(typical) 0.58mm to 0.55mm  
E2(typical) 0.32mm to 0.35mm  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.  
1
Revision 3.0  
January 2002  
K6F8016U6A Family  
CMOS SRAM  
512K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
· Process Technology: Full CMOS  
· Organization: 512K x16  
The K6F8016U6A families are fabricated by SAMSUNG¢s  
advanced full CMOS process technology. The families support  
industrial operating temperature ranges and have chip scale  
package for user flexibility of system design. The families also  
support low data retention voltage for battery back-up operation  
with low data retention current.  
· Power Supply Voltage: 2.7~3.3V  
· Low Data Retention Voltage: 1.5V(Min)  
· Three State Outputs  
· Package Type: 48-TBGA-7.00x9.00  
PRODUCT FAMILY  
Power Dissipation  
Product Family  
Operating Temperature Vcc Range  
Speed  
PKG Type  
Standby  
(ISB1, Typ.)  
Operating  
(ICC1, Max)  
551)/70ns  
0.5mA2)  
K6F8016U6A-F  
Industrial(-40~85°C)  
2.7~3.3V  
3mA  
48-TBGA-7.00x9.00  
1. The parameter is measured with 30pF test load.  
2. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested.  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
1
2
3
4
5
6
Clk gen.  
Precharge circuit.  
A
B
C
D
E
F
LB  
OE  
UB  
A0  
A3  
A1  
A4  
A2  
CS2  
I/O1  
I/O3  
Vcc  
Vcc  
Vss  
I/O9  
I/O10  
Vss  
CS1  
I/O2  
I/O4  
I/O5  
I/O6  
WE  
Row  
Addresses  
Memory array  
1024 rows  
512´ 16 columns  
Row  
select  
I/O11  
I/O12  
I/O13  
I/O14  
DNU  
A8  
A5  
A6  
A17  
Vss  
A14  
A12  
A9  
A7  
Data  
cont  
I/O Circuit  
Column select  
I/O1~I/O8  
Vcc  
A16  
A15  
A13  
A10  
Vss  
Data  
cont  
I/O9~I/O16  
I/O15  
I/O16  
A18  
I/O7  
I/O8  
DNU  
Data  
cont  
G
H
Column Addresses  
A11  
CS1  
CS2  
OE  
48 ball TBGA - Top View(Ball Down)  
Function Name Function  
Control Logic  
WE  
UB  
Name  
LB  
CS1, CS2 Chip Select Inputs  
Vcc Power  
Vss Ground  
OE  
WE  
Output Enable Input  
Write Enable Input  
Address Inputs  
UB  
LB  
Upper Byte(I/O9~16)  
Lower Byte(I/O1~8)  
A0~A18  
I/O1~I/O16 Data Inputs/Outputs  
DNU Do Not Use  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
2
Revision 3.0  
January 2002  
K6F8016U6A Family  
CMOS SRAM  
PRODUCT LIST  
Industrial Temperature Products(-40~85°C)  
Part Name  
Function  
K6F8016U6A-EF55  
K6F8016U6A-EF70  
48-TBGA, 55ns, 3.0V  
48-TBGA, 70ns, 3.0V  
FUNCTIONAL DESCRIPTION  
CS1  
H
X1)  
X1)  
L
CS2  
X1)  
L
OE  
X1)  
X1)  
X1)  
H
WE  
X1)  
X1)  
X1)  
H
LB  
X1)  
X1)  
H
UB  
X1)  
X1)  
H
I/O1~8  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Dout  
I/O9~16  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Dout  
Mode  
Power  
Standby  
Standby  
Standby  
Active  
Deselected  
Deselected  
X1)  
H
Deselected  
X1)  
L
L
Output Disabled  
Output Disabled  
Lower Byte Read  
Upper Byte Read  
Word Read  
X1)  
L
L
H
H
H
Active  
L
H
L
H
H
Active  
L
H
L
H
H
L
High-Z  
Dout  
Active  
L
H
L
H
L
L
Dout  
Active  
X1)  
X1)  
X1)  
L
H
L
L
H
Din  
High-Z  
Din  
Lower Byte Write  
Upper Byte Write  
Word Write  
Active  
L
H
L
H
L
High-Z  
Din  
Active  
L
H
L
L
L
Din  
Active  
1. X means don¢t care. (Must be low or high state)  
ABSOLUTE MAXIMUM RATINGS1)  
Item  
Voltage on any pin relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
Symbol  
VIN, VOUT  
VCC  
Ratings  
-0.5 to VCC+0.3V(Max. 3.6V)  
-0.3 to 3.6  
Unit  
V
V
PD  
1.0  
W
°C  
°C  
Storage temperature  
TSTG  
-65 to 150  
Operating Temperature  
TA  
-40 to 85  
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be  
restricted to recommended operating condition. Exposure to absolute maximum rating conditions over 1 seconds may affect reliability.  
3
Revision 3.0  
January 2002  
K6F8016U6A Family  
CMOS SRAM  
RECOMMENDED DC OPERATING CONDITIONS1)  
Item  
Symbol  
Vcc  
Min  
2.7  
0
Typ  
Max  
3.3  
0
Unit  
V
Supply voltage  
Ground  
3.0  
Vss  
0
-
V
Vcc+0.32)  
0.6  
Input high voltage  
Input low voltage  
Note:  
VIH  
2.2  
V
-0.33)  
VIL  
-
V
1. TA=-40 to 85°C, otherwise specified.  
2. Overshoot: VCC+2.0V in case of pulse width £20ns.  
3. Undershoot: -2.0V in case of pulse width £20ns.  
4. Overshoot and undershoot are sampled, not 100% tested.  
CAPACITANCE1) (f=1MHz, TA=25°C)  
Item  
Input capacitance  
Symbol  
CIN  
Test Condition  
VIN=0V  
Min  
Max  
8
Unit  
pF  
-
-
Input/Output capacitance  
CIO  
VIO=0V  
10  
pF  
1. Capacitance is sampled, not 100% tested.  
DC AND OPERATING CHARACTERISTIC  
Typ1)  
Item  
Symbol  
Test Conditions  
Min  
Max Unit  
Input leakage current  
ILI  
VIN=Vss to Vcc  
-1  
-
1
1
mA  
mA  
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or  
LB=UB=VIH, VIO=Vss to Vcc  
Output leakage current  
ILO  
-1  
-
Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V,  
ICC1  
-
-
3
mA  
mA  
LB£0.2V or/and UB£0.2V, CS2³ Vcc-0.2V, VIN£0.2V or  
VIN³ VCC-0.2V  
Average operating current  
70ns  
55ns  
-
-
-
-
30  
40  
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL,  
CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH  
ICC2  
Output low voltage  
Output high voltage  
VOL  
VOH  
IOL = 2.1mA  
-
-
-
0.4  
-
V
V
IOH = -1.0mA  
2.4  
Other input =0~Vcc  
Standby Current(CMOS)  
ISB1  
1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or  
2) 0V£CS2£0.2V(CS2 controlled)  
-
0.5  
15  
mA  
1. Typical value are measured at VCC=3.0V, TA=25°C and not 100% tested.  
4
Revision 3.0  
January 2002  
K6F8016U6A Family  
CMOS SRAM  
3)  
VTM  
AC OPERATING CONDITIONS  
TEST CONDITIONS(Test Load and Input/Output Reference)  
Input pulse level: 0.4 to 2.2V  
2)  
R1  
Input rising and falling time: 5ns  
Input and output reference voltage: 1.5V  
Output load(see right): CL=100pF+1TTL  
CL=30pF+1TTL  
1)  
2)  
CL  
R2  
1. Including scope and jig capacitance  
2. R1=3070W, R2=3150W  
3. VTM =2.8V  
AC CHARACTERISTICS (Vcc=2.7~3.3V, Industrial product: TA=-40 to 85°C)  
Speed Bins  
Parameter List  
Symbol  
Units  
55ns  
70ns  
Min  
55  
-
Max  
Min  
Max  
Read Cycle Time  
tRC  
tAA  
-
55  
55  
25  
55  
-
70  
-
-
70  
70  
35  
70  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
-
-
Output Enable to Valid Output  
UB, LB Access Time  
-
-
tBA  
-
-
Chip Select to Low-Z Output  
UB, LB Enable to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
UB, LB Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Write Cycle Time  
tLZ  
10  
10  
5
10  
10  
5
Read  
tBLZ  
tOLZ  
tHZ  
-
-
-
-
0
20  
20  
20  
-
0
25  
25  
25  
-
tBHZ  
tOHZ  
tOH  
tWC  
tCW  
tAS  
0
0
0
0
10  
55  
45  
0
10  
70  
60  
0
-
-
Chip Select to End of Write  
Address Set-up Time  
-
-
-
-
Address Valid to End of Write  
UB, LB Valid to End of Write  
Write Pulse Width  
tAW  
tBW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
45  
45  
40  
0
-
60  
60  
50  
0
-
-
-
Write  
-
-
Write Recovery Time  
-
-
Write to Output High-Z  
0
20  
-
0
20  
-
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Output Low-Z  
25  
0
30  
0
-
-
tOW  
5
-
5
-
DATA RETENTION CHARACTERISTICS  
Typ2)  
Item  
Symbol  
Test Condition  
Min  
1.5  
-
Max  
Unit  
V
CS1³ Vcc-0.2V1)  
Vcc for data retention  
Data retention current  
Data retention set-up time  
Recovery time  
VDR  
-
0.5  
-
3.3  
Vcc=1.5V, CS1³ Vcc-0.2V1)  
IDR  
6
-
mA  
tSDR  
0
See data retention waveform  
ns  
tRDR  
tRC  
-
-
1. 1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or  
2) 0£CS2£0.2V(CS2 controlled)  
2. Typical value are measured at TA=25°C and not 100% tested.  
5
Revision 3.0  
January 2002  
K6F8016U6A Family  
CMOS SRAM  
TIMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)  
tRC  
Address  
tAA  
tOH  
Data Valid  
Data Out  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tOH  
tAA  
tCO  
CS1  
CS2  
tHZ  
tBA  
UB, LB  
OE  
tBHZ  
tOHZ  
tOE  
tOLZ  
tBLZ  
tLZ  
Data out  
High-Z  
Data Valid  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
6
Revision 3.0  
January 2002  
K6F8016U6A Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
Address  
CS1  
tCW(2)  
tWR(4)  
CS2  
tAW  
tBW  
UB, LB  
tWP(1)  
WE  
tAS(3)  
tDW  
tDH  
High-Z  
High-Z  
Data in  
Data Valid  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)  
tWC  
Address  
tCW(2)  
tAW  
tAS(3)  
tWR(4)  
CS1  
CS2  
tBW  
UB, LB  
tWP(1)  
WE  
tDW  
tDH  
Data Valid  
Data in  
Data out  
High-Z  
High-Z  
7
Revision 3.0  
January 2002  
K6F8016U6A Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)  
tWC  
Address  
CS1  
tCW(2)  
tAW  
tWR(4)  
CS2  
tBW  
UB, LB  
tAS(3)  
tWP(1)  
WE  
tDH  
tDW  
Data in  
Data Valid  
High-Z  
Data out  
High-Z  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting  
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-  
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.  
2. tCW is measured from the CS1 going low to the end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high.  
DATA RETENTION WAVE FORM  
CS1 controlled  
Data Retention Mode  
tSDR  
tRDR  
VCC  
2.7V  
2.2V  
VDR  
CS1³ VCC - 0.2V  
CS1  
GND  
CS2 controlled  
Data Retention Mode  
VCC  
2.7V  
CS2  
tSDR  
tRDR  
VDR  
CS2£0.2V  
0.4V  
GND  
8
Revision 3.0  
January 2002  
K6F8016U6A Family  
CMOS SRAM  
Unit: millimeters  
PACKAGE DIMENSION  
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)  
Top View  
B
Bottom View  
B
B1  
6
5
4
3
2
1
A
B
#A1  
C
D
E
F
G
H
B/2  
Detail A  
Side View  
D
A
Y
C
Min  
Typ  
0.75  
7.00  
3.75  
9.00  
5.25  
0.45  
0.90  
0.55  
0.35  
-
Max  
-
A
B
-
6.90  
-
Notes.  
7.10  
-
1. Ball counts: 48(8 row x 6 column)  
2. Ball pitch: (x,y)=(0.75 x 0.75)(typ.)  
3. All tolerence are ±0.050 unless  
specified beside figure.  
B1  
C
8.90  
-
9.10  
-
C1  
D
4. Typ: Typical  
0.40  
0.80  
-
0.50  
1.00  
-
5. Y is coplanarity: 0.08(Max)  
E
E1  
E2  
Y
0.30  
-
0.40  
0.08  
9
Revision 3.0  
January 2002  

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