K6R1004V1C-P10 [SAMSUNG]
256Kx4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating).; 256Kx4位（与OE ）高速CMOS静态RAM （ 3.3V工作） 。
| 型号： | K6R1004V1C-P10 |
| 厂家： | 
SAMSUNG |
| 描述： | 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating). |
| 文件： | 总9页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
PRELIMINARY
CMOS SRAM
K6R1004V1C-C/C-L, K6R1004V1C-I/C-P
Document Title
256Kx4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating).
Preliminary
CCPCCCRCELIMINARY
Revision History
Rev.No.
Rev. 0.0
Rev. 1.0
History
Draft Data
Remark
Preliminary
Final
Initial release with Preliminary.
Aug. 5th. 1998
Sep. 7th. 1998
Release to Final Data Sheet.
1.1. Delete Preliminary.
1.2. Relax DC characteristics.
Item
Previous
65mA
63mA
Changed
70mA
68mA
ICC
12ns
15ns
20ns
60mA
65mA
Final
Rev. 2.0
Add 10ns & Low Power Ver.
Apr. 24. 2000
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision 2.0
April 2000
- 1 -
PRELIMINARY
PRELIMINARY
CMOS SRAM
K6R1004V1C-C/C-L, K6R1004V1C-I/C-P
256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
The K6R1004V1C is a 1,048,576-bit high-speed Static Random
Ac6cRPe1s0s Memory organized as 262,144 words by 4 bits. The
C
04V
C
1C
C
u
RC
4
E
co
L
mmIMon i
I
n
N
put
A
an
R
d o
Y
ses Preliminaryutput lines and has
Standby (TTL)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-Ver. only
: 30mA(Max.)
C
K
C
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG¢s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
Operating K6R1004V1C-10 : 75mA(Max.)
K6R1004V1C-12 : 70mA(Max.)
K6R1004V1C-15 : 68mA(Max.)
K6R1004V1C-20 : 65mA(Max.)
Single 3.3±0.3V Power Supply
TTL Compatible Inputs and Outputs
Fully Static Operation
high-density
high-speed
system
applications.
The
K6R1004V1C is packaged in a 400 mil 32-pin plastic SOJ.
•
•
•
- No Clock or Refresh required
Three State Outputs
2V Mimimum Data Retention ; L-ver. Only
Center Power/Ground Pin Configuration
• Standard Pin Configuration :
K6R1004V1C-J : 32-SOJ-400
ORDERING INFORMATION
•
•
•
K6R1004V1C-C10/C12/C15/C20
K6R1004V1C-I10/I12/I15/I20
Commercial Temp.
Industrial Temp.
PIN CONFIGURATION(Top View)
A17
A16
A15
A14
A13
OE
N.C
A0
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FUNCTIONAL BLOCK DIAGRAM
A1
A2
A3
Clk Gen.
Pre-Charge Circuit
CS
I/O1
Vcc
Vss
I/O4
Vss
Vcc
I/O3
A12
A11
A10
A9
A0
A1
A2
A3
A4
SOJ
Memory Array
512 Rows
512x4 Columns
I/O2 10
WE 11
A4 12
A5 13
A6 14
A7 15
N.C 16
A5
A6
A7
A8
A8
Data
Cont.
I/O Circuit &
Column Select
I/O1 ~ I/O4
N.C
CLK
Gen.
PIN FUNCTION
A9 A10 A11 A12 A13 A14 A15 A16 A17
Pin Name
A0 - A17
WE
Pin Function
Address Inputs
Write Enable
Chip Select
CS
WE
OE
CS
OE
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
I/O1 ~ I/O4
VCC
VSS
N.C
No Connection
Revision 2.0
April 2000
- 2 -
PRELIMINARY
PRELIMINARY
K6R1004V1C-C/C-L, K6R1004V1C-I/C-P
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
Unit
V
-0.5 to 4.6
-0.5 to 4.6
V
Preliminary
CCPCCCRCELIMINARY
Pd
TSTG
TA
1
W
°C
°C
°C
Storage Temperature
-65 to 150
0 to 70
Operating Temperature
Commercial
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter
Supply Voltage
Symbol
Min
3.0
0
Typ
Max
Unit
V
VCC
3.3
3.6
0
Ground
VSS
0
-
V
V
Input High Voltage
Input Low Voltage
VIH
2.2
-0.5*
VCC+0.5**
0.8
VIL
-
V
* VIL(Min) = -2.0V a.c (Pulse Width £ 8ns) for I £ 20mA.
** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 8ns) for I £ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Test Conditions
VIN = VSS to VCC
Min
-2
Max
2
Unit
mA
ILI
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
mA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL,
IOUT=0mA
10ns
12ns
15ns
20ns
-
75
70
68
65
30
5
mA
-
-
-
Standby Current
ISB
Min. Cycle, CS=VIH
-
mA
mA
ISB1
f=0MHz, CS ³ VCC-0.2V,
VIN³ VCC-0.2V or VIN£0.2V
Normal
L-ver.
-
-
0.5
0.4
-
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
V
V
IOH=-4mA
2.4
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
Test Conditions
VI/O=0V
MIN
Max
8
Unit
Input/Output Capacitance
Input Capacitance
CI/O
-
-
pF
pF
CIN
VIN=0V
6
* Capacitance is sampled and not 100% tested.
Revision 2.0
April 2000
- 3 -
PRELIMINARY
PRELIMINARY
CMOS SRAM
K6R1004V1C-C/C-L, K6R1004V1C-I/C-P
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
Preliminary
CCPCCCRCELIMINARY
Input Rise and Fall Times
3ns
1.5V
Input and Output timing Reference Levels
Output Loads
See below
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
Output Loads(A)
DOUT
+3.3V
RL = 50W
319W
VL = 1.5V
30pF*
DOUT
ZO = 50W
353W
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
K6R1004V1C-10 K6R1004V1C-12 K6R1004V1C-15 K6R1004V1C-20
Sym-
bol
Unit
Min
10
-
Max
Min
12
-
Max
Min
15
-
Max
Min
20
-
Max
Read Cycle Time
tRC
tAA
-
10
10
5
-
12
12
6
-
15
15
7
-
20
20
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address
Chip Selection to Power Up Time
Chip Selection to Power Down-
-
-
-
-
3
-
3
-
3
-
3
-
tOLZ
tHZ
0
-
0
-
0
-
0
-
0
5
0
6
0
7
0
9
tOHZ
tOH
tPU
tPD
0
5
0
6
0
7
0
9
3
-
3
-
3
-
3
-
0
-
0
-
0
-
0
-
-
10
-
12
-
15
-
20
* The above parameters are also guaranteed at industrial temperature range.
Revision 2.0
April 2000
- 4 -
PRELIMINARY
PRELIMINARY
K6R1004V1C-C/C-L, K6R1004V1C-I/C-P
CMOS SRAM
WRITE CYCLE*
K6R1004V1C-10
K6R1004V1C-12
K6R1004V1C-15
K6R1004V1C-20
Unit
Sym-
bol
Parameter
Min
10
7
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
5
-
-
-
12
-
15
-
20
-
-
-
-
-
-
-
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary
CCPCCCRCELIMINARY
Chip Select to End of Write
Address Set-up Time
8
0
-
-
-
-
-
-
6
-
-
-
9
0
-
-
10
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
7
8
9
-
10
10
20
0
7
8
9
-
10
0
12
0
15
0
-
-
Write to Output High-Z
0
0
0
7
-
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
5
6
7
8
0
0
0
-
0
tOW
3
3
3
-
3
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Valid Data
Data Out
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tCO
CS
tOHZ
tOH
tOE
OE
tOLZ
tLZ(4,5)
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
Revision 2.0
April 2000
- 5 -
PRELIMINARY
PRELIMINARY
CMOS SRAM
K6R1004V1C-C/C-L, K6R1004V1C-I/C-P
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
Preliminary
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
CCPCCCRCELIMINARY
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
tDH
High-Z
Data in
Data out
Valid Data
tOHZ(6)
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(9)
(10)
High-Z(8)
Data out
Revision 2.0
April 2000
- 6 -
PRELIMINARY
PRELIMINARY
CMOS SRAM
K6R1004V1C-C/C-L, K6R1004V1C-I/C-P
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
CS
Preliminary
CCPCCCRCELIMINARY
tAW
tWR(5)
tCW(3)
tWP(2)
tAS(4)
WE
tDH
tDW
High-Z
High-Z
High-Z
Data in
Data out
Valid Data
tLZ
tWHZ(6)
High-Z(8)
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS
WE
X
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
H
ISB, ISB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* X means Don¢t Care.
Revision 2.0
April 2000
- 7 -
PRELIMINARY
PRELIMINARY
CMOS SRAM
K6R1004V1C-C/C-L, K6R1004V1C-I/C-P
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
Parameter
VCC for Data Retention
Data Retention Current
Symbol
VDR
Test Condition
Min.
Typ.
Max.
Unit
V
CS³ VCC-0.2V
-
3.6
P2r.e0 liminary
VCC=3.0V, CCSC³ VCPC-C0.2CV CRCELIMINARY0.4
VIN³ VCC-0.2V or VIN£0.2V
IDR
-
-
mA
VCC=2.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
-
-
0.3
Data Retention Set-Up Time
Recovery Time
tSDR
tRDR
See Data Retention
Wave form(below)
0
5
-
-
-
-
ns
ms
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
VIH
VDR
CS³ VCC - 0.2V
CS
GND
Revision 2.0
April 2000
- 8 -
PRELIMINARY
PRELIMINARY
K6R1004V1C-C/C-L, K6R1004V1C-I/C-P
PACKAGE DIMENSIONS
CMOS SRAM
Units:millimeters/Inches
32-SOJ-400
Preliminary
CCPCCCRCELIMINARY
#32
#17
9.40 ±0.25
0.370 ±0.010
11.18 ±0.12
0.440 ±0.005
+0.10
-0.05
0.20
0.008 +0.004
#1
#16
-0.002
0.69
MIN
21.36
0.841
MAX
0.027
20.95 ±0.12
0.825 ±0.005
1.30
0.051
1.30
0.051
(
(
)
)
0.10
0.004
3.76
0.148
MAX
MAX
+0.10
-0.05
+0.10
-0.05
+0.004
-0.002
0.71
0.43
1.27
0.050
0.95
(
0.028 +0.004
)
0.017
0.0375
-0.002
Revision 2.0
April 2000
- 9 -
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