K6R1004V1D-KI080 [SAMSUNG]
Standard SRAM, 256KX4, 8ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, PLASTIC, SOJ-32;型号: | K6R1004V1D-KI080 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 256KX4, 8ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, PLASTIC, SOJ-32 静态存储器 光电二极管 内存集成电路 |
文件: | 总9页 (文件大小:192K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
PRELIMINARY
for AT&T
K6R1004V1D
CMOS SRAM
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev.No.
History
Draft Data
Remark
Rev. 0.0
Rev. 0.1
Rev. 0.2
Initial document.
Speed bin modify
Current modify
May. 11. 2001
June. 18. 2001
September. 9. 2001
Preliminary
Preliminary
Preliminary
Rev. 1.0
1. Final datasheet release
2. Delete 12ns speed bin.
3. Change Icc for Industrial mode.
Item
December. 18. 2001
Final
Previous
100mA
85mA
Current
90mA
75mA
8ns
ICC(Industrial)
10ns
Rev. 2.0
Rev. 3.0
1. Delete UB,LB releated timing diagram.
1. Add the Lead Free Package type.
June. 19. 2002
July. 26, 2004
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. 3.0
July 2004
- 1 -
PRELIMINARY
PRELIMINARY
for AT&T
K6R1004V1D
CMOS SRAM
1Mb Async. Fast SRAM Ordering Information
Org.
Part Number
VDD(V)
Speed ( ns )
PKG
Temp. & Power
K6R1004C1D-J(K)C(I) 10
K6R1004V1D-J(K)C(I) 08/10
K6R1008C1D-J(K,T,U)C(I) 10
5
3.3
5
10
8/10
10
J : 32-SOJ
256K x4
K: 32-SOJ(LF)
J : 32-SOJ
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
K : 32-SOJ(LF)
T : 32-TSOP2
U : 32-TSOP2(LF)
128K x8
64K x16
K6R1008V1D-J(K,T,U)C(I) 08/10
K6R1016C1D-J(K,T,U,E)C(I) 10
K6R1016V1D-J(K,T,U,E)C(I) 08/10
3.3
5
8/10
10
J : 44-SOJ
K : 44-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
E : 48-TBGA
3.3
8/10
Rev. 3.0
July 2004
- 2 -
PRELIMINARY
PRELIMINARY
for AT&T
K6R1004V1D
CMOS SRAM
256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 8,10ns(Max.)
• Low Power Dissipation
The K6R1004V1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits.
The K6R1004V1D uses 4 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using
SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1004V1D is packaged in a 400 mil 32-pin plastic SOJ.
Standby (TTL)
: 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating //K6R1004V1D-08: 80mA(Max.)
K6R1004V1D-10: 65mA(Max.)
Single 3.3 0.3V Power Supply
TTL Compatible Inputs and Outputs
Fully Static Operation
•
•
•
- No Clock or Refresh required
Three State Outputs
•
•
Center Power/Ground Pin Configuration
• Standard Pin Configuration :
K6R1004V1D-J : 32-SOJ-400
K6R1004V1D-K : 32-SOJ-400 (Lead-Free)
• Operating in Commercial and Industrial Temperature range.
PIN CONFIGURATION(Top View)
A17
A16
A15
A14
A13
OE
N.C
A0
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FUNCTIONAL BLOCK DIAGRAM
A1
A2
A3
Clk Gen.
Pre-Charge Circuit
CS
I/O1
Vcc
Vss
I/O4
Vss
Vcc
I/O3
A12
A11
A10
A9
A0
A1
A2
A3
A4
A5
A6
A7
A8
SOJ
Memory Array
512 Rows
I/O2 10
WE 11
A4 12
A5 13
A6 14
A7 15
N.C 16
512x4 Columns
A8
Data
I/O Circuit &
I/O1 ~ I/O4
N.C
Cont.
Column Select
CLK
Gen.
PIN FUNCTION
A9 A10 A11 A12 A13 A14 A15 A16 A17
Pin Name
A0 - A17
WE
Pin Function
Address Inputs
Write Enable
Chip Select
CS
WE
OE
CS
OE
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
I/O1 ~ I/O4
VCC
VSS
N.C
No Connection
Rev. 3.0
July 2004
- 3 -
PRELIMINARY
PRELIMINARY
for AT&T
K6R1004V1D
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
-0.5 to 4.6
-0.5 to 4.6
1
Unit
V
V
Pd
W
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Commercial
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter
Supply Voltage
Symbol
VCC
Min
3.0
0
Typ
Max
Unit
V
3.3
3.6
0
Ground
VSS
0
-
V
Input High Voltage
Input Low Voltage
VIH
2.0
-0.3*
VCC+0.3**
0.8
V
VIL
-
V
* VIL(Min) = -2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3 0.3V, unless otherwise specified)
Parameter
Symbol
ILI
Test Conditions
Min
-2
Max
2
Unit
µA
Input Leakage Current
Output Leakage Current
VIN=VSS to VCC
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
µA
Operating Current
Standby Current
ICC
Min. Cycle, 100% Duty
Com.
Ind.
8ns
10ns
8ns
-
-
-
-
-
-
80
65
90
75
20
5
mA
CS=VIL, VIN=VIH or VIL, IOUT=0mA
10ns
ISB
Min. Cycle, CS=VIH
mA
ISB1
f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
0.4
-
V
V
IOH=-4mA
2.4
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
CI/O
Test Conditions
VI/O=0V
TYP
Max
Unit
pF
Input/Output Capacitance
Input Capacitance
-
-
8
6
CIN
VIN=0V
pF
* Capacitance is sampled and not 100% tested.
Rev. 3.0
July 2004
- 4 -
PRELIMINARY
PRELIMINARY
for AT&T
K6R1004V1D
CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3 0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
Output Loads(A)
DOUT
+3.3V
RL = 50Ω
319Ω
VL = 1.5V
DOUT
30pF*
ZO = 50Ω
353Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
K6R1004V1D-08
K6R1004V1D-10
Parameter
Symbol
Unit
Min
Max
Min
10
-
Max
Read Cycle Time
tRC
tAA
8
-
-
8
8
4
-
-
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
-
-
3
0
0
0
3
0
-
3
-
tOLZ
tHZ
-
0
-
4
4
-
0
5
tOHZ
tOH
tPU
tPD
0
5
3
-
-
0
-
8
-
10
* The above parameters are also guaranteed at industrial temperature range.
Rev. 3.0
July 2004
- 5 -
PRELIMINARY
PRELIMINARY
for AT&T
K6R1004V1D
CMOS SRAM
WRITE CYCLE*
Parameter
K6R1004V1D-08
Max
K6R1004V1D-10
Symbol
Unit
Min
8
Min
10
7
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
5
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
6
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
6
7
6
7
8
10
0
0
Write to Output High-Z
0
0
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
4
5
0
0
tOW
3
3
* The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Valid Data
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tCO
tHZ(3,4,5)
CS
tOHZ
tDH
tOE
OE
tOLZ
tLZ(4,5)
Data out
High-Z
Valid Data
tPU
tPD
ICC
ISB
VCC
Current
50%
50%
Rev. 3.0
July 2004
- 6 -
PRELIMINARY
PRELIMINARY
for AT&T
K6R1004V1D
CMOS SRAM
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
tDH
High-Z
Data in
Data out
Valid Data
tOHZ(6)
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(9)
(10)
High-Z(8)
Data out
Rev. 3.0
July 2004
- 7 -
PRELIMINARY
PRELIMINARY
for AT&T
K6R1004V1D
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDH
tDW
High-Z
High-Z
Data in
Valid Data
tLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
H
X
ISB, ISB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* X means Don′t Care.
Rev. 3.0
July 2004
- 8 -
PRELIMINARY
PRELIMINARY
for AT&T
K6R1004V1D
CMOS SRAM
Units:millimeters/Inches
PACKAGE DIMENSIONS
32-SOJ-400
#32
#17
9.40 0.25
11.18 0.12
0.440 0.005
0.370 0.010
+0.10
0.20
-0.05
0.008 +0.004
#1
#16
-0.002
0.69
MIN
21.36
0.841
MAX
0.027
20.95 0.12
0.825 0.005
1.30
(
(
)
)
0.051
0.10
3.76
MAX
MAX
1.30
0.004
0.148
0.051
+0.10
-0.05
+0.10
0.71
0.43
0.017
-0.05
1.27
0.95
(
)
0.028 +0.004
+0.004
0.050
0.0375
-0.002
-0.002
Rev. 3.0
July 2004
- 9 -
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