K6R1008C1C- [SAMSUNG]
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.; 128Kx8位高速CMOS静态RAM （ 5V工作） 。工作在商用和工业温度范围。
| 型号： | K6R1008C1C- |
| 厂家： | 
SAMSUNG |
| 描述： | 128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges. |
| 文件： | 总9页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CMOS SRAM
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
Document Title
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev.No.
Rev. 0.0
Rev. 1.0
History
Draft Data
Aug. 5. 1998
Mar. 3. 1999
Remark
Preliminary
Final
Initial release with Preliminary.
Release to Final Data Sheet.
1.1. Delete Preliminary.
2.2. Added Data Retention Characteristics.
Rev. 2.0
Rev. 3.0
Add 10ns part.
Mar. 3. 2000
Final
Final
Delete 20ns speed bin
Sep. 24. 2001
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision 3.0
September 2001
- 1 -
PRELIMINARY
CMOS SRAM
128K x 8 Bit High-Speed CMOS Static RAM(5.0V Operating)
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10,12,15ns(Max.)
• Low Power Dissipation
The K6R1008C1C is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 131,072 words by 8 bits.
The K6R1008C1C uses 8 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG¢s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
Standby (TTL)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
: 30mA(Max.)
Operating K6R1008C1C-10 : 80mA(Max.)
K6R1008C1C-12 : 75mA(Max.)
K6R1008C1C-15 : 73mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention: L-ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
high-density
high-speed
system
applications.
The
K6R1008C1C is packaged in a 400mil 32-pin plastic SOJ or
TSOP2 forward.
ORDERING INFORMATION
K6R1008C1C-C10/C12/C15
K6R1008C1C-I10/I12/I15
Commercial Temp.
Industrial Temp.
K6R1008C1C-J : 32-SOJ-400
K6R1008C1C-T : 32-TSOP2-400CF
PIN CONFIGURATION(Top View)
A0
A1
1
2
3
4
5
6
7
8
9
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O8
26 I/O7
25 Vss
24 Vcc
23 I/O6
22 I/O5
21 A12
20 A11
19 A10
18 A9
17 A8
FUNCTIONAL BLOCK DIAGRAM
A2
A3
CS
I/O1
I/O2
Vcc
Vss
Clk Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A4
SOJ/
TSOP2
Memory Array
512 Rows
I/O3 10
I/O4 11
WE 12
A4 13
A5 14
A6 15
A7 16
256x8 Columns
A5
A6
A7
A8
Data
Cont.
I/O Circuit
Column Select
I/O1~I/O8
CLK
Gen.
PIN FUNCTION
A9 A10 A11 A12 A13 A14 A15 A16
Pin Name
A0 - A16
WE
Pin Function
Address Inputs
Write Enable
Chip Select
CS
WE
OE
CS
OE
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
I/O1 ~ I/O8
VCC
VSS
N.C
No Connection
Revision 3.0
September 2001
- 2 -
PRELIMINARY
CMOS SRAM
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
-0.5 to Vcc+0.5V
-0.5 to 7.0
1
Unit
V
V
Pd
W
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Commercial
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter
Min
Symbol
Typ
Max
Unit
V
Supply Voltage
VCC
4.5
5.0
5.5
Ground
VSS
0
0
-
0
VCC + 0.5***
0.8
V
V
Input High Voltage
Input Low Voltage
VIH
2.2
V
VIL
-0.5**
-
*
The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 8ns) for I £ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Test Conditions
VIN = VSS to VCC
Min
-2
Max
2
Unit
mA
ILI
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
mA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL,
IOUT=0mA
10ns
12ns
15ns
-
80
75
73
30
5
mA
-
-
Standby Current
ISB
Min. Cycle, CS=VIH
-
mA
mA
ISB1
f=0MHz, CS ³ VCC-0.2V,
VIN³ VCC-0.2V or VIN£0.2V
Normal
L-ver.
-
-
-
0.5
0.4
-
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
V
V
V
IOH=-4mA
IOH1=-0.1mA
2.4
-
VOH1**
3.95
* The above parameters are also guaranteed at industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
Test Conditions
VI/O=0V
MIN
Max
8
Unit
CI/O
-
-
pF
pF
CIN
VIN=0V
6
* Capacitance is sampled and not 100% tested.
Revision 3.0
September 2001
- 3 -
PRELIMINARY
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(B)
Output Loads(A)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
RL = 50W
DOUT
480W
VL = 1.5V
30pF*
DOUT
ZO = 50W
255W
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
K6R1008C1C-10
K6R1008C1C-12
K6R1008C1C-15
Symbol
Unit
Min
10
-
Max
Min
12
-
Max
Min
15
-
Max
Read Cycle Time
tRC
tAA
-
10
10
5
-
12
12
6
-
15
15
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
-
-
-
3
-
3
-
3
-
tOLZ
tHZ
0
-
0
-
0
-
0
5
0
6
0
7
tOHZ
tOH
tPU
tPD
0
5
0
6
0
7
3
-
3
-
3
-
0
-
0
-
0
-
-
10
-
12
-
15
* The above parameters are also guaranteed at industrial temperature range.
Revision 3.0
September 2001
- 4 -
PRELIMINARY
CMOS SRAM
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
WRITE CYCLE*
K6R1008C1C-10
K6R1008C1C-12
K6R1008C1C-15
Parameter
Symbol
Unit
Min
10
7
Max
Min
12
8
Max
Min
15
9
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
7
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
0
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
7
8
9
7
8
9
10
0
12
0
15
0
Write to Output High-Z
0
0
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
5
6
7
0
0
0
tOW
3
3
3
* The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Valid Data
Data Out
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tCO
CS
tOHZ
tOH
tOE
OE
tOLZ
tLZ(4,5)
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
Revision 3.0
September 2001
- 5 -
PRELIMINARY
CMOS SRAM
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
tDH
High-Z
Data in
Data out
Valid Data
tOHZ(6)
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tWR(5)
tAW
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
Data out
Revision 3.0
September 2001
- 6 -
PRELIMINARY
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP(2)
WE
tDH
tDW
High-Z
High-Z
High-Z
Data in
Data out
Data Valid
tLZ
tWHZ(6)
High-Z(8)
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS
WE
X
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
H
ISB, ISB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* X means Don¢t Care.
Revision 3.0
September 2001
- 7 -
PRELIMINARY
CMOS SRAM
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
Parameter
VCC for Data Retention
Data Retention Current
Symbol
VDR
Test Condition
CS³ VCC-0.2V
Min.
2.0
-
Typ.
Max.
5.5
Unit
-
-
V
IDR
VCC=3.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
0.4
mA
VCC=2.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
-
-
0.3
Data Retention Set-Up Time
Recovery Time
tSDR
tRDR
See Data Retention
Wave form(below)
0
5
-
-
-
-
ns
ms
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
VIH
VDR
CS³ VCC - 0.2V
CS
GND
Revision 3.0
September 2001
- 8 -
PRELIMINARY
CMOS SRAM
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
Units:millimeters/Inches
PACKAGE DIMENSIONS
32-SOJ-400
#32
#17
9.40 ±0.25
0.370 ±0.010
11.18 ±0.12
0.440 ±0.005
+0.10
-0.05
0.20
0.008 +0.004
#1
#16
-0.002
0.69
MIN
21.36
MAX
0.841
0.027
20.95 ±0.12
0.825 ±0.005
1.30
0.051
1.30
0.051
(
(
)
)
0.10
0.004
3.76
0.148
MAX
MAX
+0.10
-0.05
+0.10
-0.05
+0.004
-0.002
0.71
0.43
1.27
0.050
0.95
0.0375
0.028 +0.004
(
)
0.017
-0.002
32-TSOP2-400CF
0~8°
0.25
0.010
(
)
#32
#17
0.45 ~0.75
0.018 ~ 0.030
11.76 ±0.20
0.463 ±0.008
0.50
0.020
(
)
#1
#16
+0.10
-0.05
+0.004
-0.002
0.15
21.35
0.841
MAX
0.006
20.95 ±0.10
0.825 ±0.004
1.00 ±0.10
0.10 MAX
0.004 MAX
1.20
0.047
MAX
0.039 ±0.004
1.27
0.050
0.95
0.037
0.05
0.40 ±0.10
0.016 ±0.004
(
)
MIN
0.002
Revision 3.0
September 2001
- 9 -
相关型号：
K6R1008C1C-C10
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1008C1C-C12
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1008C1C-C15
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1008C1C-I10
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1008C1C-I12
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1008C1C-I15
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1008C1C-J10
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1008C1C-J12
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
K6R1008C1C-J15
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
SAMSUNG
©2020 ICPDF网 联系我们和版权申明