K6R1016V1D-EC080 [SAMSUNG]

Standard SRAM, 64KX16, 8ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TBGA-48;


型号：	K6R1016V1D-EC080
厂家：	SAMSUNG
描述：	Standard SRAM, 64KX16, 8ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TBGA-48 静态存储器
文件：	总11页 (文件大小：302K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

for AT&T

CMOS SRAM

K6R1016V1D

Document Title

64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)

Operated at Commercial and Industrial Temperature Ranges.

Revision History

Rev.No.

History

Draft Data

Remark

Rev. 0.0

Rev. 0.1

Rev. 0.2

Initial document.

Speed bin modify

Current modify

May. 11. 2001

June. 18. 2001

September. 9. 2001

Preliminary

Rev. 1.0

1. Delete 12ns speed bin.

2. Change Icc for Industrial mode.

Item

December. 18. 2001

Final

100mA

85mA

Current

90mA

75mA

8ns

ICC(Industrial)

10ns

Rev. 2.0

Rev. 3.0

Rev. 4.0

1. Add tBA,tBLZ,tBHZ,tBW AC parematers.

1. Correct read cycle timing diagram(2).

1. Add the Lead Free Package type.

February. 14. 2002

June. 19. 2002

July. 26, 2004

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,

please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev. 4.0

July 2004

- 1 -

for AT&T

CMOS SRAM

K6R1016V1D

1Mb Async. Fast SRAM Ordering Information

Org.

Part Number

VDD(V)

Speed ( ns )

PKG

Temp. & Power

K6R1004C1D-J(K)C(I) 10

K6R1004V1D-J(K)C(I) 08/10

K6R1008C1D-J(K,T,U)C(I) 10

3.3

8/10

J : 32-SOJ

256K x4

K: 32-SOJ(LF)

J : 32-SOJ

C : Commercial Temperature

,Normal Power Range

I : Industrial Temperature

,Normal Power Range

K : 32-SOJ(LF)

T : 32-TSOP2

U : 32-TSOP2(LF)

128K x8

64K x16

K6R1008V1D-J(K,T,U)C(I) 08/10

K6R1016C1D-J(K,T,U,E)C(I) 10

K6R1016V1D-J(K,T,U,E)C(I) 08/10

3.3

8/10

J : 44-SOJ

K : 44-SOJ(LF)

T : 44-TSOP2

U : 44-TSOP2(LF)

E : 48-TBGA

3.3

8/10

Rev. 4.0

July 2004

- 2 -

for AT&T

CMOS SRAM

K6R1016V1D

64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)

FEATURES

GENERAL DESCRIPTION

• Fast Access Time 8,10ns(Max.)

• Low Power Dissipation

The K6R1016V1D is a 1,048,576-bit high-speed Static Random

Access Memory organized as 65,536 words by 16 bits.

The K6R1016V1D uses 16 common input and output lines and

has at output enable pin which operates faster than address

access time at read cycle. Also it allows that lower and upper

byte access by data byte control (UB, LB). The device is

fabricated using SAMSUNG′s advanced CMOS process and

designed for high-speed circuit technology. It is particularly well

suited for use in high-density high-speed system applications.

The K6R1016V1D is packaged in a 400mil 44-pin plastic SOJ

or TSOP2 forward or 48-TBGA.

Standby (TTL)

: 20mA(Max.)

(CMOS) : 5mA(Max.)

Operating K6R1016V1D- 08: 80mA(Max.)

K6R1016V1D-10: 65mA(Max.)

• Single 3.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16

• Standard Pin Configuration:

K6R1016V1D-J: 44-SOJ-400

K6R1016V1D-K: 44-SOJ-400 (Lead-Free)

K6R1016V1D-T: 44-TSOP2-400BF

K6R1016V1D-U: 44-TSOP2-400BF (Lead-Free)

K6R1016V1D-E: 48-TBGA ( 6.0mm X 7.0mm )

with 0.75mm ball pitch

• Operating in Commercial and Industrial Temperature range.

FUNCTIONAL BLOCK DIAGRAM

Clk Gen.

Pre-Charge Circuit

Memory Array

512 Rows

128x16 Columns

PIN FUNCTION

Pin Name

A0 - A15

Pin Function

Address Inputs

Data

I/O Circuit &

I/O1~I/O8

I/O9~I/O16

Cont.

Column Select

Write Enable

Data

Cont.

Chip Select

Gen.

Output Enable

CLK

A9 A10 A11 A12 A13 A14 A15

Lower-byte Control(I/O1~I/O8)

Upper-byte Control(I/O9~I/O16)

Data Inputs/Outputs

Power(+3.3V)

I/O1 ~ I/O16

VCC

VSS

Ground

N.C

No Connection

Rev. 4.0

July 2004

- 3 -

for AT&T

CMOS SRAM

K6R1016V1D

PIN CONFIGURATION(TOP VIEW)

44 A15

43 A14

42 A13

41 OE

40 UB

N.C

I/O9

I/O10

Vcc

I/O1

I/O2

I/O3

I/O4 10

Vcc 11

Vss 12

I/O5 13

I/O6 14

I/O7 15

I/O8 16

WE 17

A5 18

39 LB

I/O2

Vss

I/O3

I/O4

I/O5

I/O6

N.C

I/O11

I/O12

I/O13

I/O14

38 I/O16

37 I/O15

36 I/O14

35 I/O13

34 Vss

33 Vcc

32 I/O12

31 I/O11

30 I/O10

29 I/O9

28 N.C

27 A12

26 A11

25 A10

24 A9

N.C

A14

A12

SOJ/

TSOP2

Vcc

I/O7

I/O8

N.C

A15

A13

A10

Vss

I/O15

I/O16

N.C

A11

A6 19

A7 20

A8 21

N.C 22

48-TBGA ( Top View )

23 N.C

ABSOLUTE MAXIMUM RATINGS*

Parameter

Voltage on Any Pin Relative to VSS

Voltage on VCC Supply Relative to VSS

Power Dissipation

Symbol

VIN, VOUT

VCC

Rating

Unit

-0.5 to 4.6

Storage Temperature

TSTG

-65 to 150

0 to 70

°C

Commercial

Operating Temperature

Industrial

-40 to 85

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (TA= 0 to 70°C)

Parameter

Supply Voltage

Symbol

Min

3.0

Typ

Max

3.6

Unit

3.3

VCC

Ground

VSS

VCC+0.3⁽¹⁾

Input High Voltage

Input Low Voltage

VIH

2.0

-0.3⁽²⁾

VIL

0.8

(1) VIH(Max) = VCC + 2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA

(2) V^IL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.

Rev. 4.0

July 2004

- 4 -

for AT&T

CMOS SRAM

K6R1016V1D

DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3 0.3V, unless otherwise specified)

Parameter

Symbol

ILI

Test Conditions

Min

-2

Max

Unit

µA

Input Leakage Current

Output Leakage Current

VIN=VSS to VCC

ILO

CS=VIH or OE=VIH or WE=VIL

VOUT=VSS to VCC

-2

µA

Operating Current

Standby Current

ICC

Min. Cycle, 100% Duty

Com.

Ind.

8ns

10ns

8ns

CS=VIL, VIN=VIH or VIL, IOUT=0mA

10ns

ISB

Min. Cycle, CS=VIH

ISB1

f=0MHz, CS≥VCC-0.2V,

VIN≥VCC-0.2V or VIN≤0.2V

Output Low Voltage Level

Output High Voltage Level

VOL

VOH

IOL=8mA

0.4

IOH=-4mA

2.4

* The above parameters are also guaranteed at industrial temperature range.

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item

Symbol

CI/O

Test Conditions

VI/O=0V

TYP

Max

Unit

Input/Output Capacitance

Input Capacitance

CIN

VIN=0V

* Capacitance is sampled and not 100% tested.

AC CHARACTERISTICS(TA=0 to 70°C, Vcc=3.3V+0.3V/-0.15V, unless otherwise noted.)

TEST CONDITIONS*

Parameter

Value

0V to 3V

3ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output timing Reference Levels

Output Loads

1.5V

See below

* The above test conditions are also applied at industrial temperature range.

Output Loads(B)

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

Output Loads(A)

+3.3V

RL = 50Ω

DOUT

319Ω

VL = 1.5V

30pF*

DOUT

ZO = 50Ω

353Ω

5pF*

* Capacitive Load consists of all components of the

test environment.

* Including Scope and Jig Capacitance

Rev. 4.0

July 2004

- 5 -

for AT&T

CMOS SRAM

K6R1016V1D

READ CYCLE*

K6R1016V1D-08

K6R1016V1D-10

Parameter

Symbol

Unit

Min

Max

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

tBA

Output Enable to Valid Output

UB, LB Access Time

Chip Enable to Low-Z Output

Output Enable to Low-Z Output

UB, LB Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

UB, LB Disable to High-Z Output

Output Hold from Address Change

Chip Selection to Power Up Time

Chip Selection to Power DownTime

tLZ

tOLZ

tBLZ

tHZ

tOHZ

tBHZ

tOH

tPU

tPD

* The above parameters are also guaranteed at industrial temperature range.

WRITE CYCLE*

K6R1016V1D-08

K6R1016V1D-10

Min Max

Parameter

Symbol

Unit

Min

Max

Write Cycle Time

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width(OE High)

Write Pulse Width(OE Low)

UB, LB Valid to End of Write

Write Recovery Time

tAW

tWP

tWP1

tBW

tWR

tWHZ

tDW

tDH

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End of Write to Output Low-Z

tOW

* The above parameters are also guaranteed at industrial temperature range.

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)

tRC

Address

tAA

tOH

Valid Data

Data Out

Previous Valid Data

Rev. 4.0

July 2004

- 6 -

for AT&T

CMOS SRAM

K6R1016V1D

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tAA

tCO

tHZ(3,4,5)

tBHZ(3,4,5)

tBA

UB, LB

tBLZ(4,5)

tOHZ

tDH

tOE

tOLZ

tLZ(4,5)

Data out

High-Z

Valid Data

tPU

tPD

ICC

ISB

VCC

Current

50%

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. t^HZand tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

V^OLlevels.

4. At any given temperature and voltage condition, t^HZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock)

tWC

tAW

Address

tWR(5)

tCW(3)

tBW

UB, LB

tAS(4)

tWP(2)

tDW

tDH

High-Z

Data in

Valid Data

tOHZ(6)

Data out

Rev. 4.0

July 2004

- 7 -

for AT&T

CMOS SRAM

K6R1016V1D

TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tWP1(2)

tAS(4)

tDW

tDH

High-Z

Valid Data

Data in

(9)

(10)

tWHZ(6)

tOW

High-Z

Data out

TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tAS(4)

tWP(2)

tDH

tDW

High-Z

Data in

Valid Data

tLZ

tWHZ(6)

High-Z(8)

High-Z

Data out

Rev. 4.0

July 2004

- 8 -

for AT&T

CMOS SRAM

K6R1016V1D

TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tAS(4)

tWP(2)

tDH

tDW

High-Z

Data in

Valid Data

tBLZ

tWHZ(6)

High-Z(8)

High-Z

Data out

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE

going low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write

to the end of write.

3. t^CWis measured from the later of CS going low to end of write.

4. t^ASis measured from the address valid to the beginning of write.

5. t^WRis measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

FUNCTIONAL DESCRIPTION

I/O Pin

Mode

Supply Current

I/O1~I/O8

I/O9~I/O16

Not Select

High-Z

ISB, ISB1

ICC

Output Disable

High-Z

DOUT

High-Z

DOUT

DIN

High-Z

DOUT

High-Z

DIN

Read

Write

ICC

High-Z

DIN

* X means Don′t Care.

Rev. 4.0

July 2004

- 9 -

for AT&T

CMOS SRAM

K6R1016V1D

Units:millimeters/Inches

PACKAGE DIMENSIONS

44-SOJ-400

#44

#23

9.40 0.25

11.18 0.12

0.370 0.010

0.440 0.005

+0.10

0.20

-0.05

0.008 ^+0.004

-0.002

#22

28.98

1.141

0.69

MIN

MAX

0.027

25.58 0.12

1.125 0.005

1.19

)

(

0.047

3.76

1.27

MAX

0.148

(

)

0.050

0.10

MAX

0.004

+0.10

0.43

-0.05

+0.10

-0.05

0.71

0.017 ^+0.004

0.95

1.27

-0.002

(

)

0.028 ^+0.004

0.0375

0.050

-0.002

44-TSOP2-400BF

Units:millimeters/Inches

0~8°

0.25

TYP

0.010

#23

#44

0.45 ~0.75

0.018 ~ 0.030

11.76 0.20

0.463 0.008

0.50

(

)

0.020

#22

18.81

MAX

+ 0.075

- 0.035

+ 0.003

- 0.001

0.125

0.005

0.741

18.41 0.10

0.725 0.004

1.00 0.10

1.20

0.047

MAX

0.039 0.004

0.10

MAX

+0.10

−0.05

0.05

0.004

0.30

0.012

MIN

0.002

0.80

0.805

(

)

+0.004

−0.002

0.0315

0.032

Rev. 4.0

July 2004

- 10

for AT&T

CMOS SRAM

K6R1016V1D

Unit: millimeters

PACKAGE DIMENSION

48 TAPE BALL GRID ARRAY(0.75mm ball pitch)

Top View

Bottom View

#A1

B/2

Detail A

Side View

Min

Typ

0.75

6.00

3.75

7.00

5.25

0.45

0.90

0.55

0.35

Max

5.90

Notes.

6.10

1. Bump counts: 48(8 row x 6 column)

2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

4. Typ: Typical

5. Y is coplanarity: 0.08(Max)

6.90

7.10

0.40

0.80

0.50

1.00

0.30

0.40

0.08

Rev. 4.0

July 2004

- 11

K6R1016V1D-EC080 [SAMSUNG]

相关型号：

K6R1016V1D-EC10

K6R1016V1D-EC100

K6R1016V1D-EI08

K6R1016V1D-EI08/10

K6R1016V1D-EI080

K6R1016V1D-EI10

K6R1016V1D-EI100

K6R1016V1D-FI12

K6R1016V1D-FI12T

K6R1016V1D-JC08

K6R1016V1D-JC08/10

K6R1016V1D-JC080