K6R3024V1D-HC090 [SAMSUNG]
SRAM Module, 128KX24, 9ns, CMOS, PBGA119, 14 X 22 MM, BGA-119;
| 型号： | K6R3024V1D-HC090 |
| 厂家： | 
SAMSUNG |
| 描述： | SRAM Module, 128KX24, 9ns, CMOS, PBGA119, 14 X 22 MM, BGA-119 静态存储器 |
| 文件： | 总9页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
for AT&T
CMOS SRAM
K6R3024V1D
Document Title
128Kx24 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev.No.
History
Remark
Draft Data
Rev. 0.0
Rev. 0.1
Design-In Specification
Pin Configurations Modified ( page 2 )
Add Timing Diagram page 6 ~ 8 )
Design-In
Preliminary
Dec. 05. 2000
Mar. 07. 2001
Rev. 0.2
Rev. 0.3
Modified Read Cycle Timing(2)
1) Version change from M to D
Preliminary
Preliminary
April. 04.2001
June. 23.2001
2) Cin from 20 to 15 pF
3) Icc from 300 to 170mA for 9ns products
from 270 to 150mA for 10ns products
from 240 to 130mA for 12ns products
4) Isb ( TTL ) from 120 to 40 mA for all products
( CMOS ) from 30 to 15 mA for all products
5) Part number change from -9 to -09 for 9ns products
Change write parameter( tDW) from 6ns to 5ns at -10
Final Specification Release
Rev. 0.4
Rev. 1.0
Preliminary
Final
Oct. 31. 2001
Dec. 19. 2001
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision 1.0
December 2001
- 1 -
for AT&T
CMOS SRAM
K6R3024V1D
128K x 24 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
• Fast Access Time 9,10,12ns
• Power Dissipation
Standby (TTL)
(CMOS) : 15mA(Max.)
Operating K6R3024V1D-09 : 170mA(Max.)
K6R3024V1D-10 : 150mA(Max.)
K6R3024V1D-12 : 130mA(Max.)
Single 3.3V Power Supply
GENERAL DESCRIPTION
The K6R3024V1D is a 3,145,728-bit high-speed Static Random
Access Memory organized as 131,072 words by 24 bits. The
K6R3024V1D uses 24 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNGs’
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R3024V1D is a three
megabit static RAM constructed on an multilayer laminate sub-
strate using three 3.3V, 128K x 8 static RAMS encapsulated in a
Ball Grid Array(BGA).
: 40mA(Max.)
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm)
• Operating in Commercial and Industrial Temperature range.
PIN FUNCTION
Pin Name
A0 - A16
WE
Pin Function
Addresses Inputs
FUNCTIONAL BLOCK DIAGRAM
17
A0-16
Write Enable
Chip Select
CS1
CS2
128K x 8 128K x 8 128K x 8
CS1,CS2,CS3
OE
CS3
SRAM
SRAM
SRAM
Output Enable
Data Inputs/Outputs
Power(+3.3v)
Ground
WE
OE
I/O0 ~ I/O23
VCC
8
8
8
I/O0-7
I/O8-15
I/O16-23
Vss
ORDERING INFORMATION
NC
No Connection
K6R3024V1D-HC09/HC10/HC12
K6R3024V1D-HI09/HI10/HI12
Commercial Temp.
Industrial Temp.
PIN CONFIGURATIONS(TOP VIEW)
K6R3024V1D
1
2
3
4
5
6
7
A
B
C
D
E
F
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
A
A
A
A
A
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
A
A
CS1
NC
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
WE
OE
A
A
NC
VCC
Vss
VCC
Vss
VCC
Vss
VCC
Vss
VCC
Vss
VCC
NC
A
CS2
Vss
VCC
Vss
VCC
Vss
VCC
Vss
VCC
Vss
VCC
Vss
NC
A
CS3
Vss
VCC
Vss
VCC
Vss
VCC
Vss
VCC
Vss
VCC
Vss
NC
A
NC
VCC
Vss
VCC
Vss
VCC
Vss
VCC
Vss
VCC
Vss
VCC
NC
A
G
H
J
K
L
M
N
P
R
T
U
A
A
A
A
Revision 1.0
December 2001
- 2 -
for AT&T
CMOS SRAM
K6R3024V1D
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
VIN, VOUT
VCC
Rating
-0.5 to 4.6
-0.5 to 4.6
2
Unit
V
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
V
Pd
W
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Commercial
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
CS2
CS1
H
X
CS3
X
OE
X
WE
X
Mode
Standby
I/O
Power
Standby
Standby
Standby
Active
X
High-Z
High-Z
High-Z
DATAOUT
DATAIN
High-Z
L
X
X
X
Standby
Standby
Read
X
X
H
X
X
L
H
L
L
H
L
H
L
X
L
Write
Active
L
H
L
H
H
Outputs Disabled
Active
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter
Supply Voltage
Symbol
Min
3.0
Typ
Max
3.6
Unit
V
3.3
VCC
VIH
Input High Voltage
Input Low Voltage
2.0
-
-
V
VCC+0.3***
0.8
V
VIL
-0.3**
*
The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 8ns) for I £ 20mA.
Revision 1.0
December 2001
- 3 -
for AT&T
CMOS SRAM
K6R3024V1D
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Min
Max
Parameter
Symbol
Test Conditions
Unit
Input Leakage Current
ILI
VIN=Vss to VCC
-
6
mA
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
Output Leakage Current
Operating Current
ILO
ICC
-
2
mA
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL,
IOUT=0mA
-09
-10
-12
-09
-10
-12
-09
-10
-12
-
170
150
130
40
40
40
15
15
15
0.4
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
-
-
Standby Current
ISB
Min. Cycle, CS=VIH
-
-
-
ISB1
f=0MHz, CS ³ VCC-0.2V,
VIN³ VCC-0.2V or VIN£0.2V
-
-
-
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
IOH=-4mA
2.4
V
* The above parameters are also guaranteed at industrial temperature range.
* CS represents CS1 , CS2 and CS3 in this data sheet. CS2 as of opposite polarity to CS1 and CS3.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
Test Conditions
VI/O=0V
MIN
Max
8
Unit
Input/Output Capacitance
Input Capacitance
CI/O
-
-
pF
pF
CIN
VIN=0V
15
* Capacitance is sampled and not 100% tested
AC TEST CONDITIONS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Value
Input Pulse Levels
0V to 3.0V
3ns
Input Rise and Fall Times
Input and output Timing Reference Levels
Output Load
1.5V
See Below
* The above parameters are also guaranteed at industrial temperature range.
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+3.3V
RL = 50W
DOUT
319W
VL = 1.5V
30pF*
DOUT
ZO = 50W
216W
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
Revision 1.0
December 2001
- 4 -
for AT&T
CMOS SRAM
K6R3024V1D
READ CYCLE*
Parameter
K6R3024V1D-09
K6R3024V1D-10
K6R3024V1D-12
Unit
Symbol
Min
9
-
Max
Min
10
-
Max
Min
12
-
Max
Read Cycle Time
tRC
tAA
-
9
9
4
-
-
10
10
5
-
12
12
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power DownTime
-
-
-
3
0
0
0
3
0
-
3
-
3
-
tOLZ
tHZ
-
0
-
0
-
4
5
-
0
5
0
6
tOHZ
tOH
tPU
tPD
0
6
0
7
3
-
3
-
-
0
-
0
-
9
-
10
-
12
WRITE CYCLE*
Parameter
K6R3024V1D-09
K6R3024V1D-10
K6R3024V1D-12
Symbol
Unit
Min
9
Max
Min
10
7
Max
Min
12
8
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
5
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
7
0
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
7
7
8
7
7
8
9
9
10
0
0
0
Write to Output High-Z
0
0
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
5
5
7
0
0
0
tOW
3
3
3
* This parameter is guaranteed by design but not tested.
These specifications are for the individual K6R3024V1D Static RAMs.
Revision 1.0
December 2001
- 5 -
for AT&T
CMOS SRAM
K6R3024V1D
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Valid Data
Data Out
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tOHZ
tCO
CS
tOE
OE
tOLZ
tLZ(4,5)
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
9. CS represents CS1 , CS2 and CS3 in this data sheet. CS2 as of opposite polarity to CS1 and CS3.
Revision 1.0
December 2001
- 6 -
for AT&T
CMOS SRAM
K6R3024V1D
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
OE
tWR(5)
tAW
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
tDH
High-Z
Data in
Valid Data
tOHZ(6)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tWR(5)
tAW
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
Data out
Revision 1.0
December 2001
- 7 -
for AT&T
CMOS SRAM
K6R3024V1D
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP(2)
WE
tDH
tDW
High-Z
High-Z
High-Z
Data in
Data out
Data Valid
tLZ
tWHZ(6)
High-Z(8)
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
11. CS represents CS1 , CS2 and CS3 in this data sheet. CS2 as of opposite polarity to CS1 and CS3.
Revision 1.0
December 2001
- 8 -
for AT&T
CMOS SRAM
K6R3024V1D
119 BGA PACKAGE DIMENSIONS
14.00±0.10
1.27
1.27
22.00±0.10
Indicator of
Ball(1A) Location
20.50±0.10
C0.70
C1.00
0.750±0.15
1.50REF
0.60±0.10
0.60±0.10
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
12.50±0.10
Revision 1.0
December 2001
- 9 -
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