K6R4004C1D-JC15 [SAMSUNG]
Standard SRAM, 1MX4, 15ns, CMOS, PDSO32;
| 型号： | K6R4004C1D-JC15 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 1MX4, 15ns, CMOS, PDSO32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
PRELIMINARY
CMOS SRAM
K6R4004C1D-C/D-I/D-P
Document Title
1Mx4 Bit High Speed Static RAM(5.0V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev No.
History
Draft Data
September. 7. 2001
Remark
Rev. 0.0
Initial release with Preliminary.
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev 0.0
- 1 -
September 2001
Preliminary
PRELIMINARY
CMOS SRAM
K6R4004C1D-C/D-I/D-P
1M x 4 Bit (with OE)High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10,12,15ns(Max.)
• Low Power Dissipation
Standby (TTL) : 30mA(Max.)
(CMOS) : 10mA(Max.)
Operating K6R4004C1D-10 : 90mA(Max.)
K6R4004C1D-12 : 80mA(Max.)
K6R4004C1D-15 : 70mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
GENERAL DESCRIPTION
The K6R4004C1D is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
K6R4004C1D uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG¢s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R4004C1D is packaged
in a 400 mil 32-pin plastic SOJ.
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention( Idr=1.5mA)
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4004C1D-J : 32-SOJ-400
PIN CONFIGURATION(Top View)
A19
A18
A17
A16
A15
OE
I/O4
Vss
Vcc
I/O3
A14
A13
A12
A11
A10
N.C
A0
A1
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ORDERING INFORMATION
A2
K6R4004C1D-C10/C12/C15
K6R4004C1D-I10/I12/I15
Commercial Temp.
Industrial Temp.
A3
A4
CS
I/O1
Vcc
Vss
FUNCTIONAL BLOCK DIAGRAM
SOJ
Clk Gen.
Pre-Charge Circuit
I/O2 10
WE 11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A5
A6
A7
A8
A9
12
13
14
15
16
Memory Array
1024 Rows
1024 x 4 Columns
Data
Cont.
I/O Circuit
Column Select
I/O1~I/O4
PIN FUNCTION
Pin Name
A0 - A19
WE
Pin Function
CLK
Gen.
Address Inputs
Write Enable
Chip Select
A10
A12
A11 A13
A14
A15
A16
A18
A17
A19
CS
OE
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
CS
WE
OE
I/O1 ~ I/O4
VCC
VSS
N.C
No Connection
Rev 0.0
September 2001
- 2 -
Preliminary
PRELIMINARY
CMOS SRAM
K6R4004C1D-C/D-I/D-P
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
-0.5 to VCC+0.5
-0.5 to 7.0
1.0
Unit
V
V
PD
W
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Commercial
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter
Symbol
Min
4.5
0
Typ
Max
Unit
V
Supply Voltage
Ground
VCC
5.0
5.5
0
VSS
VIH
0
-
V
Input High Voltage
Input Low Voltage
2.2
-0.5*
VCC+0.5**
0.8
V
VIL
-
V
*
The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 8ns) for I £ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
Output Leakage Current
ILI
VIN=VSS to VCC
-2
2
2
mA
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
mA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL, IOUT=0mA
Com.
Ind.
10ns
12ns
15ns
10ns
12ns
15ns
-
-
-
-
-
-
-
-
90
80
mA
70
115
100
85
Standby Current
ISB
Min. Cycle, CS=VIH
30
mA
ISB1
f=0MHz, CS³ VCC-0.2V,
10
VIN³ VCC-0.2V or VIN£0.2V
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
0.4
-
V
V
IOH=-4mA
2.4
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
CI/O
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
Input Capacitance
VI/O=0V
VIN=0V
-
-
8
6
pF
pF
CIN
* Capacitance is sampled and not 100% tested.
Rev 0.0
September 2001
- 3 -
Preliminary
PRELIMINARY
CMOS SRAM
K6R4004C1D-C/D-I/D-P
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
0V to 3V
3ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(B)
Output Loads(A)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
RL = 50W
DOUT
480W
VL = 1.5V
DOUT
30pF*
ZO = 50W
255W
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
K6R4004C1D-10
K6R4004C1D-12
K6R4004C1D-15
Parameter
Symbol
Unit
Min
10
-
Max
Min
12
-
Max
Min
15
-
Max
Read Cycle Time
tRC
tAA
-
10
10
5
-
12
12
6
-
15
15
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power Down-
-
-
-
-
5
-
6
-
7
tOLZ
tHZ
3
-
3
-
3
-
0
-
0
-
0
-
tOHZ
tOH
tPU
0
-
0
-
0
-
0
5
0
6
0
7
0
5
0
6
0
7
tPD
0
5
0
6
0
7
* The above parameters are also guaranteed at industrial temperature range.
Rev 0.0
- 4 -
September 2001
Preliminary
PRELIMINARY
CMOS SRAM
K6R4004C1D-C/D-I/D-P
WRITE CYCLE*
K6R4004C1D-10
Min Max
10
K6R4004C1D-12
Min Max
12
K6R4004C1D-15
Unit
Parameter
Symbol
Min
Max
Write Cycle Time
tWC
tCW
tAS
-
-
15
10
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
7
0
-
-
-
-
-
-
-
5
-
-
8
0
-
-
-
-
-
-
-
6
-
-
-
Address Valid to End of
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
7
8
10
10
15
10
0
-
7
8
-
10
7
12
8
-
-
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
0
0
-
0
0
0
7
-
5
6
7
tOW
0
0
0
-
* The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Previous Valid Data
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tCO
CS
tOHZ
tOH
tOE
OE
tOLZ
tLZ(4,5)
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
Rev 0.0
- 5 -
September 2001
Preliminary
PRELIMINARY
CMOS SRAM
K6R4004C1D-C/D-I/D-P
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
OE
tWR(5)
tAW
tCW(3)
CS
tAS(4)
tWP(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tOHZ(6)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(9)
(10)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP(2)
WE
tDW
tDH
High-Z
High-Z
Data in
Valid Data
tLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
Rev 0.0
- 6 -
September 2001
Preliminary
PRELIMINARY
CMOS SRAM
K6R4004C1D-C/D-I/D-P
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS andWE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS
WE
X
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
H
ISB, ISB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* X means Don¢t Care.
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
Parameter
VCC for Data Retention
Data Retention Current
Symbol
VDR
Test Condition
CS ³ VCC - 0.2V
VCC=3.0V, CS ³ VCC - 0.2V
Min.
2.0
-
Typ.
Max.
3.6
Unit
-
-
V
IDR
1.5
mA
VIN ³ VCC - 0.2V or VIN£0.2V
VCC=2.0V, CS ³ VCC - 0.2V
VIN³ VCC - 0.2V or VIN£0.2V
-
-
1.0
Data Retention Set-Up Time
Recovery Time
tSDR
tRDR
See Data Retention
Wave form(below)
0
5
-
-
-
-
ns
ms
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
VIH
VDR
CS³ VCC - 0.2V
CS
GND
Rev 0.0
- 7 -
September 2001
Preliminary
PRELIMINARY
CMOS SRAM
K6R4004C1D-C/D-I/D-P
PACKAGE DIMENSIONS
Units:millimeters/Inches
32-SOJ-400
#32
#17
9.40 ± 0.25
0.370 ± 0.010
11.18 ± 0.12
0.440 ± 0.005
+0.10
-0.05
0.20
+0.004
-0.002
#1
#16
0.008
0.69
MIN
21.36
0.841
MAX
0.027
20.95± 0.12
0.825 ± 0.005
1.30
0.051
1.30
0.051
(
(
)
)
0.10
0.004
3.76
0.148
MAX
MAX
+0.10
+0.10
0.71
-0.05
0.43
-0.05
1.27
0.050
0.95
0.0375
0.028 +0.004
(
)
+0.004
-0.002
0.017
-0.002
Rev 0.0
September 2001
- 8 -
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