K6R4008V1C-P [SAMSUNG]

512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges.; 512Kx8位高速静态RAM （ 3.3V工作）。工作在商用和工业温度范围。


型号：	K6R4008V1C-P
厂家：	SAMSUNG
描述：	512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. 512Kx8位高速静态RAM （ 3.3V工作）。工作在商用和工业温度范围。
文件：	总9页 (文件大小：139K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

CMOS SRAM

K6R4008V1C-C/C-L, K6R4008V1C-I/C-P

3Document Title

512Kx8 Bit High Speed Static RAM(3.3V Operating).

Operated at Commercial and Industrial Temperature Ranges.

Revision History

RevNo.

Rev. 0.0

Rev. 1.0

History

Remark

Draft Data

Initial release with Preliminary.

Preliminary

Feb. 12. 1999

Mar. 29. 1999

1.1 Removed Low power Version.

1.2 Removed Data Retention Characteristics.

1.3 Changed ISB1 to 20mA

Rev. 2.0

Rev. 3.0

Relax D.C parameters.

Preliminary

Aug. 19. 1999

Mar. 27. 2000

Item

160mA

155mA

150mA

Current

195mA

190mA

185mA

12ns

15ns

20ns

ICC

Final

3.1 Delete Preliminary

3.2 Update D.C parameters and 10ns part.

Current

ICC

195mA

190mA

185mA

Isb

Isb1

ICC

Isb

Isb1

10ns

12ns

15ns

20ns

155mA

145mA

135mA

125mA

70mA

20mA

60mA

10mA

Add Low Power-Ver.

Delete 20ns speed bin

Rev. 4.0

Rev. 5.0

Final

Apr. 24. 2000

Sep. 24. 2001

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev 5.0

September 2001

- 1 -

PRELIMINARY

CMOS SRAM

K6R4008V1C-C/C-L, K6R4008V1C-I/C-P

512K x 8 Bit High-Speed CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

• Fast Access Time 10,12,15ns(Max.)

• Low Power Dissipation

The K6R4008V1C is a 4,194,304-bit high-speed Static Random

Access Memory organized as 524,288 words by 8 bits. The

K6R4008V1C uses 8 common input and output lines and has an

output enable pin which operates faster than address access

time at read cycle. The device is fabricated using SAMSUNG¢s

advanced CMOS process and designed for high-speed circuit

technology. It is particularly well suited for use in high-density

high-speed system applications. The K6R4008V1C is packaged

in a 400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II.

Standby (TTL)

(CMOS) : 10mA(Max.)

1.2mA(Max.) L-Ver. only

: 60mA(Max.)

Operating

K6R4008V1C-10 : 155mA(Max.)

K6R4008V1C-12 : 145mA(Max.)

K6R4008V1C-15 : 135mA(Max.)

• Single 3.3±0.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• 2V Minimum Data Retention : L-Ver. only

• Center Power/Ground Pin Configuration

• Standard Pin Configuration

K6R4008V1C-J : 36-SOJ-400

K6R4008V1C-T : 44-TSOP2-400BF

FUNCTIONAL BLOCK DIAGRAM

ORDERING INFORMATION

K6R4008V1C-C10/C12/C15

Commercial Temp.

Industrial Temp.

Clk Gen.

Pre-Charge Circuit

K6R4008V1C-I10/I12/I15

Memory Array

1024 Rows

512 x 8 Columns

Data

Cont.

I/O Circuit

Column Select

I/O1~I/O8

CLK

Gen.

A10 A11 A12 A13 A14 A15 A16 A17 A18

Rev 5.0

September 2001

- 2 -

PRELIMINARY

CMOS SRAM

K6R4008V1C-C/C-L, K6R4008V1C-I/C-P

PIN CONFIGURATION (Top View)

N.C

44 N.C

43 N.C

42 N.C

41 A18

40 A17

39 A16

38 A15

37 OE

36 I/O8

35 I/O7

34 Vss

33 Vcc

32 I/O6

31 I/O5

30 A14

29 A13

28 A12

27 A11

26 A10

25 N.C

24 N.C

23 N.C

36 N.C

35 A18

34 A17

33 A16

32 A15

31 OE

30 I/O8

29 I/O7

28 Vss

27 Vcc

26 I/O6

25 I/O5

24 A14

23 A13

22 A12

21 A11

20 A10

19 N.C

I/O1

I/O2

Vcc

I/O1

I/O2 10

Vcc 11

Vss 12

I/O3 13

I/O4 14

WE 15

A5 16

A6 17

A7 18

A8 19

A9 20

N.C 21

N.C 22

36-SOJ

44-TSOP2

Vss 10

I/O3 11

I/O4 12

WE 13

A5 14

A6 15

A7 16

A8 17

A9 18

PIN FUNCTION

Pin Name

A0 - A18

Pin Function

Address Inputs

Write Enable

Chip Select

Output Enable

Data Inputs/Outputs

Power(+3.3V)

Ground

I/O1 ~ I/O8

VCC

VSS

N.C

No Connection

ABSOLUTE MAXIMUM RATINGS*

Parameter

Voltage on Any Pin Relative to VSS

Voltage on VCC Supply Relative to VSS

Power Dissipation

Symbol

VIN, VOUT

VCC

Rating

-0.5 to 4.6

1.0

Unit

Storage Temperature

TSTG

-65 to 150

0 to 70

°C

Operating Temperature

Commercial

Industrial

-40 to 85

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Rev 5.0

September 2001

- 3 -

PRELIMINARY

CMOS SRAM

K6R4008V1C-C/C-L, K6R4008V1C-I/C-P

RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)

Parameter

Supply Voltage

Symbol

VCC

VSS

Min

3.0

Typ

Max

Unit

3.3

3.6

Ground

Input High Voltage

Input Low Voltage

VIH

2.0

VCC+0.3***

0.8

VIL

-0.3**

The above parameters are also guaranteed at industrial temperature range.

** VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.

*** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 8ns) for I £ 20mA

DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input Leakage Current

Output Leakage Current

ILI

VIN=VSS to VCC

-2

ILO

CS=VIH or OE=VIH or WE=VIL

VOUT=VSS to VCC

-2

Operating Current

ICC

Min. Cycle, 100% Duty

CS=VIL, VIN=VIH or VIL, IOUT=0mA

Com.

Ind.

10ns

12ns

15ns

10ns

12ns

15ns

155

145

135

170

160

150

Standby Current

ISB

Min. Cycle, CS=VIH

ISB1

f=0MHz, CS³ VCC-0.2V,

Norrmal

VIN³ VCC-0.2V or VIN£0.2V

L-Ver.

1.2

0.4

Output Low Voltage Level

Output High Voltage Level

VOL

VOH

IOL=8mA

IOH=-4mA

2.4

* The above parameters are also guaranteed at industrial temperature range.

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item

Input/Output Capacitance

Input Capacitance

Symbol

CI/O

Test Conditions

VI/O=0V

MIN

Max

Unit

VIN=0V

CIN

* Capacitance is sampled and not 100% tested.

Rev 5.0

September 2001

- 4 -

PRELIMINARY

CMOS SRAM

K6R4008V1C-C/C-L, K6R4008V1C-I/C-P

AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)

TEST CONDITIONS*

Parameter

Value

Input Pulse Levels

0V to 3V

3ns

Input Rise and Fall Times

Input and Output timing Reference Levels

Output Loads

1.5V

See below

*The above test conditions are also applied at industrial temperature range.

Output Loads(A)

Output Loads(B)

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

+3.3V

RL = 50W

DOUT

VL = 1.5V

30pF*

319W

DOUT

ZO = 50W

353W

5pF*

* Including Scope and Jig Capacitance

* Capacitive Load consists of all components of the

test environment.

READ CYCLE*

K6R4008V1C-10

K6R4008V1C-12

K6R4008V1C-15

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

tLZ

Output Enable to Valid Output

Chip Enable to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Chip Selection to Power Up Time

Chip Selection to Power DownTime

tOLZ

tHZ

tOHZ

tOH

tPU

tPD

* The above parameters are also guaranteed at industrial temperature range.

Rev 5.0

September 2001

- 5 -

PRELIMINARY

CMOS SRAM

K6R4008V1C-C/C-L, K6R4008V1C-I/C-P

WRITE CYCLE*

K6R4008V1C-10

K6R4008V1C-12

K6R4008V1C-15

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

Write Cycle Time

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width(OE High)

Write Pulse Width(OE Low)

Write Recovery Time

tAW

tWP

tWP1

tWR

tWHZ

tDW

tDH

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

tOW

* The above parameters are also guaranteed at industrial temperature range.

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tAA

tOH

Data Out

Valid Data

Previous Valid Data

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tAA

tHZ(3,4,5)

tCO

tOE

tOHZ

tOH

tOLZ

tLZ(4,5)

Data out

Valid Data

tPU

tPD

ICC

ISB

VCC

50%

Current

NOTES(WRITE CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

VOL levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

Rev 5.0

September 2001

- 6 -

PRELIMINARY

CMOS SRAM

K6R4008V1C-C/C-L, K6R4008V1C-I/C-P

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

tWC

Address

tWR(5)

tAW

tCW(3)

tWP(2)

tAS(4)

tDW

tDH

High-Z

Data in

Data out

Valid Data

tOHZ(6)

High-Z(8)

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)

tWC

Address

tWR(5)

tAW

tCW(3)

tAS(4)

tWP1(2)

tDH

tDW

High-Z

Data in

Valid Data

tWHZ(6)

tOW

(10)

(9)

High-Z(8)

Data out

TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)

tWC

Address

tAW

tWR(5)

tCW(3)

tWP(2)

tAS(4)

tDH

tDW

High-Z

Data in

Data out

Valid Data

tLZ

tWHZ(6)

High-Z(8)

Rev 5.0

September 2001

- 7 -

PRELIMINARY

CMOS SRAM

K6R4008V1C-C/C-L, K6R4008V1C-I/C-P

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write

ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the

output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.

FUNCTIONAL DESCRIPTION

Mode

Not Select

Output Disable

Read

I/O Pin

High-Z

DOUT

Supply Current

ISB, ISB1

ICC

Write

DIN

ICC

* X means Don¢t Care.

DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)

Parameter

VCC for Data Retention

Data Retention Current

Symbol

VDR

Test Condition

CS ³ VCC - 0.2V

VCC=3.0V, CS³ VCC - 0.2V

Min.

2.0

Typ.

Max.

3.6

Unit

IDR

1.0

VIN ³ VCC - 0.2V or VIN£0.2V

VCC=2.0V, CS³ VCC - 0.2V

VIN³ VCC - 0.2V or VIN£0.2V

0.7

Data Retention Set-Up Time

Recovery Time

tSDR

tRDR

See Data Retention

Wave form(below)

* The above parameters are also guaranteed at industrial temperature range.

Data Retention Characteristic is for L-ver only.

DATA RETENTION WAVE FORM

CS controlled

Data Retention Mode

tSDR

tRDR

VCC

3.0V

VIH

VDR

CS³ VCC - 0.2V

GND

Rev 5.0

September 2001

- 8 -

PRELIMINARY

CMOS SRAM

K6R4008V1C-C/C-L, K6R4008V1C-I/C-P

Units:millimeters/Inches

PACKAGE DIMENSIONS

36-SOJ-400

#36

#19

9.40 ±0.25

0.370 ±0.010

11.18 ±0.12

0.440 ±0.005

+0.10

-0.05

0.20

+0.004

-0.002

#18

0.008

0.69

MIN

0.027

23.90

MAX

0.941

23.50 ±0.12

0.925 ±0.005

1.19

0.047

1.27

(

)

3.76

0.148

0.10

0.004

MAX

0.050

+0.10

-0.05

0.43

+0.10

+0.004

-0.002

0.71

0.028

-0.05

0.017

0.95

0.0375

1.27

0.050

(

)

+0.004

-0.002

44-TSOP2-400BF

Units:millimeters/Inches

0~8°

0.25

0.010

TYP

#23

#44

0.45 ~0.75

0.018 ~ 0.030

11.76 ±0.20

0.463 ±0.008

0.50

0.020

(

)

#22

18.81

0.741

MAX

+ 0.075

- 0.035

+ 0.003

- 0.001

0.125

0.005

18.41 ±0.10

0.725 ±0.004

1.00 ±0.10

0.039 ±0.004

1.20

0.047

MAX

0.10

0.004

MAX

+0.10

- 0.05

+0.004

- 0.002

0.05

0.002

0.30

MIN

0.80

0.0315

0.805

0.032

(

)

0.012

Rev 5.0

September 2001

- 9 -

K6R4008V1C-P [SAMSUNG]

相关型号：

K6R4008V1C-TC10T

K6R4008V1C-TC120

K6R4008V1C-TC15

K6R4008V1C-TC150

K6R4008V1C-TL10T

K6R4008V1C-TL12T

K6R4008V1C-TL15T

K6R4008V1C-TP100

K6R4008V1C-TP12

K6R4008V1C-TP120

K6R4008V1C-TP150

K6R4008V1C-TP15T