K6T0808C1D-RP700 [SAMSUNG]
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, REVERSE, TSOP1-28;型号: | K6T0808C1D-RP700 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, REVERSE, TSOP1-28 静态存储器 光电二极管 内存集成电路 |
文件: | 总9页 (文件大小:170K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K6T0808C1D Family
CMOS SRAM
Document Title
32Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No History
Draft Data
Remark
0.0
0.1
Initial draft
May 18, 1997
Design target
First revision
April 1, 1997
Preliminily
- KM62256DL/DLI ISB1 = 100 ® 50mA
KM62256DL-L ISB1 = 20 ® 10mA
KM62256DLI-L ISB1 = 50 ® 15mA
- CIN = 6 ® 8pF, CIO = 8 ® 10pF
- KM62256D-4/5/7 Family
tOH = 5 ® 10ns
- KM62256DL/DLI IDR = 50® 30mA
KM62256DL-L/DLI-L IDR = 30 ® 15mA
1.0
Finalize
November 11, 1997
Final
- Remove ICC write value
- Improved operating current
ICC2 = 70 ® 60mA
- Improved standby current
KM62256DL/DLI ISB1 = 50 ® 30mA
KM62256DL-L ISB1 = 10 ® 5mA
KM62256DLI-L ISB1 = 15 ® 5mA
- Improved data retention current
KM62256DL/DLI IDR = 30 ® 5mA
KM62256DL-L/DLI-L IDR = 15 ® 3mA
- Remove 45ns part from commercial product and 100ns part
from industrial product.
Replace test load 100pF to 50pF for 55ns part
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
November 1997
K6T0808C1D Family
CMOS SRAM
32Kx8 bit Low Power CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology : TFT
The K6T0808C1D families are fabricated by SAMSUNG¢s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The fami-
lies also support low data retention voltage for battery back-
up operation with low data retention current.
· Organization : 32Kx8
· Power Supply Voltage : 4.5~5.5V
· Low Data Retention Voltage : 2V(Min)
· Three state output and TTL Compatible
· Package Type : 28-DIP-600B, 28-SOP-450
28-TSOP1-0813.4 F/R
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
VCC Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(Icc2, Max)
K6T0808C1D-L
K6T0808C1D-B
K6T0808C1D-P
K6T0808C1D-F
30mA
5mA
28-DIP,28-SOP
28-TSOP1-F/R
551)/70ns
70ns
Commercial (0~70°C)
Industrial (-40~85°C)
4.5 to 5.5V
60mA
30mA
5mA
28-SOP
28-TSOP1-F/R
1. The parameter is tested with 50pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
28
27
26
25
24
23
22
21
A10
CS
OE
A11
A9
Clk gen.
Precharge circuit.
2
3
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
4
A8
A13
A8
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
5
A13
WE
VCC
A14
A12
A7
6
2
28-TSOP
Type1 - Forward
7
A12
8
3
Memory array
256 rows
128´ 8 columns
20
19
18
17
16
15
9
Row
select
A14
A4
4
A6
10
11
12
13
14
A6
5
A9
A5
A5
A5
A6
A7
A1
A4
6
A11
OE
A4
A2
A3
28-DIP
7
A3
28-SOP
8
14
13
12
11
10
9
A3
A4
A10
CS
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A2
A2
A1
9
A1
I/O Circuit
A5
Data
cont
I/O1
I/O8
A0
A6
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
Column select
10
11
12
13
14
I/O8
I/O7
I/O6
I/O5
I/O4
A0
A7
A12
A14
VCC
WE
A13
A8
I/O1
I/O2
I/O3
VSS
8
28-TSOP
Type1 - Reverse
Data
cont
7
6
5
4
A10 A3 A0 A1 A2 A9 A11
A9
3
A11
2
1
A10
OE
CS
Pin Name
CS
Function
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Pin Name
I/O1~I/O8
Vcc
Function
Control
Logic
WE
OE
Data Inputs/Outputs
Power
OE
WE
Vss
Ground
A0~A14
NC
No connect
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 1.0
November 1997
K6T0808C1D Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Industrial Temperature Products(-40~85°C)
Part Name
Function
Part Name
Function
K6T0808C1D-DL55
K6T0808C1D-DB55
K6T0808C1D-DL70
K6T0808C1D-DB70
K6T0808C1D-GL55
K6T0808C1D-GB55
K6T0808C1D-GL70
K6T0808C1D-GB70
K6T0808C1D-TL55
K6T0808C1D-TB55
K6T0808C1D-TL70
K6T0808C1D-TB70
K6T0808C1D-RL55
K6T0808C1D-RB55
K6T0808C1D-RL70
K6T0808C1D-RB70
28-DIP, 55ns, L-pwr
K6T0808C1D-GP70
K6T0808C1D-GF70
K6T0808C1D-TP70
K6T0808C1D-TF70
K6T0808C1D-RP70
K6T0808C1D-RF70
28-SOP, 70ns, L-pwr
28-DIP, 55ns, LL-pwr
28-DIP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP1 F, 70ns, L-pwr
28-TSOP1 F, 70ns, LL-pwr
28-TSOP1 R, 70ns, L-pwr
28-TSOP1 R, 70ns, LL-pwr
28-DIP, 70ns, LL-pwr
28-SOP, 55ns, L-pwr
28-SOP, 55ns, LL-pwr
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP1 F, 55ns, L-pwr
28-TSOP1 F, 55ns, LL-pwr
28-TSOP1 F, 70ns, L-pwr
28-TSOP1 F, 70ns, LL-pwr
28-TSOP1 R, 55ns, L-pwr
28-TSOP1 R, 55ns, LL-pwr
28-TSOP1 R, 70ns, L-pwr
28-TSOP1 R, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X1)
H
WE
X1)
H
I/O
High-Z
High-Z
Dout
Mode
Power
Standby
Active
Deselected
Output Disabled
Read
L
L
H
Active
X1)
L
L
Din
Write
Active
1. X means don¢t care (Must be in high or low states)
1)
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
-0.5 to 7.0
-0.5 to 7.0
1.0
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-
V
-
PD
W
-
Storage temperature
TSTG
-65 to 150
0 to 70
°C
°C
°C
-
K6T0808C1D-L
K6T0808C1D-P
-
Operating Temperature
TA
-40 to 85
Soldering temperature and time
TSOLDER
260°C, 10sec (Lead Only)
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 1.0
November 1997
K6T0808C1D Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
4.5
0
Typ
Max
Unit
V
Supply voltage
Ground
5.0
5.5
Vss
0
-
0
V
Vcc+0.5V2)
0.8
Input high voltage
Input low voltage
VIH
2.2
-0.53)
V
VIL
-
V
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width£30ns
3. Undershoot : -3.0V in case of pulse width£30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
-
-
pF
pF
Input/Output capacitance
CIO
VIO=0V
10
1. Capacitance is sampled not, 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
1
1
mA
mA
Output leakage current
Operating power supply current
ILO
CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc
IIO=0mA, CS=VIL, VIN=VIH or VIL, Read
ICC
5
2
-
10
5
mA
Read
Write
-
Cycle time=1ms, 100% duty, IIO=0mA
CS£0.2V, VIN£0.2V, VIN³ Vcc -0.2V
ICC1
mA
Average operating current
20
60
0.4
-
ICC2
VOL
VOH
ISB
Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
-
45
-
mA
V
Output low voltage
Output high voltage
Standby Current(TTL)
IOL=2.1mA
-
IOH=-1.0mA
2.4
-
V
CS=VIH, Other inputs=VIH or VIL
-
-
-
-
1
mA
mA
mA
Low Power
1
0.2
30
5
Standby Current (CMOS)
ISB1
CS³ Vcc-0.2V, Other inputs=0~Vcc
Low Low Power
Revision 1.0
November 1997
K6T0808C1D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
1)
Input rising and falling time : 5ns
CL
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
CL=50pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, K6T0808C1D-L Family:TA=0 to 70°C, K6T0808C1D-P Family:TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
551)ns
Max
70ns
Min
55
-
Min
70
-
Max
Read cycle time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
tCO
tOE
-
-
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
Read
tLZ
10
5
10
5
tOLZ
tHZ
-
-
0
20
20
-
0
30
30
-
tOHZ
tOH
tWC
tCW
tAS
0
0
10
55
45
0
10
70
60
0
-
-
Chip select to end of write
Address set-up time
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
-
60
50
0
-
-
-
Write
Write recovery time
-
-
Write to output high-Z
0
20
-
0
25
-
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
30
0
-
-
tOW
5
-
5
-
1. The parameter is tested with 50pF test load.
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
5.5
15
3
Unit
Vcc for data retention
VDR
CS³ Vcc-0.2V
2.0
-
-
1
V
L-Ver
Data retention current
IDR
Vcc=3.0V, CS³ Vcc-0.2V
mA
LL-Ver
-
0.2
-
Data retention set-up time
Recovery time
tSDR
tRDR
0
-
See data retention waveform
ms
5
-
-
Revision 1.0
November 1997
K6T0808C1D Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tOE
OE
tOLZ
tLZ
tOHZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 1.0
November 1997
K6T0808C1D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS
tAW
tWP(1)
WE
tDW
tDH
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
Revision 1.0
November 1997
K6T0808C1D Family
CMOS SRAM
Units: millimeter(inch)
PACKAGE DIMENSIONS
+0.10
-0.05
28 PIN DUAL INLINE PACKAGE(600mil)
0.25
+0.004
-0.002
0.010
#28
#15
13.60± 0.20
0.535± 0.008
#1
#14
0~15°
3.81± 0.20
0.150± 0.008
36.72
1.446
MAX
5.08
0.200
MAX
36.32± 0.20
1.430± 0.008
3.30± 0.30
0.46± 0.10
0.130± 0.012
0.018± 0.004
0.38
0.015
2.54
0.100
1.65
0.065
1.52± 0.10
0.060± 0.004
MIN
(
)
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
0~8°
#28
#15
8.38± 0.20
0.330± 0.008
11.81± 0.30
0.465± 0.012
#1
#14
1.02± 0.20
0.040± 0.008
+0.10
-0.05
+0.004
-0.002
0.15
2.59± 0.20
0.102± 0.008
18.69
MAX
0.006
0.736
3.00
MAX
0.118
18.29± 0.20
0.720± 0.008
0.10 MAX
0.004 MAX
0.89
0.035
1.27
0.050
0.41± 0.10
0.016± 0.004
(
)
0.05
0.002
MIN
Revision 1.0
November 1997
K6T0808C1D Family
CMOS SRAM
Units: millimeter(inch)
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)
13.40± 0.20
0.528± 0.008
+0.10
-0.05
+0.004
0.20
0.008
-0.002
#1
#28
0.425
0.017
(
)
0.55
0.0217
#14
#15
0.25
0.010
11.80± 0.10
0.465± 0.004
+0.10
-0.05
TYP
0.15
+0.004
0.006
-0.002
1.00± 0.10
0.039± 0.004
0.05
0.002
MIN
0~8°
1.20
MAX
0.047
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)
13.40± 0.20
0.528± 0.008
+0.10
-0.05
0.20
0.008+0.004
-0.002
#14
#15
0.425
0.017
(
)
0.55
0.0217
#1
#28
1.00± 0.10
0.05
0.002
MIN
0.25
0.010
11.80± 0.10
0.465± 0.004
0.039± 0.004
+0.10
-0.05
TYP
0.15
0.006+0.004
1.20
MAX
0.047
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
Revision 1.0
November 1997
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