K6T1008C2E-DB700 [SAMSUNG]
Standard SRAM, 128KX8, 70ns, CMOS, PDIP32, 0.600 INCH, DIP-32;
| 型号： | K6T1008C2E-DB700 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 128KX8, 70ns, CMOS, PDIP32, 0.600 INCH, DIP-32 静态存储器 光电二极管 |
| 文件： | 总10页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6T1008C2E Family
CMOS SRAM
Document Title
128Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
1.0
Design target
October 12, 1998
August 30, 1999
Preliminary
Final
Finalize
- Improve tWP form 55ns to 50ns for 70ns product.
- Remove 55ns speed bin from industrial product.
1.01
2.0
Errata correction
Revise
December 1, 1999
February 14, 2000
March 3, 2000
Final
Final
3.0
Revise
- Add 55ns parts to industrial products.
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
128Kx8 bit Low Power CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: TFT
The K6T1008C2E families are fabricated by SAMSUNG¢s
advanced CMOS process technology. The families support
various operating temperature ranges and have various pack-
age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
· Organization: 128Kx8
· Power Supply Voltage: 4.5~5.5V
· Low Data Retention Voltage: 2V(Min)
· Three state output and TTL Compatible
· Package Type: 32-DIP-600, 32-SOP-525,
32-TSOP1-0820F/R
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
K6T1008C2E-L
K6T1008C2E-B
K6T1008C2E-P
K6T1008C2E-F
50mA
10mA
50mA
15mA
32-DIP-600, 32-SOP-525
32-TSOP1-0820F/R
Commercial(0~70°C)
Industrial(-40~85°C)
4.5~5.5V
551)/70ns
50mA
32-SOP -525
32-TSOP1-0820F/R
1. The parameters are tested with 50pF test load
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
Clk gen.
Precharge circuit.
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
VCC
A15
CS2
WE
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
32-TSOP
Type1-Forward
3
9
10
11
12
13
14
15
16
4
Memory array
1024 rows
128´ 8 columns
Raw
Address
Row
select
A13
A8
5
6
A6
32-SOP
32-DIP
A6
A5
A4
A1
A2
A3
A9
A5
7
A11
OE
A4
8
9
A3
A4
A5
A6
16
15
14
13
12
11
10
9
8
7
6
5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A2
10
11
12
13
14
15
16
A2
A1
A0
A1
A7
A12
A14
A16
NC
VCC
A15
CS2
WE
A13
A8
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
Data
cont
I/O Circuit
I/O1
I/O8
I/O1
I/O2
I/O3
VSS
32-TSOP
Type1-Reverse
Column select
Data
cont
4
3
2
1
A9
A11
Column Address
Name
CS1, CS2
OE
Function
Chip Select Input
Output Enable Input
Write Enable Input
Data Inputs/Outputs
Address Inputs
Power
CS1
Control
logic
CS2
WE
WE
OE
I/O1~I/O8
A0~A16
Vcc
Vss
Ground
NC
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Industrial Temperature Products(-40~85°C)
Part Name
Function
Part Name
Function
K6T1008C2E-DL55
K6T1008C2E-DL70
K6T1008C2E-DB55
K6T1008C2E-DB70
32-DIP, 55ns, Low Power
32-DIP, 70ns, Low Power
32-DIP, 55ns, Low Low Power
32-DIP, 70ns, Low Low Power
K6T1008C2E-GP55
K6T1008C2E-GP70
K6T1008C2E-GF55
K6T1008C2E-GF70
32-SOP, 55ns, Low Power
32-SOP, 70ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Low Power
K6T1008C2E-GL55
K6T1008C2E-GL70
K6T1008C2E-GB55
K6T1008C2E-GB70
32-SOP, 55ns, Low Power
32-SOP, 70ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Low Power
K6T1008C2E-TF55
K6T1008C2E-TF70
K6T1008C2E-RF55
K6T1008C2E-RF70
32-TSOP-F, 55ns, Low Low Power
32-TSOP-F, 70ns, Low Low Power
32-TSOP-R, 55ns, Low Low Power
32-TSOP-R, 70ns, Low Low Power
K6T1008C2E-TB55
K6T1008C2E-TB70
K6T1008C2E-RB55
K6T1008C2E-RB70
32-TSOP-F, 55ns, Low Low Power
32-TSOP-F, 70ns, Low Low Power
32-TSOP-R, 55ns, Low Low Power
32-TSOP-R, 70ns, Low Low Power
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Power
Standby
Standby
Active
X1)
L
X1)
X1)
H
High-Z
High-Z
Deselected
Deselected
X1)
L
X1)
H
X1)
H
H
H
H
High-Z
Dout
Din
Output Disabled
Read
L
L
L
H
L
Active
X1)
Write
Active
1. X means don¢t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-0.5 to 7.0
-0.5 to 7.0
1.0
-
-
-
-
V
PD
W
Storage temperature
TSTG
-65 to 150
0 to 70
°C
°C
°C
K6T1008C2E-L/-B
K6T1008C2E-P/-F
Operating Temperature
TA
-40 to 85
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Supply voltage
Ground
Symbol
Vcc
Product
Min
4.5
0
Typ
Max
5.5
0
Unit
V
K6T1008C2E Family
All Family
5.0
Vss
0
-
V
Vcc+0.52)
0.8
Input high voltage
Input low voltage
Note:
VIH
K6T1008C2E Family
K6T1008C2E Family
2.2
V
-0.53)
VIL
-
V
1. Commercial Product: TA=0 to 70°C
Industrial Product: TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+3.0V in case of pulse width£30ns.
3. Undershoot: -3.0V in case of pulse width£30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
1
)
CAPACITANCE (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
Test Condition
Min
Max
6
Unit
CIN
CIO
VIN=0V
VIO=0V
-
-
pF
pF
Input/Output capacitance
8
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
-
1
1
mA
mA
Output leakage current
Operating power supply current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read
ICC
10 mA
mA
Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V, CS2³ Vcc-0.2V,
VIN£0.2V or VIN³ VCC-0.2V
ICC1
ICC2
-
-
-
-
7
Average operating current
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH,
VIN=VIH or VIL
50 mA
Output low voltage
VOL
VOH
ISB
IOL=2.1mA
-
2.4
-
-
-
-
-
0.4
-
V
V
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
IOH=-1.0mA
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V, Other inputs=0~Vcc
3
mA
mA
501)
ISB1
-
1. 50mA for Low power product, in case of Low Low power products are comercial=10mA, industrial=15mA.
4
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
1)
CL
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
55ns
70ns
Min
55
-
Max
Min
70
-
Max
Read Cycle Time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
-
-
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
-
-
Read
tLZ
10
5
10
5
tOLZ
tHZ
-
-
0
20
20
-
0
25
25
-
tOHZ
tOH
tWC
tCW
tAS
0
0
10
55
45
0
10
70
60
0
-
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
-
60
50
0
-
-
-
Write
Write Recovery Time
-
-
Write to Output High-Z
0
20
-
0
25
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
20
0
25
0
-
-
tOW
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
CS1³ Vcc-0.2V1)
Vcc for data retention
VDR
2.0
-
-
-
-
-
-
-
5.5
20
10
25
10
-
V
K6T1008C2E-L
K6T1008C2E-B
K6T1008C2E-P
K6T1008C2F-F
-
-
Vcc=3.0V, CS1³ Vcc-0.2V1)
Data retention current
IDR
mA
-
-
Data retention set-up time
Recovery time
tSDR
tRDR
0
5
See data retention waveform
ms
-
1. CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or CS2£0.2V(CS2 controlled)
5
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
CS1
tCW(2)
tAS(3)
tWR(4)
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
7
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
CS1
tAS(3)
tCW(2)
tWR(4)
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
2.2V
VDR
CS³ VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
4.5V
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
8
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
PACKAGE DIMENSIONS
32 DUAL INLINE PACKAGE (600mil)
Units: millimeters(inches)
+0.10
0.25
-0.05
+0.004
-0.002
0.010
#32
#17
13.60±0.20
0.535±0.008
#1
#16
0~15°
3.81±0.20
0.150±0.008
42.31
1.666
MAX
5.08
0.200
MAX
41.91±0.20
1.650±0.008
3.30±0.30
0.130±0.012
0.46±0.10
0.018±0.004
0.38
MIN
1.91
0.075
1.52±0.10
0.060±0.004
2.54
0.100
(
)
0.015
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
#17
14.12±0.30
0.556±0.012
11.43±0.20
0.450±0.008
#1
#16
0.80±0.20
+0.10
-0.05
0.20
2.74±0.20
0.031±0.008
20.87
MAX
0.108±0.008
+0.004
0.822
0.008
-0.002
3.00
MAX
0.118
20.47±0.20
0.806±0.008
0.10 MAX
0.004 MAX
+0.100
-0.050
0.41
0.71
0.028
1.27
0.050
+0.004
-0.002
(
)
0.05
0.002
0.016
MIN
9
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
0.008+0.004
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#17
#16
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
18.40±0.10
0.724±0.004
TYP
+0.10
0.15
-0.05
0.006+0.004
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
+0.004
-0.002
0.008
#16
#17
0.25
0.010
(
)
0.50
0.0197
#1
#32
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
18.40±0.10
0.724±0.004
TYP
+0.10
-0.05
0.15
+0.004
-0.002
0.006
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
10
Revision 3.0
March 2000
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