K6T2008S2M-YF15 [SAMSUNG]
Standard SRAM, 256KX8, 150ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32;型号: | K6T2008S2M-YF15 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 256KX8, 150ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32 静态存储器 光电二极管 |
文件: | 总9页 (文件大小:183K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K6T2008S2M Family
CMOS SRAM
Document Title
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial draft
September 30, 1997 Preliminary
1.0
Finalize
August 27, 1998
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
August 1998
K6T2008S2M Family
CMOS SRAM
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: TFT
The K6T2008S2M families are fabricated by SAMSUNG¢s
advanced CMOS process technology. The families support
various operating temperature ranges and various package
type for user flexibility of system design. The families also sup-
port low data retention voltage for battery back-up operation
with low data retention current.
· Organization: 256Kx8
· Power Supply Voltage
K6T2008S2M Family: 2.3~2.7V
· Low Data Retention Voltage: 2V(Min)
· Three state output and TTL Compatible
· Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
K6T2008S2M-B
K6T2008S2M-F
Commercial(0~70°C)
Industrial(-40~85°C)
10mA
15mA
32-TSOP1-F
32-sTSOP1-F
2.3~2.7V
1201)/150ns
25mA
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
Clk gen.
Precharge circuit.
2
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
3
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
4
5
Vcc
Vss
A3
6
32-TSOP
32-STSOP
Type1 - Forward
7
A8
8
9
A9
10
11
12
13
14
15
16
A10
A11
Memory array
1024 rows
256´ 8 columns
Row
select
A6
A5
A4
A13
A14
A15
A17
A1
A2
A3
A16
Name
Function
Name
Function
I/O Circuit
I/O1
I/O8
Data
cont
CS1,CS2 Chip Select Input
I/O1~I/O8 Data Inputs/Outputs
Column select
OE
Output Enable Input
Write Enable Input
Vcc
Vss
N.C.
Power
WE
Ground
Data
cont
A0~A17 Address Inputs
No Connection
A0 A1 A2 A4 A5 A6 A7 A12
CS1
CS2
Control
Logic
WE
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 1.0
August 1998
K6T2008S2M Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Industrial Temperture Products(-40~85°C)
Part Name
Function
Part Name
Function
K6T2008S2M-TB12
K6T2008S2M-TB15
K6T2008S2M-YB12
K6T2008S2M-YB15
32-TSOP F, 120ns, 2.3~2.7V, LL
32-TSOP F, 150ns, 2.3~2.7V, LL
32-sTSOP F, 120ns, 2.3~2.7V, LL
32-sTSOP F, 150ns, 2.3~2.7V, LL
K6T2008S2M-TF12
K6T2008S2M-TF15
K6T2008S2M-YF12
K6T2008S2M-YF15
32-TSOP F, 120ns, 2.3~2.7V, LL
32-TSOP F, 150ns, 2.3~2.7V, LL
32-sTSOP F, 120ns, 2.3~2.7V, LL
32-sTSOP F, 150ns, 2.3~2.7V, LL
Note : LL - Low Low Standby Current
FUNCTIONAL DESCRIPTION
CS1
H
CS2
X1)
L
OE
X1)
X1)
H
WE
X1)
X1)
H
I/O
Mode
Deselected
Deselected
Output Disabled
Read
Power
Standby
Standby
Active
High-Z
X1)
L
High-Z
High-Z
Dout
H
L
H
L
H
Active
X1)
L
H
L
Din
Write
Active
1. X means don¢t care (Must be in high or low states)
)
1
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-0.5 to VCC+0.5
-0.3 to 4.6
1
-
V
-
PD
W
-
Storage temperature
TSTG
-65 to 150
0 to 70
°C
°C
°C
-
K6T2008S2M-L
K6T2008S2M-P
-
Operating Temperature
TA
-40 to 85
Soldering temperature and time
TSOLDER
260°C, 10sec (Lead Only)
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 1.0
August 1998
K6T2008S2M Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Supply voltage
Symbol
Vcc
Product
Min
2.3
0
Typ
Max
2.7
Unit
V
K6T2008S2M Family
All Family
2.5
Ground
Vss
0
-
0
V
Vcc+0.32)
0.6
Input high voltage
Input low voltage
VIH
K6T2008S2M Family
K6T2008S2M Family
2.0
-0.33)
V
VIL
-
V
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : Vcc+1.0V in case of pulse width£20ns
3. Undershoot : -1.0V in case of pulse width£20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
Unit
VIN=0V
VIO=0V
-
-
8
pF
pF
Input/Output capacitance
CIO
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min
Typ Max Unit
Input leakage current
Output leakage current
Operating power supply
VIN=Vss to Vcc
-1
-
-
-
-
-
-
-
-
-
-
1
1
mA
mA
ILO
-1
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read
ICC
-
2
mA
Cycle time=1ms, 100% duty, IIO=0mA
CS1£0.2V, CS2³ Vcc-0.2V, VIN£0.2V or VIN³ Vcc-0.2V
Read
Write
-
3
ICC1
mA
Average operating current
-
10
25
0.4
-
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH
IOL=0.5mA
ICC2
VOL
VOH
ISB
-
mA
V
Output low voltage
Output high voltage
Standby Current(TTL)
-
2.0
-
IOH=-0.5mA
V
CS1=VIH, CS2=VIL, Other inputs=VIL or VIH
CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V, Other inputs=0~Vcc
0.3
101)
mA
mA
Standby Current (CMOS)
ISB1
-
1. Industrial product=15mA
Revision 1.0
August 1998
K6T2008S2M Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
1)
CL
Input and output reference voltage : 1.5V
Output load (See right) : CL=100pF+1TTL
CL=30pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=2.3~2.7V, Commercial products:TA=0 to 70°C, Industrial products:TA=-40 to 85°C)
Speed Bins
120ns1)
Parameter List
Symbol
Units
150ns
Min
120
-
Max
Min
150
-
Max
Read cycle time
tRC
tAA
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
120
150
Chip select to output
tCO1, tCO2
tOE
-
120
-
150
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
60
-
-
75
-
Read
tLZ
20
20
-
20
20
0
tOLZ
tHZ
-
-
35
35
-
40
40
-
tOHZ
tOH
-
0
15
120
100
0
15
150
120
0
tWC
-
-
Chip select to end of write
Address set-up time
tCW1, tCW2
tAS
-
-
-
-
Address valid to end of write
Write pulse width
tAW
100
80
0
-
120
100
0
-
tWP
-
-
Write
Write recovery time
tWR
-
-
Write to output high-Z
tWHZ
tDW
0
30
-
0
40
-
Data to write time overlap
Data hold from write time
End write to output low-Z
50
0
60
0
tDH
-
-
tOW
5
-
5
-
1. The parameter is measured with 30pF test load.
DATA RETENTION CHARACTERISTICS
Item
Symbol
VDR
Test Condition
Min
2.0
-
Typ
Max
Unit
V
CS1³ Vcc-0.2V1)
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
-
-
-
-
3.3
10
-
IDR
Vcc=2.0V, CS1³ Vcc-0.2V or CS2£0.2V
mA
tSDR
0
See data retention waveform
ms
tRDR
5
-
1. CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 Contrlled) or CS2£0.2V(CS2 Controlled)
Revision 1.0
August 1998
K6T2008S2M Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 1.0
August 1998
K6T2008S2M Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
CS1
tCW(2)
tAS(3)
tWR(4)
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
Revision 1.0
August 1998
K6T2008S2M Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled)
tWC
Address
CS1
tAS(3)
tCW(2)
tWR(4)
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
2.3V
2.2V
VDR
CS1³ VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
2.3V
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
Revision 1.0
August 1998
K6T2008S2M Family
CMOS SRAM
Units: millimeter(Inch)
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
0.008+0.004
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#17
#16
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
18.40±0.10
0.724±0.004
TYP
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
+0.10
-0.05
+0.004
0.20
13.40±0.10
0.528±0.008
0.008
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#16
#17
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
TYP
11.80±0.10
0.465±0.004
+0.10
-0.05
0.15
+0.004
0.006
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
Revision 1.0
August 1998
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