K6T2008U2M-YB85T [SAMSUNG]

Standard SRAM, 256KX8, 85ns, CMOS, PDSO32;


型号：	K6T2008U2M-YB85T
厂家：	SAMSUNG
描述：	Standard SRAM, 256KX8, 85ns, CMOS, PDSO32 静态存储器光电二极管
文件：	总9页 (文件大小：146K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K6T2008V2M, K6T2008U2M Family

CMOS SRAM

Document Title

256Kx8 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No. History

Draft Data

Remark

0.0

0.1

1.0

Design target

Initial draft

January 30, 1997

April 7, 1997

Advance

Preliminary

Final

Finalize

November 27, 1997

- Improved VIL(Min.) : 0.4V ® 0.6V

- Erase reverse type package

- Change speed bin

KM68V2000 : 70/85ns

KM68V2000I, KM68U2000, KM68U2000I : 85/100ns

- Improved standby current

Commercial product : 15mA ® 10mA

Industrial product : 30mA ® 15mA

- Increased Power dissipation : 0.7W ® 1.0W

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

November 1997

K6T2008V2M, K6T2008U2M Family

CMOS SRAM

256Kx8 bit Low Power and Low Voltage CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: TFT

The K6T2008V2M and K6T2008U2M families are fabricated

by SAMSUNG¢s advanced CMOS process technology. The

families support various operating temperature ranges and

have various package types for user flexibility of system

design. The families also support low data retention voltage

for battery back-up operation with low data retention current.

· Organization: 256Kx8

· Power Supply Voltage

K6T2008V2M Family: 3.0V ~ 3.6V

K6T2008U2M Family: 2.7V ~ 3.3V

· Low Data Retention Voltage: 2V(Min)

· Three state output and TTL Compatible

· Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F

PRODUCT FAMILY

Power Dissipation

Product Family

Operating Temperature Vcc Range

Speed

PKG Type

Standby

(ISB1, Max)

Operating

(ICC2,Max)

K6T2008V2M-B

K6T2008U2M-B

3.0~3.6V

2.7~3.3V

3.0~3.6V

2.7~3.3V

70/85ns

85/100ns

Commercial

(0~70°C)

10mA

15mA

32-TSOP1-F

32-sTSOP1-F

40mA¹⁾

K6T2008V2M-F

Industrial

(-40~85°C)

K6T2008U2M-F

1. K6T2008V2M family = 50mA

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

A11

Clk gen.

Precharge circuit.

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A13

CS2

A15

VCC

A17

A16

A14

A12

32-TSOP

32-sTSOP1

Type - Forward

A10

A11

A13

A14

A15

A16

Memory array

1024 rows

256´ 8 columns

Row

select

A17

Name

Function

Chip Select Input

I/O1

I/O8

Data

cont

I/O Circuit

Column select

CS1,CS2

Output Enable Input

Write Enable Input

Address Inputs

Data Inputs/Outputs

Power

Data

cont

A0~A17

I/O1~I/O8

Vcc

A0 A1 A2 A4 A5 A6 A7 A12

CS1

Vss

Ground

Control

logic

CS2

N.C.

No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

November 1997

K6T2008V2M, K6T2008U2M Family

CMOS SRAM

PRODUCT LIST

Commercial Temperature Products(0~70°C)

Industrial Temperature Products(-40~85°C)

Part Name

Function

Part Name

Function

K6T2008V2M-TB70

K6T2008V2M-TB85

32-TSOP1 F, 70ns, 3.3V, LL

32-TSOP1 F, 85ns, 3.3V, LL

K6T2008V2M-TF85

K6T2008V2M-TF10

32-TSOP1 F, 85ns, 3.3V, LL

32-TSOP1 F, 100ns, 3.3V, LL

K6T2008U2M-TB85

K6T2008U2M-TB10

32-TSOP1 F, 85ns, 3.0V, LL

32-TSOP1 F, 100ns, 3.0V, LL

K6T2008U2M-TF85

K6T2008U2M-TF10

32-TSOP1 F, 85ns, 3.0V, LL

32-TSOP1 F, 100ns, 3.0V, LL

K6T2008V2M-YB70

K6T2008V2M-YB85

32-sTSOP1 F, 70ns, 3.3V,LL

32-sTSOP1 F, 85ns, 3.3V,LL

K6T2008V2M-YF85

K6T2008V2M-YF10

32-sTSOP1 F, 85ns, 3.3V,LL

32-sTSOP1 F, 100ns, 3.3V,LL

K6T2008U2M-YB85

K6T2008U2M-YB10

32-sTSOP1 F, 85ns, 3.0V, LL

32-sTSOP1 F, 100ns, 3.0V, LL

K6T2008U2M-YF85

K6T2008U2M-YF10

32-sTSOP1 F, 85ns, 3.0V, LL

32-sTSOP1 F, 100ns, 3.0V, LL

FUNCTIONAL DESCRIPTION

CS1

CS2

I/O

Mode

Power

Standby

Active

X¹⁾

High-Z

Deselected

X¹⁾

High-Z

Dout

Din

Output Disabled

Read

Active

X¹⁾

Write

Active

1. X means don¢t care (Must be in high or low states)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

VIN,VOUT

VCC

Ratings

-0.5 to VCC+0.5

-0.3 to 4.6

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

1.0

°C

Storage temperature

TSTG

-65 to 150

0 to 70

K6T2008V2M-L, K6T2008U2M-L

K6T2008V2M-P, K6T2008U2M-P

Operating Temperature

-40 to 85

Soldering temperature and time

TSOLDER

260°C, 10sec(Lead Only)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 1.0

November 1997

K6T2008V2M, K6T2008U2M Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Product

Min

Typ

Max

Unit

K6T2008V2M Family

K6T2008U2M Family

3.0

2.7

3.3

3.0

3.6

3.3

Supply voltage

Vcc

Ground

Vss

VIH

VIL

All Family

Vcc+0.3²⁾

0.6

Input high voltage

Input low voltage

Note:

K6T2008V2M, K6T2008U2M Family

2.2

-0.3³⁾

1. Commercial Product : TA=0 to 70°C, otherwise specified

Industrial Product : TA=-40 to 85°C, otherwise specified

2. Overshoot : Vcc+3.0V in case of pulse width£30ns

3. Undershoot : -3.0V in case of pulse width£30ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

Output leakage current

Operating power supply

VIN=Vss to Vcc

-1

ILO

CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read

-1

ICC

Read

Write

Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V,

CS2³ Vcc-0.2V, VIN£0.2V or VIN³ VCC-0.2V

ICC1

Average operating current

40¹⁾

0.4

Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL

IOL=2.1mA

ICC2

VOL

VOH

ISB

Output low voltage

2.2

Output high voltage

Standby Current(TTL)

Standby Current(CMOS)

IOH=-1.0mA

CS1=VIH, CS2=VIL, Other inputs=VIH or VIL

CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V, Other inputs=0~Vcc

0.3

10²⁾

ISB1

0.2

1. K6T2008V2M Family = 50mA

2. Industrial product = 15mA

Revision 1.0

November 1997

K6T2008V2M, K6T2008U2M Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Input/Output Reference)

Input pulse level: 0.4 to 2.2V

Input rising and falling time: 5ns

Input and output reference voltage:1.5V

Output load(see right): CL=100pF+1TTL

1. Including scope and jig capacitance

AC CHARACTERISTICS (K6T2008V2M Family: VCC=3.0~3.6V, K6T2008U2M Family: VCC=2.7~3.3V

Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C)

Speed Bins

Parameter List

Symbol

Units

70ns

Max

85ns

Max

100ns

Min

Max

Read cycle time

tRC

tAA

100

Address access time

100

Chip select to output

tCO1, tCO2

tOE

100

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

Write cycle time

Read

tLZ

tOLZ

tHZ

tOHZ

tOH

100

tWC

Chip select to end of write

Address set-up time

tCW

tAS

Address valid to end of write

Write pulse width

tAW

tWP

Write

Write recovery time

tWR

Write to output high-Z

tWHZ

tDW

Data to write time overlap

Data hold from write time

End write to output low-Z

tDH

tOW

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

Min

Typ

Max

Unit

Vcc for data retention

VDR

IDR

2.0

3.6

CS1 ³ Vcc-0.2V

Commercial

Industrial

Vcc=3.0V CS1³ Vcc-0.2V

CS2³ Vcc-0.2V or CS2£0.2V

Data retention current

0.2

Data retention set-up time

Recovery time

tSDR

tRDR

See data retention waveform

1. CS¹³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or CS2£0.2V(CS2 controlled)

Revision 1.0

November 1997

K6T2008V2M, K6T2008U2M Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS¹=OE=VIL, WE=VIH)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

CS1

tHZ(1,2)

CS2

tCO2

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 1.0

November 1997

K6T2008V2M, K6T2008U2M Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

CS1

tAW

CS2

tCW(2)

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS¹Controlled)

tWC

Address

CS1

tCW(2)

tAS(3)

tWR(4)

tAW

CS2

tWP(1)

tDW

tDH

Data in

Data out

Data Valid

High-Z

Revision 1.0

November 1997

K6T2008V2M, K6T2008U2M Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC

Address

CS1

tAS(3)

tCW(2)

tWR(4)

tAW

CS2

tCW(2)

tWP(1)

tDH

tDW

Data in

Data Valid

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS¹going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied

in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

3.0/2.7V¹⁾

2.2V

VDR

CS1³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

3.0/2.7V¹⁾

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

1. 3.0V for K6T2008V2M Family, 2.7V for K6T2008U2MFamily.

Revision 1.0

November 1997

K6T2008V2M, K6T2008U2M Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeters(inches)

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

+0.10

-0.05

+0.004

20.00±0.20

0.787±0.008

0.20

0.008

-0.002

#32

0.25

0.010

(

)

8.40

0.331

MAX

0.50

0.0197

#17

#16

1.00±0.10

0.039±0.004

0.05

0.002

MIN

1.20

MAX

0.047

18.40±0.10

0.724±0.004

0.25

0.010

TYP

+0.10

-0.05

0.15

+0.004

0.006

-0.002

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)

+0.10

-0.05

+0.004

0.20

13.40±0.10

0.528±0.008

0.008

-0.002

#32

0.25

0.010

(

)

8.40

0.331

MAX

0.50

0.0197

#17

#16

1.00±0.10

0.039±0.004

0.05

0.002

MIN

1.20

MAX

0.047

0.25

0.010

TYP

11.80±0.10

0.465±0.004

+0.10

-0.05

0.15

0.006^+0.004

-0.002

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

Revision 1.0

November 1997

K6T2008U2M-YB85T [SAMSUNG]

相关型号：

K6T2008U2M-YF85

K6T2008U2M-YF850

K6T2008V2A

K6T2008V2A-B

K6T2008V2A-F

K6T2008V2A-FF70

K6T2008V2A-FF70T

K6T2008V2A-FF85

K6T2008V2A-FF850

K6T2008V2A-FF85T

K6T2008V2A-TB70

K6T2008V2A-TB700