K6T2008V2A-YF10T [SAMSUNG]
Standard SRAM, 256KX8, 100ns, CMOS, PDSO32;
| 型号： | K6T2008V2A-YF10T |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 256KX8, 100ns, CMOS, PDSO32 静态存储器 光电二极管 |
| 文件： | 总10页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
Document Title
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
1.0
2.0
Design target
Finalize
May 26, 1998
Advance
October 8, 1998
July 21, 1999
Final
Final
Revised
- Add FBGA type package
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: TFT
The K6T2008V2A and K6T2008U2A families are fabricated by
SAMSUNG¢s advanced CMOS process technology. The fam-
ily support various operating temperature ranges and have
various package types for user flexibility of system design. The
family also support low data retention voltage for battery back-
up operation with low data retention current.
· Organization: 256Kx8
· Power Supply Voltage
K6T2008V2A Family: 3.0V~3.6V
K6T2008U2A Family: 2.7V~3.3V
· Low Data Retention Voltage: 2V(Min)
· Three state output and TTL Compatible
· Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F
48-FBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2,Max)
K6T2008V2A-B
K6T2008U2A-B
K6T2008V2A-F
K6T2008U2A-F
3.0~3.6V
70/85ns
Commercial(0~70°C)
10mA
15mA
32-TSOP1-0820F
32-TSOP1-0813.4F
48-FBGA-6.00x7.00
701)/85/100ns
2.7~3.3V
30mA2)
3.0~3.6V
701)/85/100ns
Industrial(-40~85°C)
2.7~3.3V
1. The parameters are tested with 30pF test load
2. K6T2008V2A Family = 35mA
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Precharge circuit.
A11
A9
A8
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A
B
C
D
E
F
A0
A1
A2
CS2
WE
NC
A3
A4
A5
A6
A7
A8
3
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
4
5
A16
A15
A14
I/O5
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
A14
6
7
8
32-TSOP1
I/O6
Vss
32-sTSOP1
Type - Forward
9
A13
A12
10
11
12
13
14
15
16
Memory array
1024 rows
256´ 8 columns
Row
select
A11
A10
A9
A6
A1
Vcc
I/O7
I/O8
A9
A5
A4
A2
A3
NC
CS1
A11
A17
A16
A12
A8
A7
G
H
OE
A15
A13
A10
I/O1
I/O8
Data
cont
I/O Circuit
Column select
48-FBGA: Top View (Ball Down)
Data
cont
Name
Function
Name
Function
CS1,CS2 Chip Select Inputs
I/O1~I/O8 Data Inputs/Outputs
OE
Output Enable Input
Write Enable Input
Vcc
Vss
Power
A0 A1 A17 A6 A5 A4 A3 A2
WE
Ground
A0~A17 Address Inputs
N.C.
No Connection
CS1
Control
logic
CS2
WE
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Industrial Temperature Products(-40~85°C)
Part Name
Function
Part Name
Function
K6T2008V2A-TB70
K6T2008V2A-TB85
32-TSOP1 F, 70ns, 3.3V,LL
32-TSOP1 F, 85ns, 3.3V,LL
K6T2008V2A-TF70
K6T2008V2A-TF85
K6T2008V2A-TF10
32-TSOP1 F, 70ns, 3.3V, LL
32-TSOP1 F, 85ns, 3.3V, LL
32-TSOP1 F, 100ns, 3.3V, LL
K6T2008U2A-TB70
K6T2008U2A-TB85
K6T2008U2A-TB10
32-TSOP1 F, 70ns, 3.0V, LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
K6T2008U2A-TF70
K6T2008U2A-TF85
K6T2008U2A-TF10
32-TSOP1 F, 70ns, 3.0V, LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
K6T2008V2A-YB70
K6T2008V2A-YB85
32-sTSOP1 F, 70ns, 3.3V,LL
32-sTSOP1 F, 85ns, 3.3V,LL
K6T2008V2A-YF70
K6T2008V2A-YF85
K6T2008V2A-YF10
32-sTSOP1 F, 70ns, 3.3V, LL
32-sTSOP1 F, 85ns, 3.3V, LL
32-sTSOP1 F, 100ns, 3.3V, LL
K6T2008U2A-YB70
K6T2008U2A-YB85
K6T2008U2A-YB10
32-sTSOP1 F, 70ns, 3.0V, LL
32-sTSOP1 F, 85ns, 3.0V, LL
32-sTSOP1 F, 100ns, 3.0V, LL
K6T2008U2A-YF70
K6T2008U2A-YF85
K6T2008U2A-YF10
32-sTSOP1 F, 70ns, 3.0V, LL
32-sTSOP1 F, 85ns, 3.0V, LL
32-sTSOP1 F, 100ns, 3.0V, LL
K6T2008V2A-FF70
K6T2008V2A-FF85
48-FBGA, 70ns, 3.3V, LL
48-FBGA, 85ns, 3.3V, LL
K6T2008U2A-FF70
K6T2008U2A-FF85
48-FBGA, 70ns, 3.0V, LL
48-FBGA, 85ns, 3.0V, LL
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Power
Standby
Standby
Active
X1)
L
X1)
X1)
H
High-Z
High-Z
High-Z
Dout
Deselected
Deselected
Output Disabled
Read
X1)
L
X1)
H
X1)
H
H
H
H
L
L
L
H
L
Active
X1)
Din
Write
Active
1. X means don¢t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOUT
VCC
Ratings
Unit
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
-0.5 to VCC+0.5
-0.3 to 4.6
1.0
V
V
-
-
-
-
PD
W
°C
°C
°C
Storage temperature
TSTG
-65 to 150
0 to 70
K6T2008V2A-L, K6T2008U2A-L
K6T2008V2A-P, K6T2008U2A-P
Operating Temperature
TA
-40 to 85
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
Min
Typ
Max
Unit
K6T2008V2A Family
K6T2008U2A Family
3.0
2.7
3.3
3.0
3.6
3.3
Supply voltage
Vcc
V
Ground
Vss
VIH
VIL
All Family
0
0
-
0
V
V
V
Input high voltage
Input low voltage
Note:
K6T2008V2A, K6T2008U2A Family
K6T2008V2A, K6T2008U2A Family
2.2
Vcc+0.3
0.6
-0.33)
-
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : Vcc+2.0V in case of pulse width£30ns
3. Undershoot : -2.0V in case of pulse width£30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
-
-
8
pF
pF
Input/Output capacitance
CIO
VIO=0V
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-
1
1
5
4
mA
mA
mA
mA
mA
V
Output leakage current
Operating power supply current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL
-1
-
-
ICC
-
ICC1
ICC2
VOL
VOH
ISB
-
-
Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V, CS2³ Vcc-0.2V, VIN£0.2V
Average operating current
301)
0.4
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL
-
25
-
Output low voltage
IOL=2.1mA
-
2.4
-
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
IOH=-1.0mA
-
-
V
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V, Other inputs=0~Vcc
-
0.3 mA
mA
102)
ISB1
-
0.2
1. K6T2008V2A Family = 35mA
2. Industrial product = 15mA
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
1)
CL
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
CL=30pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (K6T2008V2A Family: VCC=3.0~3.6V, K6T2008U2A Family: VCC=2.7~3.3V
Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
70ns
Max
85ns
Max
100ns
Min
70
-
Min
85
-
Min
Max
Read cycle time
tRC
tAA
-
70
70
35
-
-
85
85
40
-
100
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO1, tCO2
tOE
-
-
-
100
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
-
50
-
Read
tLZ
10
5
10
5
10
5
tOLZ
tHZ
-
-
-
0
25
25
-
0
25
25
-
0
30
30
-
tOHZ
tOH
0
0
0
10
70
60
0
15
85
70
0
15
100
80
0
tWC
-
-
-
Chip select to end of write
Address set-up time
tCW
-
-
-
tAS
-
-
-
Address valid to end of write
Write pulse width
tAW
60
55
0
-
70
60
0
-
80
70
0
-
tWP
-
-
-
Write
Write recovery time
tWR
-
-
-
Write to output high-Z
tWHZ
tDW
0
25
-
0
30
-
0
30
-
Data to write time overlap
Data hold from write time
End write to output low-Z
30
0
35
0
40
0
tDH
-
-
-
tOW
5
-
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
VDR
Test Condition
Min
2.0
-
Typ
Max
Unit
V
CS1³ Vcc-0.2V1)
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
-
0.2
-
3.6
102)
Vcc=3.0V, CS1³ Vcc-0.2V1)
IDR
mA
tSDR
0
-
-
See data retention waveform
ms
tRDR
5
-
1. CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or CS2£0.2V(CS2 controlled)
2. Industrial Products = 15mA
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
CS1
tCW(2)
tAS(3)
tWR(4)
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
CS1
tAS(3)
tCW(2)
tWR(4)
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V1)
2.2V
VDR
CS1³ VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
3.0/2.7V1)
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
1. 3.0V for K6T2008V2A Family, 2.7V for K6T2008U2A Family
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeter(inch)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
+0.004
20.00±0.20
0.787±0.008
0.20
0.008
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#17
#16
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
18.40±0.10
0.724±0.004
0.25
0.010
TYP
+0.10
-0.05
0.15
+0.004
0.006
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
+0.10
-0.05
+0.004
0.20
13.40±0.10
0.528±0.008
0.008
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#17
#16
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
TYP
11.80±0.10
0.465±0.004
+0.10
-0.05
0.15
0.006+0.004
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
CMOS SRAM
PACKAGE DIMENSIONS
48 BALL FINE PITCH BALL GRID ARRAY(6.00X7.00)
Top View
Units: millimeters
Bottom View
B
A1 INDEX MARK
0.50
B1
B
0.50
6
5
4
3
2
1
A
B
C
D
E
F
#A1
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.35
1.10
0.85
0.25
-
Max
-
A
B
-
Notes.
5.90
6.10
-
1. Bump counts: 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
B1
C
-
6.90
7.10
-
C1
D
-
4. Typ : Typical
0.30
0.40
1.20
-
5. Y is coplanarity: 0.08(Max)
E
-
E1
E2
Y
-
0.20
-
0.30
0.08
Revision 2.0
July 1999
相关型号：
©2020 ICPDF网 联系我们和版权申明