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K6T4008C1C-GL55T00 [SAMSUNG]

Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32;
K6T4008C1C-GL55T00
型号： K6T4008C1C-GL55T00
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32

静态存储器 光电二极管 内存集成电路
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CMOS SRAM  
K6T4008C1C Family  
Document Title  
512Kx8 bit Low Power CMOS Static RAM  
Revision History  
Revision No. History  
Draft Date  
Remark  
0.0  
Initial draft  
October 20,1998  
Preliminary  
1.0  
Finalize  
April 12, 1999  
Final  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.  
Revision 1.0  
1
April 1999  
CMOS SRAM  
K6T4008C1C Family  
512Kx8 bit Low Power CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
· Process Technology: TFT  
The K6T4008C1C families are fabricated by SAMSUNG¢s  
advanced CMOS process technology. The families support  
various operating temperature ranges and various package  
types for user flexibility of system design. The family also  
support low data retention voltage for battery back-up oper-  
ation with low data retention current.  
· Organization: 512Kx8  
· Power Supply Voltage: 4.5~5.5V  
· Low Data Retention Voltage: 2V(Min)  
· Three state output and TTL Compatible  
· Package Type: 32-DIP-600, 32-SOP-525,  
32-TSOP2-400F/R  
PRODUCT FAMILY  
Power Dissipation  
Product Family  
Operating Temperature  
Vcc Range  
Speed  
PKG Type  
Standby  
(ISB1, Max)  
Operating  
(ICC2, Max)  
K6T4008C1C-L  
K6T4008C1C-B  
K6T4008C1C-P  
K6T4008C1C-F  
80mA  
20mA  
100mA  
30mA  
32-DIP,32-SOP  
32-TSOP2-F/R  
Commercial (0~70°C)  
Inderstrial (-40~85°C)  
551)/70ns  
4.5~5.5V  
55mA  
32-SOP  
32-TSOP2-F/R  
1. The parameter is measured with 50pF test load.  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
A18  
A16  
A14  
A12  
A7  
VCC  
A15  
A17  
WE  
A13  
A8  
1
VCC  
A15  
A17  
Clk gen.  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
A18  
Precharge circuit.  
2
2
3
A16  
A14  
A12  
A7  
3
4
WE  
A13  
A8  
4
5
5
Memory array  
1024 rows  
512´ 8 columns  
6
A6  
6
A6  
Row  
select  
32-DIP  
32-SOP  
32-TSOP2  
7
A9  
A9  
A5  
7
A5  
32-TSOP2  
(Reverse)  
A4  
8
A11  
OE  
A11  
OE  
8
A4  
A3  
9
9
A3  
(Forward)  
A10  
CS  
A2  
10  
11  
12  
13  
14  
15  
16  
A10  
CS  
10  
11  
12  
13  
14  
15  
16  
A2  
A1  
A1  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A0  
A0  
I/O1  
I/O8  
Data  
cont  
I/O Circuit  
I/O1  
I/O2  
I/O3  
VSS  
I/O1  
I/O2  
I/O3  
VSS  
Column select  
Data  
cont  
Pin Name  
WE  
Function  
Write Enable Input  
Chip Select Input  
Output Enable Input  
Address Inputs  
Data Inputs/Outputs  
Power  
CS  
CS  
WE  
OE  
Control  
logic  
OE  
A0~A18  
I/O1~I/O8  
Vcc  
Vss  
Ground  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
Revision 1.0  
April 1999  
2
CMOS SRAM  
K6T4008C1C Family  
PRODUCT LIST  
Commercial Temperature Products(0~70°C)  
Industrial Temperature Products(-40~85°C)  
Part Name Function  
K6T4008C1C-GP55 32-SOP, 55ns, Low Power  
K6T4008C1C-GF55 32-SOP, 55ns, Low Low Power  
K6T4008C1C-GP70 32-SOP, 70ns, Low Power  
Part Name  
Function  
K6T4008C1C-DL55  
K6T4008C1C-DB55  
K6T4008C1C-DL70  
K6T4008C1C-DB70  
32-DIP, 55ns, Low Power  
32-DIP, 55ns, Low Low Power  
32-DIP, 70ns, Low Power  
32-DIP, 70ns, Low Low Power  
K6T4008C1C-GF70  
32-SOP, 70ns, Low Low Power  
K6T4008C1C-GL55  
32-SOP, 55ns, Low Power  
K6T4008C1C-VF55  
K6T4008C1C-VF70  
K6T4008C1C-MF55 32-TSOP2-R, 55ns, Low Low Power  
K6T4008C1C-MF70 32-TSOP2-R, 70ns, Low Low Power  
32-TSOP2-F, 55ns, Low Low Power  
32-TSOP2-F, 70ns, Low Low Power  
K6T4008C1C-GB55 32-SOP, 55ns, Low Low Power  
K6T4008C1C-GL70 32-SOP, 70ns, Low Power  
K6T4008C1C-GB70 32-SOP, 70ns, Low Low Power  
K6T4008C1C-VB55  
K6T4008C1C-VB70  
32-TSOP2-F, 55ns, Low Low Power  
32-TSOP2-F, 70ns, Low Low Power  
K6T4008C1C-MB55 32-TSOP2-R, 55ns, Low Low Power  
K6T4008C1C-MB70 32-TSOP2-R, 70ns, Low Low Power  
FUNCTIONAL DESCRIPTION  
CS  
H
L
OE  
WE  
I/O Pin  
High-Z  
High-Z  
Dout  
Mode  
Deselected  
Output disbaled  
Read  
Power  
Standby  
Active  
X1)  
H
X1)  
H
L
L
H
L
Active  
X1)  
L
Din  
Write  
Active  
1. X means don¢t care.( Must be in low or high state.)  
ABSOLUTE MAXIMUM RATINGS1)  
Item  
Voltage on any pin relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
Symbol  
Ratings  
Unit  
V
Remark  
VIN,VOUT  
VCC  
-0.5 to 7.0  
-0.5 to 7.0  
1.0  
-
V
-
PD  
W
-
Storage temperature  
TSTG  
-65 to 150  
0 to 70  
°C  
°C  
°C  
-
K6T4008C1C-L/-B  
K6T4008C1C-P/-F  
Operating Temperature  
TA  
-40 to 85  
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be  
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
Revision 1.0  
3
April 1999  
CMOS SRAM  
K6T4008C1C Family  
RECOMMENDED DC OPERATING CONDITIONS1)  
Item  
Symbol  
Vcc  
Min  
4.5  
0
Typ  
Max  
Unit  
V
Supply voltage  
Ground  
5.0  
5.5  
0
Vss  
0
-
V
Vcc+0.52)  
0.8  
Input high voltage  
Input low voltage  
VIH  
2.2  
V
-0.53)  
VIL  
-
V
Note:  
1. Commercial Product : TA=0 to 70°C, otherwise specified  
Industrial Product : TA=-40 to 85°C, otherwise specified  
2. Overshoot : VCC+3.0V in case of pulse width £ 30ns  
3. Undershoot : -3.0V in case of pulse width £ 30ns  
4. Overshoot and undershoot are sampled, not 100% tested.  
CAPACITANCE1) (f=1MHz, TA=25°C)  
Item  
Input capacitance  
Symbol  
CIN  
Test Condition  
VIN=0V  
Min  
Max  
8
Unit  
pF  
-
-
Input/Output capacitance  
CIO  
VIO=0V  
10  
pF  
1. Capacitance is sampled, not 100% tested  
DC AND OPERATING CHARACTERISTICS  
Item  
Symbol  
ILI  
Test Conditions  
Min  
-1  
-1  
-
Typ  
Max  
Unit  
mA  
Input leakage current  
VIN=Vss to Vcc  
-
-
-
1
1
Output leakage current  
Operating power supply current  
ILO  
CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc  
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read  
mA  
ICC  
10  
mA  
Cycle time=1ms, 100% duty, IIO=0mA  
CS£0.2V, VIN³ 0.2V or VIN³ Vcc-0.2V  
ICC1  
-
-
8
mA  
Average operating current  
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL  
IOL=2.1mA  
ICC2  
VOL  
VOH  
ISB  
-
-
-
-
-
-
-
-
-
55  
0.4  
-
mA  
V
Output low voltage  
Output high voltage  
Standby Current(TTL)  
-
IOH=-1.0mA  
2.4  
V
CS=VIH, Other inputs = VIL or VIH  
K6T4008C1C-L  
-
-
-
-
-
3
mA  
80  
20  
100  
30  
K6T4008C1C-B  
Standby Current(CMOS)  
ISB1  
CS³ Vcc-0.2V, Other inputs=0~Vcc  
mA  
K6T4008C1C-P  
K6T4008C1C-F  
Revision 1.0  
April 1999  
4
CMOS SRAM  
K6T4008C1C Family  
AC OPERATING CONDITIONS  
TEST CONDITIONS (Test Load and Test Input/Output Reference)  
Input pulse level : 0.8 to 2.4V  
Input rising and falling time : 5ns  
1)  
CL  
Input and output reference voltage : 1.5V  
Output load (See right) :CL=100pF+1TTL  
CL=50pF+1TTL  
1. Including scope and jig capacitance  
AC CHARACTERISTICS (Vcc=4.5~5.5V, K6T4008C1C-C Family:TA=0 to 70°C, K6T4008C1C-I Family:TA=-40 to 85°C)  
Speed Bins  
Parameter List  
Symbol  
Units  
55ns  
70ns  
Min  
55  
-
Max  
Min  
70  
-
Max  
Read cycle time  
tRC  
tAA  
-
55  
55  
25  
-
-
70  
70  
35  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
Chip select to output  
tCO  
tOE  
-
-
Output enable to valid output  
Chip select to low-Z output  
Output enable to low-Z output  
Chip disable to high-Z output  
Output disable to high-Z output  
Output hold from address change  
Write cycle time  
-
-
Read  
tLZ  
10  
5
10  
5
tOLZ  
tHZ  
-
-
0
20  
20  
-
0
25  
25  
-
tOHZ  
tOH  
tWC  
tCW  
tAS  
0
0
10  
55  
45  
0
10  
70  
60  
0
-
-
Chip select to end of write  
Address set-up time  
-
-
-
-
Address valid to end of write  
Write pulse width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
tOW  
45  
40  
0
-
60  
50  
0
-
-
-
Write  
Write recovery time  
-
-
Write to output high-Z  
0
20  
-
0
25  
-
Data to write time overlap  
Data hold from write time  
End write to output low-Z  
25  
0
30  
0
-
-
5
-
5
-
DATA RETENTION CHARACTERISTICS  
Item  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Vcc for data retention  
VDR  
CS³ Vcc-0.2V  
2.0  
-
-
-
-
-
-
-
5.5  
40  
15  
50  
20  
-
V
K6T4008C1C-L  
K6T4008C1C-B  
K6T4008C1C-P  
K6T4008C1C-F  
-
-
Data retention current  
IDR  
Vcc=3.0V, CS³ Vcc-0.2V  
mA  
-
-
Data retention set-up time  
Recovery time  
tSDR  
tRDR  
0
5
See data retention waveform  
ms  
-
Revision 1.0  
April 1999  
5
CMOS SRAM  
K6T4008C1C Family  
TIMMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)  
tRC  
Address  
tAA  
tOH  
Data Valid  
Data Out  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tOH  
tAA  
tCO1  
CS  
tHZ  
tOE  
OE  
tOLZ  
tLZ  
tOHZ  
High-Z  
Data out  
Data Valid  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
Revision 1.0  
April 1999  
6
CMOS SRAM  
K6T4008C1C Family  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
Address  
tCW(2)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tAS(3)  
tDW  
tDH  
Data Valid  
Data in  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)  
tWC  
Address  
tCW(2)  
tAS(3)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tDW  
tDH  
Data in  
Data Valid  
High-Z  
Data out  
High-Z  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE  
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write  
to the end of write.  
2. tCW is measured from the CS going low to end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
DATA RETENTION WAVE FORM  
CS controlled  
Data Retention Mode  
tSDR  
tRDR  
VCC  
4.5V  
2.2V  
VDR  
CS³ VCC - 0.2V  
CS  
GND  
Revision 1.0  
April 1999  
7
CMOS SRAM  
K6T4008C1C Family  
PACKAGE DIMENSIONS  
Units : millimeter(Inch)  
32 PIN DUAL INLINE PACKAGE (600mil)  
+0.10  
-0.05  
0.25  
+0.004  
-0.002  
0.010  
#32  
#17  
13.60±0.20  
0.535±0.008  
#1  
#16  
0~15°  
3.81±0.20  
0.150±0.008  
42.31  
1.666  
MAX  
5.08  
0.200  
MAX  
41.91±0.20  
1.650±0.008  
3.30±0.30  
0.130±0.012  
0.46±0.10  
0.018±0.004  
0.38  
0.015  
1.91  
0.075  
1.52±0.10  
0.060±0.004  
2.54  
0.100  
MIN  
(
)
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)  
0~8°  
#32  
#17  
14.12±0.30  
11.43±0.20  
0.450±0.008  
0.556±0.012  
#1  
#16  
0.80±0.20  
+0.10  
-0.05  
0.20  
2.74±0.20  
0.031±0.008  
20.87  
MAX  
0.108±0.008  
+0.004  
0.822  
0.008  
-0.002  
3.00  
0.118  
MAX  
20.47±0.20  
0.806±0.008  
0.10 MAX  
0.004 MAX  
+0.100  
-0.050  
0.41  
0.71  
0.028  
1.27  
0.050  
+0.004  
-0.002  
(
)
0.05  
MIN  
0.016  
0.002  
Revision 1.0  
April 1999  
8
CMOS SRAM  
K6T4008C1C Family  
PACKAGE DIMENSIONS  
Units : millimeter(Inch)  
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)  
0~8°  
0.25  
0.010  
(
)
#32  
#17  
0.45 ~0.75  
0.018 ~ 0.030  
11.76±0.20  
0.463±0.008  
#1  
#16  
0.50  
0.020  
(
)
+0.10  
-0.05  
+0.004  
-0.002  
0.15  
21.35  
MAX  
0.841  
1.00±0.10  
0.039±0.004  
0.006  
1.20  
0.047  
20.95±0.10  
0.825±0.004  
MAX  
0.10 MAX  
0.004 MAX  
0.05  
0.002  
MIN  
1.27  
0.050  
0.95  
0.037  
0.40±0.10  
0.016±0.004  
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)  
0~8°  
0.25  
(
)
0.010  
#1  
#16  
0.45 ~0.75  
0.018 ~ 0.030  
11.76±0.20  
0.463±0.008  
#32  
#17  
0.50  
0.020  
(
)
+0.10  
0.15  
-0.05  
21.35  
MAX  
1.00 ±0.10  
0.039±0.004  
+0.004  
-0.002  
0.841  
0.006  
1.20  
0.047  
20.95±0.10  
0.825±0.004  
MAX  
0.10 MAX  
0.004 MAX  
1.27  
0.050  
0.95  
0.037  
0.05  
0.002  
0.40±0.10  
0.016±0.004  
MIN  
(
)
Revision 1.0  
April 1999  
9

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