K6T4008U1C-YF85T [SAMSUNG]
Standard SRAM, 512KX8, 85ns, CMOS, PDSO32;
| 型号： | K6T4008U1C-YF85T |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 512KX8, 85ns, CMOS, PDSO32 静态存储器 光电二极管 |
| 文件： | 总10页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6T4008V1C, K6T4008U1C Family
CMOS SRAM
Document Title
512Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
0.1
Initial Draft
January 13, 1998
June 12, 1998
Advance
Revisied
Preliminary
- Speed bin change
KM68U4000C : 85/100ns ® 70/85/100ns
- DC Characteristics change
ICC : 5mA at read/write ® 4mA at read
ICC1 : 3mA ® 4mA
ICC2 : 35mA ® 30mA
ISB : 0.5mA ® 0.3mA
ISB1 : 10mA ® 15mA for commercial parts
- Add 32-TSOP1-0820
0.11
1.0
Errata correct
- 32-TSOP1-0813 products: T ® TG
November 7, 1998
January 15, 1999
Finalize
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
January 1999
K6T4008V1C, K6T4008U1C Family
CMOS SRAM
512K´ 8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: TFT
The K6T4008V1C and K6T4008U1C families are fabricated by
SAMSUNG¢s advanced CMOS process technology. The fami-
lies support various operating temperature range and have var-
ious package type for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
· Organization: 512K´ 8
· Power Supply Voltage
K6T4008V1C Family: 3.0~3.6V
K6T4008U1C Family: 2.7~3.3V
· Low Data Retention Voltage: 2V(Min)
· Three state output and TTL Compatible
· Package Type: 32-SOP-525, 32-TSOP2-400F/R
32-TSOP1-0820F, 32-TSOP1-0813.4F
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
701)/85ns
701)/85/100ns
701)/85ns
K6T4008V1C-B
K6T4008U1C-B
K6T4008V1C-F
K6T4008U1C-F
3.0~3.6V
32-SOP
Commercial(0~70°C)
15mA
20mA
2.7~3.3V
32-TSOP2-F/R
32-TSOP1-F
32-sTSOP1-F
30mA
3.0~3.6V
Industrial(-40~85°C)
701)/85/100ns
2.7~3.3V
1. The paramerter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A18
A16
A14
A12
A7
1
VCC
A15
A17
WE
A13
A8
VCC
A15
A17
WE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
1
2
A18
A16
A14
A12
A7
Clk gen.
Precharge circuit.
2
3
3
4
4
A0
A1
A4
5
A13 28
5
A6
6
A8
A9
27
26
6
A6
A5
7
A9
7
A5
32-TSOP2
(Reverse)
32-SOP
32-TSOP2
(Forward)
A11
OE
A11 25
A5
A6
A4
8
8
A4
Memory array
1024 rows
512´ 8 columns
Row
select
24
23
22
21
20
19
18
17
A3
9
OE
A10
CS
9
A3
A2
10
11
12
13
14
15
16
A10
CS
10
11
12
13
14
15
16
A2
A7
A1
A1
A12
A14
A16
A0
I/O8
I/O7
I/O6
I/O5
I/O4
I/O8
I/O7
I/O6
I/O5
I/O4
A0
I/O1
I/O2
I/O3
VSS
I/O1
I/O2
I/O3
VSS
A18
I/O1
I/O8
Data
cont
I/O Circuit
A11
A9
A8
1
2
3
4
5
6
7
8
9
32
OE
A10
CS
Column select
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
Data
cont
32-TSOP1
32-STSOP1
(Forward)
10
A2 A3 A8 A9 A10 A11 A13 A15 A17
11
12
13
14
15
16
A6
A5
A4
A1
A2
A3
CS
Control
logic
WE
OE
Name Function
Name Function
A0~A18 Address Inputs
Vcc
Vss
Power
WE
CS
OE
Write Enable Input
Chip Select Input
Output Enable Input
Ground
I/O1~I/O8 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
January 1999
K6T4008V1C, K6T4008U1C Family
CMOS SRAM
PRODUCT LIST
Commercial Temp Products(0~70°C)
Industrial Temp Products(-40~85°C)
Part Name
Function
Part Name
Function
K6T4008V1C-GB70
K6T4008V1C-GB85
K6T4008V1C-VB70
K6T4008V1C-VB85
K6T4008V1C-MB70
K6T4008V1C-MB85
K6T4008V1C-TB70
K6T4008V1C-TB85
K6T4008V1C-YB70
K6T4008V1C-YB85
32-SOP, 70ns, 3.3V, LL
K6T4008V1C-GF70
K6T4008V1C-GF85
K6T4008V1C-VF70
K6T4008V1C-VF85
K6T4008V1C-MF70
K6T4008V1C-MF85
K6T4008V1C-TF70
K6T4008V1C-TF85
K6T4008V1C-YF70
K6T4008V1C-YF85
32-SOP, 70ns, 3.3V, LL
32-SOP, 85ns, 3.3V, LL
32-SOP, 85ns, 3.3V, LL
32-TSOP2-F, 70ns, 3.3V, LL
32-TSOP2-F, 85ns, 3.3V, LL
32-TSOP2-R, 70ns, 3.3V, LL
32-TSOP2-R, 85ns, 3.3V, LL
32-TSOP1-F, 70ns, 3.3V, LL
32-TSOP1-F, 85ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F, 85ns, 3.3V, LL
32-TSOP2-F, 70ns, 3.3V, LL
32-TSOP2-F, 85ns, 3.3V, LL
32-TSOP2-R, 70ns, 3.3V, LL
32-TSOP2-R, 85ns, 3.3V, LL
32-TSOP1-F, 70ns, 3.3V, LL
32-TSOP1-F, 85ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F, 85ns, 3.3V, LL
K6T4008U1C-GB70
K6T4008U1C-GB85
K6T4008U1C-GB10
K6T4008U1C-VB70
K6T4008U1C-VB85
K6T4008U1C-VB10
K6T4008U1C-MB70
K6T4008U1C-MB85
K6T4008U1C-MB10
K6T4008U1C-TB70
K6T4008U1C-TB85
K6T4008U1C-TB10
K6T4008U1C-YB70
K6T4008U1C-YB85
K6T4008U1C-YB10
32-SOP, 70ns, 3.0V, LL
K6T4008U1C-GF70
K6T4008U1C-GF85
K6T4008U1C-GF10
K6T4008U1C-VF70
K6T4008U1C-VF85
K6T4008U1C-VF10
K6T4008U1C-MF70
K6T4008U1C-MF85
K6T4008U1C-MF10
K6T4008U1C-TF70
K6T4008U1C-TF85
K6T4008U1C-TF10
K6T4008U1C-YF70
K6T4008U1C-YF85
K6T4008U1C-YF10
32-SOP, 70ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP2-F, 70ns, 3.0V, LL
32-TSOP2-F, 85ns, 3.0V, LL
32-TSOP2-F, 100ns, 3.0V, LL
32-TSOP2-R, 70ns, 3.0V, LL
32-TSOP2-R, 85ns, 3.0V, LL
32-TSOP2-R, 100ns, 3.0V, LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL
32-TSOP2-F, 70ns, 3.0V, LL
32-TSOP2-F, 85ns, 3.0V, LL
32-TSOP2-F, 100ns, 3.0V, LL
32-TSOP2-R, 70ns, 3.0V, LL
32-TSOP2-R, 85ns, 3.0V, LL
32-TSOP2-R, 100ns, 3.0V, LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL
FUNCTIONAL DESCRIPTION
CS
H
L
OE
WE
I/O
High-Z
High-Z
Dout
Mode
Power
Standby
Active
X1)
H
X1)
H
Deselected
Output Disabled
Read
L
L
H
L
Active
X1)
L
Din
Write
Active
1. X means don¢t care (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOUT
VCC
Ratings
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
-0.5 to VCC+0.5
-0.3 to 4.6
1.0
-
V
-
PD
W
-
Storage temperature
TSTG
-65 to 150
0 to 70
°C
°C
°C
-
K6T4008V1C-L, K6T4008U1C-L
K6T4008V1C-P, K6T4008U1C-P
Operating Temperature
TA
-40 to 85
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
January 1999
K6T4008V1C, K6T4008U1C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
Min
Typ
Max
Unit
K6T4008V1C Family
K6T4008U1C Family
3.0
2.7
3.3
3.0
3.6
3.3
Supply voltage
Vcc
V
Ground
Vss
VIH
VIL
All Family
0
0
-
0
V
V
V
Vcc+0.32)
0.6
Input high voltage
Input low voltage
Note:
K6T4008V1C, K6T4008U1C Family
K6T4008V1C, K6T4008U1C Family
2.2
-0.33)
-
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+2.0V in case of pulse width £ 30ns
3. Undershoot : -2.0V in case of pulse width £ 30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
-
-
8
pF
pF
Input/Output capacitance
CIO
VIO=0V
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
Output leakage current
Operating power supply current
VIN=Vss to Vcc
-1
-
-
-
-
-
-
-
-
-
1
1
mA
mA
mA
mA
mA
V
ILO
CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read
-1
ICC
-
4
Cycle time=1ms, 100% duty, IIO=0mA CS£0.2V,VIN£0.2V or VIN³ Vcc-0.2V
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
IOL=2.1mA
ICC1
ICC2
VOL
VOH
ISB
-
4
Average operating current
-
30
0.4
-
Output low voltage
Output high voltage
Standby Current(TTL)
-
2.2
-
IOH=-1.0mA
V
CS=VIH, Other inputs = VIL or VIH
CS³ Vcc-0.2V, Other inputs=0~Vcc
0.3 mA
mA
151)
Standby Current (CMOS)
ISB1
-
1. Industrial product = 20mA
4
Revision 1.0
January 1999
K6T4008V1C, K6T4008U1C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
1)
CL
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
1)
CL =30pF+1TTL
1. Including scope and jig capacitance
1. 70ns product
AC CHARACTERISTICS (K6T4008V1C Family: Vcc=3.0~3.6V, K6T4008U1C Family: Vcc=2.7~3.3V
Commercial product:: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
70ns
Max
85ns
Max
100ns
Min
70
-
Min
85
-
Min
Max
Read cycle time
tRC
tAA
-
70
70
35
-
-
85
85
40
-
100
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO
tOE
-
-
-
100
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
-
50
-
Read
tLZ
10
5
10
5
10
5
tOLZ
tHZ
-
-
-
0
25
25
-
0
25
25
-
0
30
30
-
tOHZ
tOH
tWC
tCW
tAS
0
0
0
10
70
60
0
10
85
70
0
15
100
80
0
-
-
-
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
60
55
0
-
70
55
0
-
80
70
0
-
-
-
-
Write
Write recovery time
-
-
-
Write to output high-Z
0
25
-
0
25
-
0
30
-
Data to write time overlap
Data hold from write time
End write to output low-Z
30
0
35
0
40
0
-
-
-
tOW
5
-
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
CS³ Vcc-0.2V
Vcc=3.0V, CS³ Vcc-0.2V
Min
2.0
-
Typ
Max
Unit
V
Vcc for data retention
Data retention current
Data retention set-up time
VDR
-
0.5
-
3.6
151)
-
IDR
mA
tSDR
0
See data retention waveform
ms
Recovery time
tRDR
5
-
-
1. Industrial product = 20mA
5
Revision 1.0
January 1999
K6T4008V1C, K6T4008U1C Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS
tHZ
tOE
OE
tOLZ
tLZ
tOHZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
January 1999
K6T4008V1C, K6T4008U1C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS
tAW
tWP(1)
WE
tDW
tDH
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
7
Revision 1.0
January 1999
K6T4008V1C, K6T4008U1C Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
#17
11.43±0.20
0.450±0.008
14.12±0.30
0.556±0.012
0.80±0.20
0.031±0.008
+0.10
-0.05
#1
#16
0.20
2.74±0.20
0.108±0.008
20.87
0.822
+0.004
0.008
MAX
-0.002
3.00
MAX
0.118
20.47±0.20
0.806±0.008
0.10 MAX
0.004 MAX
+0.100
-0.050
0.41
1.27
0.050
0.71
0.028
+0.004
-0.002
0.05
0.002
(
)
0.016
MIN
8
Revision 1.0
January 1999
K6T4008V1C, K6T4008U1C Family
PACKAGE DIMENSIONS
CMOS SRAM
Units: millimeters(inches)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
+0.004
20.00±0.20
0.787±0.008
0.20
0.008
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#17
#16
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
18.40±0.10
0.724±0.004
0.25
0.010
TYP
+0.10
-0.05
0.15
+0.004
0.006
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
+0.10
-0.05
+0.004
0.20
13.40±0.10
0.528±0.008
0.008
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#16
#17
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
TYP
11.80±0.10
0.465±0.004
+0.10
-0.05
0.15
0.006+0.004
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
9
Revision 1.0
January 1999
K6T4008V1C, K6T4008U1C Family
PACKAGE DIMENSIONS
CMOS SRAM
Units: millimeters(inches)
0~8°
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0.25
0.010
(
)
#32
#17
0.45~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
#1
#16
0.50
0.020
(
)
+0.10
-0.05
+0.004
-0.002
0.15
21.35
0.841
1.00±0.10
0.039±0.004
MAX
0.006
1.20
0.047
20.95±0.10
0.825±0.004
MAX
0.10 MAX
0.004 MAX
0.05
0.002
MIN
1.27
0.050
0.95
0.037
0.40±0.10
0.016±0.004
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0~8°
0.25
0.010
(
)
#1
#16
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
#32
#17
0.50
0.020
(
)
+0.10
-0.05
+0.004
-0.002
0.15
21.35
0.841
1.00±0.10
0.039±0.004
MAX
0.006
1.20
0.047
20.95±0.10
0.825±0.004
MAX
0.10 MAX
0.004 MAX
1.27
0.050
0.05
0.002
0.40±0.10
0.016±0.004
0.95
0.037
MIN
(
)
10
Revision 1.0
January 1999
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