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K6X0808T1D-GF700 [SAMSUNG]

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, SOP-28;
K6X0808T1D-GF700
型号： K6X0808T1D-GF700
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, SOP-28

静态存储器 光电二极管 内存集成电路
文件： 总9页 (文件大小：110K)
中文：  中文翻译
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K6X0808T1D Family  
CMOS SRAM  
Document Title  
32Kx8 bit Low Power CMOS Static RAM  
Revision History  
Revision No. History  
Draft Data  
Remark  
0.0  
Initial draft  
October 09, 2002  
Preliminary  
0.1  
revised  
November 08, 2002  
Preliminary  
- errata : corrected 28-SOP-525 to 28-SOP-450 in pakage type  
0.2  
1.0  
revised  
- Added commercial product.  
March 27, 2003  
Preliminary  
Final  
Finalized  
December 16, 2003  
- Changed ICC from 3mA to 2mA  
- Changed ICC2 from 25mA to 20mA  
- Changed ISB from 3mA to 0.4mA  
- Changed ISB1 for K6X0808T1D-F from 10µA to 6µA  
- Changed ISB1 for K6X0808T1D-F from 20µA to 10µA  
- Changed IDR for K6X0808T1D-F 10µA to 6µA  
- Changed IDR for K6X0808T1D-Q 20µA to 10µA  
- Errata correction  
2.0  
Revised  
March 27, 2005  
Final  
- Changed ISB1 of Automotive product from 10µA to 25µA  
- Changed IDR of Automotive product from 10µA to 25µA  
- Added Lead Free Products  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and  
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.  
1
Revision 2.0  
March 2005  
K6X0808T1D Family  
CMOS SRAM  
32Kx8 bit Super Low Power and Low Voltage full CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
• Process Technology: Full CMOS28-  
• Organization: 32K x 8  
The K6X0808T1D families are fabricated by SAMSUNG′s  
advanced CMOS process technology. The families support  
verious operating temperature ranges and have various pack-  
age types for user flexibility of system design. The families  
also support low data retention voltage for battery back-up  
operation with low data retention current.  
• Power Supply Voltage: 2.7~3.6V  
• Low Data Retention Voltage: 1.5V(Min)  
• Three state outputs  
• Package Type: 28-SOP-450, 28-TSOP1-0813.4F/R  
PRODUCT FAMILY  
Power Dissipation  
PKG Type  
Product Family Operating Temperature Vcc Range Speed  
Standby  
Operating  
(ISB1, Max) (ICC2, Max)  
K6X0808T1D-B  
K6X0808T1D-F  
K6X0808T1D-Q  
Industrial(0~70°C)  
Industrial(-40~85°C)  
Automotive(-40~125°C)  
28-SOP-450, 28-TSOP1-0813.4F/R  
28-SOP-450, 28-TSOP1-0813.4F  
6µA  
701)/85ns  
2.7~3.6V  
25mA  
25µA  
1. The parameters are tested with 30pF test load  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A10  
CS  
OE  
A11  
A9  
2
Clk gen.  
Precharge circuit.  
3
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
VSS  
I/O3  
I/O2  
I/O1  
A0  
4
A8  
A14  
A12  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
WE  
A13  
A8  
5
A13  
WE  
VCC  
A14  
A12  
A7  
6
2
28-TSOP  
Type1 - Forward  
7
8
3
9
Row  
select  
4
A6  
10  
11  
12  
13  
14  
Row  
Addresses  
Memory array  
A6  
5
A5  
A9  
A5  
A1  
A4  
6
A11  
OE  
A4  
A2  
A3  
7
A3  
28-SOP  
8
14  
13  
12  
11  
10  
9
A3  
A4  
A10  
CS  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A2  
A2  
A1  
9
A1  
A5  
A0  
I/O1  
I/O8  
Data  
cont  
I/O Circuit  
A6  
I/O1  
I/O2  
I/O3  
VSS  
I/O4  
I/O5  
I/O6  
I/O7  
I/O8  
CS  
10  
11  
12  
13  
14  
Column select  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A0  
A7  
A12  
A14  
VCC  
WE  
A13  
A8  
I/O1  
I/O2  
I/O3  
VSS  
8
28-TSOP  
Type1 - Reverse  
Data  
cont  
7
6
5
4
Column Addresses  
A9  
3
A11  
2
1
A10  
OE  
CS1  
WE  
OE  
Control  
logic  
Pin Name  
A0~A14  
WE  
Function  
Pin Name  
Function  
Address Inputs  
I/O1~I/O8 Data Inputs/Outputs  
Write Enable Input  
Chip Select Input  
Output Enable Input  
Vcc  
Vss  
NC  
Power  
CS  
Ground  
OE  
No connect  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
2
Revision 2.0  
March 2005  
K6X0808T1D Family  
CMOS SRAM  
PRODUCT LIST  
Commercial Temp. Products(0~70°C)  
Industrial Temp. Products(-40~85°C)  
Atomotive Temp. Products(-40~125°C)  
Part Name  
Function  
Part Name  
Function  
Part Name  
Function  
K6X0808T1D-GB70  
K6X0808T1D-GB85  
K6X0808T1D-BB701)  
K6X0808T1D-BB851)  
K6X0808T1D-YB70  
K6X0808T1D-YB85  
K6X0808T1D-LB701)  
K6X0808T1D-LB851)  
K6X0808T1D-NB70  
K6X0808T1D-NB85  
28-SOP, 70ns, LL  
28-SOP, 85ns, LL  
K6X0808T1D-GF70  
K6X0808T1D-GF85  
K6X0808T1D-GF701)  
K6X0808T1D-GF851)  
K6X0808T1D-YF70  
K6X0808T1D-YF85  
K6X0808T1D-LF701)  
K6X0808T1D-LF851)  
K6X0808T1D-NF70  
K6X0808T1D-NF85  
28-SOP, 70ns, LL  
28-SOP, 85ns, LL  
K6X0808T1D-GQ70  
K6X0808T1D-GQ85  
K6X0808T1D-GQ701)  
K6X0808T1D-GQ851)  
K6X0808T1D-YQ70  
K6X0808T1D-YQ85  
K6X0808T1D-LQ701)  
K6X0808T1D-LQ851)  
28-SOP, 70ns, L  
28-SOP, 85ns, L  
28-SOP, 70ns, LL, LF  
28-SOP, 85ns, LL, LF  
28-sTSOP-F, 70ns, LL  
28-sTSOP-F, 85ns, LL  
28-sTSOP-F, 70ns, LL, LF  
28-sTSOP-F, 85ns, LL, LF  
28-sTSOP-R, 70ns, LL  
28-sTSOP-R, 85ns, LL  
28-SOP, 70ns, LL, LF  
28-SOP, 85ns, LL, LF  
28-sTSOP-F, 70ns, LL  
28-sTSOP-F, 85ns, LL  
28-sTSOP-F, 70ns, LL, LF  
28-sTSOP-F, 85ns, LL, LF  
28-sTSOP-R, 70ns, LL  
28-sTSOP-R, 85ns, LL  
28-SOP, 70ns, L, LF  
28-SOP, 85ns, L, LF  
28-sTSOP-F, 70ns, L  
28-sTSOP-F, 85ns, L  
28-sTSOP-F, 70ns, L, LF  
28-sTSOP-F, 85ns, L, LF  
1.Lead Free Products (LF)  
FUNCTIONAL DESCRIPTION  
CS  
H
L
OE  
X1)  
H
WE  
I/O  
Mode  
Deselected  
Output Disabled  
Read  
Power  
Standby  
Active  
X1)  
H
High-Z  
High-Z  
Dout  
Din  
L
L
H
Active  
X1)  
L
L
Write  
Active  
1. X means don't care (Must be in high or low states)  
ABSOLUTE MAXIMUM RATINGS1)  
Item  
Symbol  
Ratings  
Unit  
Remark  
Voltage on any pin relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
VIN,VOUT  
VCC  
-0.2 to VCC+0.3V(Max. 3.9V)  
V
V
-
-0.2 to 3.9  
1.0  
-
PD  
W
°C  
°C  
°C  
-
Storage temperature  
TSTG  
-65 to 150  
-40 to 85  
-40 to 125  
-
K6X0808T1D-F  
K6X0808T1D-Q  
Operating Temperature  
TA  
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be  
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
3
Revision 2.0  
March 2005  
K6X0808T1D Family  
CMOS SRAM  
RECOMMENDED DC OPERATING CONDITIONS1)  
Item  
Symbol  
Vcc  
Min  
2.7  
0
Typ  
Max  
3.6  
0
Unit  
V
Supply voltage  
Ground  
3.0/3.3  
Vss  
0
-
V
Vcc+0.22)  
0.6  
Input high voltage  
Input low voltage  
Note:  
VIH  
2.2  
V
-0.23)  
VIL  
-
V
1. Industrial Product: TA=-40 to 85°C, Otherwise specified  
Automotive Product: TA=-40 to 125°C, Otherwise specified  
2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.  
3. Undershoot: -3.0V in case of pulse width≤30ns.  
4. Overshoot and undershoot are sampled, not 100% tested.  
CAPACITANCE1) (f=1MHz, TA=25°C)  
Item  
Input capacitance  
Symbol  
CIN  
Test Condition  
VIN=0V  
Min  
Max  
8
Unit  
pF  
-
-
Input/Output capacitance  
CIO  
VIO=0V  
10  
pF  
1. Capacitance is sampled, not 100% tested  
DC AND OPERATING CHARACTERISTICS  
Item  
Symbol  
ILI  
Test Conditions  
Min Typ Max Unit  
Input leakage current  
VIN=Vss to Vcc  
-1  
-1  
-
-
-
-
1
1
2
µA  
µA  
Output leakage current  
Operating power supply current  
ILO  
CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc  
IIO=0mA, CS=VIL, VIN=VIH or VIL, Read  
ICC  
mA  
Cycle time=1µs, 100% duty, IIO=0mA, CS≤0.2V,  
VIN≤0.2VIN≥Vcc -0.2V  
ICC1  
ICC2  
-
-
-
-
3
mA  
Average operating current  
Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL  
20 mA  
Output low voltage  
Output high voltage  
Standby Current(TTL)  
VOL  
VOH  
ISB  
IOL=2.1mA  
-
-
-
-
-
-
0.4  
-
V
V
IOH=-1.0mA  
2.4  
CS=VIH, Other inputs=VIH or VIL  
-
-
-
0.3 mA  
µA  
K6X0808T1D-F  
K6X0808T1D-Q  
6
Standby Current(CMOS)  
ISB1  
CS≥Vcc-0.2V, Other inputs=0~Vcc  
25 µA  
4
Revision 2.0  
March 2005  
K6X0808T1D Family  
CMOS SRAM  
AC OPERATING CONDITIONS  
TEST CONDITIONS( Test Load and Input/Output Reference)  
Input pulse level: 0.4 to 2.2V  
Input rising and falling time: 5ns  
1)  
CL  
Input and output reference voltage:1.5V  
Output load(see right): CL=100pF+1TTL  
CL=30pF+1TTL  
1. Including scope and jig capacitance  
AC CHARACTERISTICS (VCC=2.7~3.6V, Industrial product:TA=-40 to 85°C, Automotive product:TA=-40 to 125°C )  
Speed Bins  
Parameter List  
Symbol  
Units  
70ns  
85ns  
Min  
70  
-
Max  
Min  
85  
-
Max  
Read Cycle Time  
tRC  
tAA  
-
70  
70  
35  
-
-
85  
85  
40  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
-
-
Output Enable to Valid Output  
Chip Select to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Write Cycle Time  
-
-
Read  
tLZ  
10  
5
10  
5
tOLZ  
tHZ  
-
-
0
25  
25  
-
0
25  
25  
-
tOHZ  
tOH  
tWC  
tCW  
tAS  
0
0
10  
70  
60  
0
15  
85  
70  
0
-
-
Chip Select to End of Write  
Address Set-up Time  
-
-
-
-
Address Valid to End of Write  
Write Pulse Width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
60  
50  
0
-
70  
60  
0
-
-
-
Write  
Write Recovery Time  
-
-
Write to Output High-Z  
0
25  
-
0
30  
-
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Output Low-Z  
25  
0
35  
0
-
-
tOW  
5
-
5
-
DATA RETENTION CHARACTERISTICS  
Item  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
V
Vcc for data retention  
VDR  
2.0  
-
-
3.6  
6
CS1≥Vcc-0.2V  
K6X0808T1D-F  
K6X0808T1D-Q  
µA  
µA  
Data retention current  
IDR  
-
Vcc=3.0V, CS1≥Vcc-0.2V  
25  
-
Data retention set-up time  
Recovery time  
tSDR  
tRDR  
0
5
-
-
See data retention waveform  
ms  
-
5
Revision 2.0  
March 2005  
K6X0808T1D Family  
CMOS SRAM  
TIMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)  
tRC  
Address  
tAA  
tOH  
Data Valid  
Data Out  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tOH  
tAA  
tCO  
CS  
tHZ  
tOE  
OE  
tOHZ  
tOLZ  
tLZ  
High-Z  
Data out  
Data Valid  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
6
Revision 2.0  
March 2005  
K6X0808T1D Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
Address  
tCW(2)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tAS(3)  
tDW  
tDH  
Data Valid  
Data in  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)  
tWC  
Address  
tCW(2)  
tAS(3)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tDW  
tDH  
Data in  
Data Valid  
High-Z  
Data out  
High-Z  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE  
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write  
to the end of write.  
2. tCW is measured from the CS going low to the end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.  
DATA RETENTION WAVE FORM  
CS controlled  
Data Retention Mode  
tSDR  
tRDR  
VCC  
3.0V/2.7V  
2.2V  
VDR  
CS≥VCC - 0.2V  
CS  
GND  
7
Revision 2.0  
March 2005  
K6X0808T1D Family  
CMOS SRAM  
PACKAGE DIMENSIONS  
Units: millimeter(inch)  
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)  
0~8°  
#28  
#15  
8.38±0.20  
0.330±0.008  
11.81±0.30  
0.465±0.012  
#1  
#14  
1.02±0.20  
0.040±0.008  
+0.10  
-0.05  
+0.004  
-0.002  
0.15  
2.59±0.20  
0.102±0.008  
18.69  
0.736  
0.006  
MAX  
3.00  
0.118  
MAX  
18.29±0.20  
0.720±0.008  
0.10 MAX  
0.004 MAX  
0.89  
0.035  
1.27  
0.050  
0.41±0.10  
0.016±0.004  
(
)
0.05  
0.002  
MIN  
8
Revision 2.0  
March 2005  
K6X0808T1D Family  
CMOS SRAM  
PACKAGE DIMENSIONS  
Units: millimeter(inch)  
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)  
13.40±0.20  
0.528±0.008  
+0.10  
0.20  
-0.05  
+0.004  
0.008  
-0.002  
#1  
#28  
0.425  
0.017  
(
)
0.55  
0.0217  
#14  
#15  
0.25  
0.010  
11.80±0.10  
0.465±0.004  
+0.10  
-0.05  
TYP  
0.15  
0.006+0.004  
-0.002  
1.00±0.10  
0.039±0.004  
0.05  
0.002  
MIN  
0~8°  
1.20  
MAX  
0.047  
0.50  
0.020  
0.45 ~0.75  
0.018 ~0.030  
(
)
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)  
13.40±0.20  
0.528±0.008  
+0.10  
-0.05  
0.20  
0.008+0.004  
-0.002  
#14  
#15  
0.425  
0.017  
(
)
0.55  
0.0217  
#1  
#28  
1.00±0.10  
0.05  
0.002  
MIN  
0.25  
0.010  
11.80±0.10  
0.465±0.004  
0.039±0.004  
+0.10  
-0.05  
TYP  
0.15  
0.006+0.004  
1.20  
MAX  
0.047  
-0.002  
0~8°  
0.50  
0.020  
0.45 ~0.75  
0.018 ~0.030  
(
)
9
Revision 2.0  
March 2005  

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