K6X1008C2D-TF700 [SAMSUNG]
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32;型号: | K6X1008C2D-TF700 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32 静态存储器 光电二极管 内存集成电路 |
文件: | 总10页 (文件大小:122K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K6X1008C2D Family
CMOS SRAM
Document Title
128Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
Initial draft
July 15, 2002
Preliminary
0.1
Revised
December 4, 2002
Preliminary
- Deleted 32-TSOP1-0820R Package Type.
- Added Commercial product.
0.2
0.3
1.0
Revised
May 13, 2003
Preliminary
Preliminary
Final
- Added Lead Free 32-SOP-525 Product
Revised
June 21, 2003
- Added Lead Free 32-TSOP1-0820F Product
Finalized
September 16, 2003
- Changed ICC from 10mA to 5mA
- Changed ICC2 from 35mA to 25mA
- Changed ISB from 3mA to 0.4mA
- Changed IDR(industrial) from 15µA to 10µA
- Changed IDR(Automotive) from 25µA to 20µA
2.0
3.0
Revised
July 15, 2004
Final
Final
- Changed ISB1 of Automotive product from 25µA to 30µA
- Deleted 55ns Automotive product
Revised
March 27, 2005
- Changed ISB1 of Automotive product from 30µA to 50µA
- Changed IDR of Automotive product from 20µA to 25µA
- Added Lead Free Products
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.0
March 2005
K6X1008C2D Family
CMOS SRAM
128Kx8 bit Low Power full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 128K x 8
The K6X1008C2D families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
verious operating temperature ranges and have various pack-
age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 32-DIP-600, 32-SOP-525,
32-SOP-525, 32-TSOP1-0820F
PRODUCT FAMILY
Power Dissipation
PKG Type
Operating
Temperature
Product Family
Vcc Range
Speed
Standby
Operating
(ICC2, Max)
(ISB1, Max)
K6X1008C2D-B
K6X1008C2D-F
K6X1008C2D-Q
Commercial(0~70°C)
Industrial(-40~85°C)
Automotive(-40~125°C)
10µA
15µA
50µA
32-DIP-600, 32-SOP-525,
32-SOP-525
551)/70ns
70ns
4.5~5.5V
25mA
32-TSOP1-0820F
32-SOP-525, 32-TSOP1-0820F
1. The parameters are tested with 50pF test load
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
VCC
A15
CS2
WE
A13
A8
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
4
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
Row
addresses
Row
select
5
Memory array
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
6
32-SOP
32-DIP
A9
A5
7
A11
OE
32-TSOP
Type1-Forward
A4
8
9
A3
9
10
11
12
13
14
15
16
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A2
10
11
12
13
14
15
16
A1
A6
A5
A4
A1
A2
A3
A0
I/O1
I/O8
Data
cont
I/O Circuit
I/O1
I/O2
I/O3
VSS
Column select
Data
cont
Column Addresses
Name
Function
CS1, CS2
OE
Chip Select Input
Output Enable Input
Write Enable Input
Data Inputs/Outputs
Address Inputs
Power
CS1
Control
logic
CS2
WE
WE
OE
I/O1~I/O8
A0~A16
Vcc
Vss
Ground
NC
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 3.0
March 2005
K6X1008C2D Family
CMOS SRAM
PRODUCT LIST
Commercial Products(0~70°C)
Industrial Products(-40~85°C)
Automotive Products(-40~125°C)
Part Name
Function
Part Name
Function
Part Name
Function
K6X1008C2D-DB55
K6X1008C2D-DB70
K6X1008C2D-GB55
K6X1008C2D-GB70
32-DIP, 55ns, LL
32-DIP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 55ns, LL, LF
32-SOP, 70ns, LL, LF
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
32-TSOP-F, 55ns, LL, LF
32-TSOP-F, 70ns, LL, LF
K6X1008C2D-DF55
K6X1008C2D-DF70
K6X1008C2D-GF55
K6X1008C2D-GF70
32-DIP, 55ns, LL
32-DIP, 70ns, LL
K6X1008C2D-GQ70
32-SOP, 70ns, L
1)
K6X1008C2D-BQ70
K6X1008C2D-TQ70
K6X1008C2D-PQ70
32-SOP, 70ns, L, LF
32-TSOP-F, 70ns, L
32-TSOP-F, 70ns, L, LF
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
1)
1)
1)
K6X1008C2D-BB55
K6X1008C2D-BB70
K6X1008C2D-TB55
K6X1008C2D-TB70
K6X1008C2D-PB55
K6X1008C2D-PB70
K6X1008C2D-BF55
K6X1008C2D-BF70
K6X1008C2D-TF55
K6X1008C2D-TF70
K6X1008C2D-PF55
K6X1008C2D-PF70
1)
1)
1)
1)
1)
1)
1. Lead Free Product
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Deselected
Deselected
Output Disabled
Read
Power
Standby
Standby
Active
X1)
L
X1)
X1)
H
High-Z
High-Z
High-Z
Dout
X1)
L
X1)
H
X1)
H
H
H
H
L
L
L
H
L
Active
X1)
Din
Write
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-0.5 to VCC+0.5V(Max. 7.0V)
-
-0.3 to 7.0
1.0
V
-
PD
W
-
Storage temperature
TSTG
-65 to 150
0 to 70
°C
°C
°C
°C
-
K6X1008C2D-B
K6X1008C2D-F
K6X1008C2D-Q
Operating Temperature
TA
-40 to 85
-40 to 125
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 3.0
March 2005
K6X1008C2D Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
4.5
0
Typ
Max
5.5
0
Unit
V
Supply voltage
Ground
5.0
Vss
0
-
V
Vcc+0.52)
0.8
Input high voltage
Input low voltage
Note:
VIH
2.2
V
-0.53)
VIL
-
V
1. Commercial Product: TA=0 to 70°C, Otherwise specified
Industrial Product: TA=-40 to 85°C, Otherwise specified
Automotive Product: TA=-40 to 125°C, Otherwise specified
2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.
3. Undershoot: -3.0V in case of pulse width≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
-
1
1
5
µA
µA
Output leakage current
Operating power supply current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read
ICC
mA
Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V, CS2≥Vcc-0.2V,
VIN≤0.2V or VIN≥VCC-0.2V
ICC1
ICC2
-
-
-
-
7
mA
Average operating current
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH,
VIN=VIH or VIL
25 mA
Output low voltage
Output high voltage
Standby Current(TTL)
VOL
VOH
ISB
IOL=2.1mA
-
-
-
-
-
-
-
0.4
-
V
V
IOH=-1.0mA
2.4
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
-
-
-
-
0.4 mA
10 µA
15 µA
50 µA
K6X1008C2D-B
CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or
CS2≤0.2V, Other inputs=0~Vcc
Standby Current(CMOS)
ISB1
K6X1008C2D-F
K6X1008C2D-Q
4
Revision 3.0
March 2005
K6X1008C2D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
1)
CL
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS
(VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40~125°C)
Speed Bins
55ns1)
Max
Parameter List
Symbol
Units
70ns
Min
55
-
Min
70
-
Max
Read Cycle Time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
-
-
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
-
-
Read
tLZ
10
5
10
5
tOLZ
tHZ
-
-
0
20
20
-
0
25
25
-
tOHZ
tOH
tWC
tCW
tAS
0
0
10
55
45
0
10
70
60
0
-
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
-
60
50
0
-
-
-
Write
Write Recovery Time
-
-
Write to Output High-Z
0
20
-
0
25
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
20
0
25
0
-
-
tOW
5
-
5
-
1. The parameter is tested with 50pF test load. Commercial & Industrial Products only.
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
V
CS1≥Vcc-0.2V1)
Vcc for data retention
VDR
2.0
-
-
-
-
-
-
-
5.5
10
10
25
-
K6X1008C2D-B
K6X1008C2D-F
K6X1008C2D-Q
µA
µA
µA
Vcc=3.0V, CS1≥Vcc-0.2V1)
Data retention current
IDR
-
-
Data retention set-up time
Recovery time
tSDR
tRDR
0
5
See data retention waveform
ms
-
1. CS1≥Vcc-0.2V, CS2≥VCC-0.2V, or CS2≤0.2V
5
Revision 3.0
March 2005
K6X1008C2D Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 3.0
March 2005
K6X1008C2D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
CS1
tCW(2)
tAS(3)
tWR(4)
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
7
Revision 3.0
March 2005
K6X1008C2D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data Valid
Data in
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
2.2V
VDR
CS≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
4.5V
CS2
tSDR
tRDR
VDR
CS2≤0.2V
0.4V
GND
8
Revision 3.0
March 2005
K6X1008C2D Family
CMOS SRAM
PACKAGE DIMENSIONS
32 DUAL INLINE PACKAGE (600mil)
Units: millimeters(inches)
+0.10
0.25
-0.05
0.010+0.004
-0.002
#32
#17
13.60±0.20
0.535±0.008
#1
#16
0~15°
3.81±0.20
42.31
1.666
MAX
0.150±0.008
5.08
0.200
MAX
41.91±0.20
1.650±0.008
3.30±0.30
0.130±0.012
0.46±0.10
0.018±0.004
0.38
0.015
1.91
0.075
1.52±0.10
2.54
0.100
MIN
(
)
0.060±0.004
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
#17
14.12±0.30
0.556±0.012
11.43±0.20
0.450±0.008
#1
#16
0.80±0.20
+0.10
-0.05
0.20
2.74±0.20
0.031±0.008
20.87
MAX
0.108±0.008
+0.004
0.822
0.008
-0.002
3.00
0.118
MAX
20.47±0.20
0.806±0.008
0.10 MAX
0.004 MAX
+0.100
-0.050
0.41
0.71
0.028
1.27
0.050
+0.004
-0.002
(
)
0.05
0.002
0.016
MIN
9
Revision 3.0
March 2005
K6X1008C2D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
0.008+0.004
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#16
#17
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
18.40±0.10
0.724±0.004
TYP
+0.10
0.15
-0.05
0.006+0.004
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
10
Revision 3.0
March 2005
相关型号:
K6X1008T2D-BB700
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.525 INCH, LEAD FREE, PLASTIC, SOP-32
SAMSUNG
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