K6X1008T2D-GB55 [SAMSUNG]

128Kx8 bit Low Power CMOS Static RAM; 128Kx8位低功耗CMOS静态RAM


型号：	K6X1008T2D-GB55
厂家：	SAMSUNG
描述：	128Kx8 bit Low Power CMOS Static RAM 128Kx8位低功耗CMOS静态RAM 存储内存集成电路静态存储器光电二极管
文件：	总9页 (文件大小：155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K6X1008T2D Family

CMOS SRAM

Document Title

128Kx8 bit Low Power CMOS Static RAM

Revision History

Revision No. History

Draft Data

Remark

0.0

0.1

Initial draft

July 15, 2002

Preliminary

Revised

December 4, 2002

Preliminary

- Deleted 32-TSOP1-0820R, 32-TSOP1-0813.4F/R Package Type.

- Added Commercial product.

- Added 55ns product( Vcc = 3.0V~3.6V)

0.2

1.0

Revised

June 23, 2003

Preliminary

Final

- Added Lead Free 32-SOP-525 Product

- Added Lead Free 32-TSOP1-0820F Product

Finalized

September 16, 2003

- Changed ICC from 3mA to 2mA

- Changed ICC2 from 25mA to 20mA

- Changed ISB1(Commercial) from 10mA to 6mA

- Changed ISB1(industrial) from 10mA to 6mA

- Changed ISB1(Automotive) from 20mA to 10mA

- Changed IDR(Commercial) from 10mA to 6mA

- Changed IDR(industrial) from 10mA to 6mA

- Changed IDR(Automotive) from 20mA to 10mA

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

September 2003

K6X1008T2D Family

CMOS SRAM

128Kx8 bit Super Low Power and Low Voltage full CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Full CMOS

· Organization: 128K x 8

The K6X1008T2D families are fabricated by SAMSUNG¢s

advanced CMOS process technology. The families support

verious operating temperature ranges and have various pack-

age types for user flexibility of system design. The families

also support low data retention voltage for battery back-up

operation with low data retention current.

· Power Supply Voltage: 2.7~3.6V

· Low Data Retention Voltage: 1.5V(Min)

· Three state outputs

· Package Type: 32-SOP-525, 32-TSOP1-0820F

32-SOP-525, 32-TSOP1-0820F

PRODUCT FAMILY

Power Dissipation

Product Family Operating Temperature Vcc Range

Speed

PKG Type

Standby Operating

(ISB1, Max) (ICC2, Max)

K6X1008T2D-B

K6X1008T2D-F

Commercial(0~70°C)

Industrial(-40~85°C)

32-SOP-525

32-TSOP1-0820F

32-SOP-525

55¹⁾/70²⁾/85ns

70²⁾/85ns

6mA

2.7~3.6V

20mA

32-TSOP1-0820F

K6X1008T2D-Q Automotive(-40~125°C)

10mA

1. This parameter is measured in the voltage range of 3.0V~3.6V with 30pF test load.

2. This parameter is measured with 30pF test load.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Precharge circuit.

VCC

A15

CS2

A13

A16

A14

A12

A11

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

Row

select

Row

Addresses

Memory array

A13

CS2

A15

VCC

A16

A14

A12

32-SOP ²⁵

A11

32-TSOP

Type1-Forward

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

I/O1

I/O2

I/O3

VSS

I/O1

I/O8

Data

cont

I/O Circuit

Column select

Data

cont

Column Addresses

Name

A0~A16

Function

Address Inputs

CS1

Control

logic

CS2

Write Enable Input

Chip Select Input

Output Enable Input

Data Inputs/Outputs

Power

CS1,CS2

I/O1~I/O8

Vcc

Vss

Ground

No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

September 2003

K6X1008T2D Family

CMOS SRAM

PRODUCT LIST

Commercial Products(0~70°C)

Industrial Products(-40~85°C)

Atomotive Products(-40~125°C)

Part Name

Function

Part Name

Function

Part Name

Function

K6X1008T2D-GB55¹⁾

K6X1008T2D-GB70

K6X1008T2D-GB85

K6X1008T2D-TB55¹⁾

K6X1008T2D-TB70

K6X1008T2D-TB85

32-SOP, 55ns, LL

32-SOP, 70ns, LL

32-SOP, 85ns, LL

32-TSOP-F, 55ns, LL

32-TSOP-F, 70ns, LL

32-TSOP-F, 85ns, LL

K6X1008T2D-GF55¹⁾

K6X1008T2D-GF70

K6X1008T2D-GF85

K6X1008T2D-TF55¹⁾

K6X1008T2D-TF70

K6X1008T2D-TF85

32-SOP, 55ns, LL

32-SOP, 70ns, LL

32-SOP, 85ns, LL

32-TSOP-F, 55ns, LL

32-TSOP-F, 70ns, LL

32-TSOP-F, 85ns, LL

K6X1008T2D-GQ70 32-SOP, 70ns, L

K6X1008T2D-GQ85 32-SOP, 85ns, L

K6X1008T2D-TQ70 32-TSOP-F, 70ns, L

K6X1008T2D-TQ85 32-TSOP-F, 85ns, L

K6X1008T2D-BB55^1,2)32-SOP, 55ns, LL

K6X1008T2D-BF55^1,2)32-SOP, 55ns, LL

K6X1008T2D-BB70²⁾

K6X1008T2D-BB85²⁾

32-SOP, 70ns, LL

K6X1008T2D-BF70²⁾

K6X1008T2D-BF85²⁾

32-SOP, 70ns, LL

32-SOP, 85ns, LL

K6X1008T2D-PB55^1,2)32-TSOP-F, 55ns, LL

32-SOP, 85ns, LL

K6X1008T2D-PF55^1,2)32-TSOP-F, 55ns, LL

K6X1008T2D-PB70²⁾

K6X1008T2D-PB85²⁾

32-TSOP-F, 70ns, LL

32-TSOP-F, 85ns, LL

K6X1008T2D-PF70²⁾

K6X1008T2D-PF85²⁾

32-TSOP-F, 70ns, LL

32-TSOP-F, 85ns, LL

1. Operating voltage range is 3.0V~3.6V

2. Lead Free Product

FUNCTIONAL DESCRIPTION

CS1

CS2

I/O

Mode

Deselected

Output Disabled

Read

Power

Standby

Active

X¹⁾

High-Z

Dout

X¹⁾

Active

X¹⁾

Din

Write

Active

1. X means don¢t care (Must be in high or low states)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

VIN,VOUT

VCC

-0.2 to VCC+0.3V(Max. 3.9V)

-0.2 to 3.9

1.0

Storage temperature

TSTG

-65 to 150

0 to 70

°C

K6X1008T2D-B

K6X1008T2D-F

K6X1008T2D-Q

Operating Temperature

-40 to 85

-40 to 125

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 1.0

September 2003

K6X1008T2D Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Vcc

Min

2.7

Typ

Max

3.6

Unit

Supply voltage

Ground

3.0/3.3

Vss

Vcc+0.2²⁾

0.6

Input high voltage

Input low voltage

Note:

VIH

2.2

-0.2³⁾

VIL

1. Commercial Product: TA=0 to 70°C, Otherwise specified

. Industrial Product: TA=-40 to 85°C, Otherwise specified

Automotive Product: TA=-40 to 125°C, Otherwise specified

2. Overshoot: Vcc+3.0V in case of pulse width£30ns.

3. Undershoot: -3.0V in case of pulse width£30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read

ICC

Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V, CS2³ Vcc-0.2V,

VIN£0.2V or VIN³ VCC-0.2V

ICC1

ICC2

Average operating current

Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH,

VIN=VIH or VIL

20 mA

Output low voltage

Output high voltage

Standby Current(TTL)

VOL

VOH

ISB

IOL=2.1mA

0.4

IOH=-1.0mA

2.4

CS1=VIH, CS2=VIL, Other inputs=VIH or VIL

0.3 mA

K6X1008T2D-B

CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V,

Other inputs=0~Vcc

Standby Current(CMOS)

ISB1

K6X1008T2D-F

K6X1008T2D-Q

10 mA

Revision 1.0

September 2003

K6X1008T2D Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS( Test Load and Input/Output Reference)

Input pulse level: 0.4 to 2.2V

Input rising and falling time: 5ns

Input and output reference voltage:1.5V

Output load(see right): CL=100pF+1TTL

CL=30pF+1TTL

1. Including scope and jig capacitance

AC CHARACTERISTICS

(VCC=2.7~3.6V, Commercial product:TA=0 to 70°C, Industrial product:TA=-40 to 85°C, Automotive product:TA=-40 to 125°C )

Speed Bins

)

Parameter List

Symbol

Units

70ns

Max

85ns

Max

55ns

Min

Max

Min

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

tLZ

Output Enable to Valid Output

Chip Select to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Write Cycle Time

Read

tOLZ

tHZ

tOHZ

tOH

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width

tAW

tWP

tWR

tWHZ

tDW

tDH

tOW

Write

Write Recovery Time

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

1. Voltage range is 3.0V~3.6V for commercial and industrial product.

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

Min

Typ

Max

Unit

CS1³ Vcc-0.2V¹⁾

Vcc for data retention

VDR

2.0

3.6

K6X1008T2D-B

K6X1008T2D-F

K6X1008T2D-Q

Vcc=3.0V, CS1³ Vcc-0.2V¹⁾

Data retention current

IDR

Data retention set-up time

Recovery time

tSDR

tRDR

See data retention waveform

1. CS¹³ Vcc-0.2V, CS2³ VCC-0.2V, or CS2£0.2V

Revision 1.0

September 2003

K6X1008T2D Family

CMOS SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)

tRC

Address

tAA

tOH

Data Out

Data Valid

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

CS1

tHZ(1,2)

CS2

tCO2

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 1.0

September 2003

K6X1008T2D Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tWR(4)

tCW(2)

CS1

tAW

CS2

tCW(2)

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS¹Controlled)

tWC

Address

CS1

tCW(2)

tAS(3)

tWR(4)

tAW

CS2

tWP(1)

tDW

tDH

Data in

Data out

Data Valid

High-Z

Revision 1.0

September 2003

K6X1008T2D Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC

Address

CS1

tAS(3)

tCW(2)

tWR(4)

tAW

CS2

tCW(2)

tWP(1)

tDH

tDW

Data Valid

Data in

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS¹going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS¹or WE going high tWR2 applied

in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

2.7V

2.2V

VDR

CS³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

2.7V

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

Revision 1.0

September 2003

K6X1008T2D Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeters(inches)

32 PLASTIC SMALL OUTLINE PACKAGE (525mil)

0~8°

#32

#17

14.12±0.30

0.556±0.012

11.43±0.20

0.450±0.008

#16

0.80±0.20

+0.10

0.20

2.74±0.20

0.031±0.008

-0.05

20.87

MAX

0.108±0.008

+0.004

0.822

0.008

-0.002

3.00

0.118

MAX

20.47±0.20

0.806±0.008

0.10 MAX

0.004 MAX

+0.100

-0.050

0.41

0.71

0.028

1.27

0.050

+0.004

-0.002

(

)

0.05

0.002

0.016

MIN

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

+0.10

-0.05

20.00±0.20

0.787±0.008

0.20

0.008^+0.004

-0.002

#32

0.25

0.010

(

)

8.40

0.331

MAX

0.50

0.0197

#16

#17

1.00±0.10

0.039±0.004

0.05

0.002

MIN

1.20

MAX

0.047

0.25

0.010

18.40±0.10

0.724±0.004

TYP

+0.10

0.15

-0.05

0.006^+0.004

-0.002

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

Revision 1.0

September 2003

K6X1008T2D-GB55 [SAMSUNG]

相关型号：

K6X1008T2D-GB550

K6X1008T2D-GB55T

K6X1008T2D-GB70

K6X1008T2D-GB700

K6X1008T2D-GB85

K6X1008T2D-GB850

K6X1008T2D-GB85T

K6X1008T2D-GF55

K6X1008T2D-GF550

K6X1008T2D-GF70

K6X1008T2D-GF700

K6X1008T2D-GF85