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K6X8008C2B-TB550 [SAMSUNG]

Standard SRAM, 1MX8, 55ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;
K6X8008C2B-TB550
型号： K6X8008C2B-TB550
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 1MX8, 55ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

静态存储器 光电二极管 内存集成电路
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K6X8008C2B Family  
CMOS SRAM  
Document Title  
1Mx8 bit Low Power and Low Voltage CMOS Static RAM  
Revision History  
Revision No. History  
Draft Date  
Remark  
0.0  
Initial draft  
October 31, 2002  
Preliminary  
0.1  
Revised  
December 11, 2002 Preliminary  
September 16, 2003 Final  
- Deleted 44-TSOP2-400R package type.  
- Added Commercial product.  
1.0  
Finalized  
- Changed ICC from 10mA to 6mA  
- Changed ICC1 from 10mA to 7mA  
- Changed ICC2 from 50mA to 35mA  
- Changed ISB from 3mA to 0.4mA  
- Changed ISB1(Commercial) from 40µA to 25µA  
- Changed ISB1(industrial) from 40µA to 25µA  
- Changed ISB1(Automotive) from 50µA to 40µA  
- Changed IDR(Commercial) from 30µA to 15µA  
- Changed IDR(industrial) from 30µA to 15µA  
- Changed IDR(Automotive) from 40µA to 30µA  
2.0  
Revised  
March 27. 2005  
Final  
- Changed ISB1 of Automotive product from 40µA to 100µA  
- Changed IDR of Automotive product from 30µA to 80µA  
- Added Lead Free Products  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.  
Revision 2.0  
March 2005  
1
K6X8008C2B Family  
CMOS SRAM  
1Mx8 bit Low Power full CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
• Process Technology: Full CMOS  
• Organization: 1M x8  
The K6X8008C2B families are fabricated by SAMSUNG′s  
advanced full CMOS process technology. The families sup-  
port various operating temperature range for user flexibility of  
system design. The families also support low data retention  
voltage for battery back-up operation with low data retention  
current.  
• Power Supply Voltage: 4.5~5.5V  
• Low Data Retention Voltage: 2.0V(Min)  
• Three state output and TTL Compatible  
• Package Type: 44-TSOP2-400F  
PRODUCT FAMILY  
Power Dissipation  
Product Family  
Operating Temperature  
Vcc Range  
Speed  
PKG Type  
Standby  
(ISB1, Max)  
Operating  
(ICC2, Max)  
K6X8008C2B-B  
K6X8008C2B-F  
K6X8008C2B-Q  
Commercial(0~70°C)  
Industrial(-40~85°C)  
Automotive(-40~125°C)  
25µA  
25µA  
4.5~5.5V  
551)/70ns  
35mA  
44-TSOP2-400F  
100µA  
1. The parameter is measured with 50pF test load.  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
Clk gen.  
Precharge circuit.  
A4  
A3  
A2  
A1  
A0  
CS1  
NC  
NC  
I/O1  
I/O2  
Vcc  
Vss  
I/O3  
I/O4  
NC  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
1
2
3
4
5
6
7
8
A5  
A6  
A7  
OE  
CS2  
A8  
Vcc  
Vss  
Row  
Addresses  
NC  
NC  
I/O8  
I/O7  
Vss  
Vcc  
I/O6  
I/O5  
NC  
NC  
A9  
A10  
A11  
A12  
A13  
A14  
Memory array  
Row  
select  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
44-TSOP2  
Forward  
NC  
I/O Circuit  
Column select  
Data  
cont  
WE  
A19  
A18  
A17  
A16  
A15  
I/O1~I/O8  
Data  
cont  
Column Addresses  
Name  
Function  
Name  
Vcc  
Function  
CS1, CS2 Chip Select Inputs  
Power  
Ground  
CS1  
CS2  
OE  
OE  
Output Enable Input  
Write Enable Input  
Vss  
WE  
A0~A19 Address Inputs  
NC No Connect  
Control Logic  
I/O1~I/O8 Data Inputs/Outputs  
WE  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
Revision 2.0  
March 2005  
2
K6X8008C2B Family  
CMOS SRAM  
PRODUCT LIST  
Commercial Products(0~70°C)  
Industrial Products(-40~85°C)  
Part Name Function  
Automotive Products(-40~125°C)  
Part Name  
Function  
Part Name  
Function  
K6X8008C2B-TB55 44-TSOP2-F, 55ns, LL  
K6X8008C2B-TB70 44-TSOP2-F, 70ns, LL  
K6X8008C2B-TF55 44-TSOP2-F, 55ns, LL  
K6X8008C2B-TF70 44-TSOP2-F, 70ns, LL  
K6X8008C2B-TQ55 44-TSOP2-F, 55ns, L  
K6X8008C2B-TQ70 44-TSOP2-F, 70ns, L  
K6X8008C2B-UB55 44-TSOP2-F, 55ns, LL, LF K6X8008C2B-UF55 44-TSOP2-F, 55ns, LL, LF K6X8008C2B-UQ55 44-TSOP2-F, 55ns, L, LF  
K6X8008C2B-UB70 44-TSOP2-F, 70ns, LL, LF K6X8008C2B-UF70 44-TSOP2-F, 70ns, LL, LF K6X8008C2B-UQ70 44-TSOP2-F, 70ns, L, LF  
1. LF : Lead Free Product  
FUNCTIONAL DESCRIPTION  
CS1  
H
CS2  
X
OE  
X
WE  
X
I/O1~8  
High-Z  
High-Z  
High-Z  
Dout  
Mode  
Deselected  
Deselected  
Output Disabled  
Read  
Power  
Standby  
Standby  
Active  
L
X
X
X
L
H
H
L
H
L
H
H
Active  
L
H
L
Din  
Write  
Active  
X
Note: X means don′t care. (Must be low or high state)  
ABSOLUTE MAXIMUM RATINGS1)  
Item  
Symbol  
Ratings  
Unit  
Remark  
Voltage on any pin relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
VIN, VOUT  
VCC  
-0.5 to VCC+0.5V(max.7.0V)  
V
-
-0.3 to 7.0  
1.0  
V
-
PD  
W
°C  
°C  
°C  
°C  
-
Storage temperature  
TSTG  
-65 to 150  
0 to 70  
-
K6X8008C2B-B  
K6X8008C2B-F  
K6X8008C2B-Q  
Operating Temperature  
TA  
-40 to 85  
-40 to 125  
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be  
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
Revision 2.0  
March 2005  
3
K6X8008C2B Family  
CMOS SRAM  
RECOMMENDED DC OPERATING CONDITIONS1)  
Item  
Supply voltage  
Ground  
Symbol  
Vcc  
Product  
Min  
4.5  
0
Typ  
Max  
5.5  
0
Unit  
V
K6X8008C2B Family  
All Family  
5.0  
Vss  
0
-
V
Vcc+0.52)  
0.8  
Input high voltage  
Input low voltage  
Note:  
VIH  
K6X8008C2B Family  
K6X8008C2B Family  
2.2  
V
-0.53)  
VIL  
-
V
1. Commercial Product: TA=0 to 70°C, otherwise specified.  
Industrial Product: TA=-40 to 85°C, otherwise specified.  
Automotive Product: TA=-40 to 125°C, otherwise specified.  
2. Overshoot: VCC+3.0V in case of pulse width ≤30ns.  
3. Undershoot: -3.0V in case of pulse width ≤30ns.  
4. Overshoot and undershoot are sampled, not 100% tested.  
CAPACITANCE1) (f=1MHz, TA=25°C)  
Item  
Input capacitance  
Symbol  
CIN  
Test Condition  
VIN=0V  
Min  
Max  
Unit  
-
-
8
pF  
pF  
Input/Output capacitance  
CIO  
VIO=0V  
10  
1. Capacitance is sampled, not 100% tested.  
DC AND OPERATING CHARACTERISTICS  
Item  
Symbol  
ILI  
Test Conditions  
Min Typ Max Unit  
Input leakage current  
VIN=Vss to Vcc  
-1  
-1  
-
-
-
-
1
1
6
µA  
µA  
Output leakage current  
Operating power supply current  
ILO  
CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc  
IIO=0mA, CS1=VIL, CS2=VIH, WE=VIH, VIN=VIH or VIL  
ICC  
mA  
Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V,  
CS2≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V  
ICC1  
ICC2  
-
-
-
-
7
mA  
Average operating current  
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH,  
VIN=VIL or VIH  
35 mA  
Output low voltage  
Output high voltage  
Standby Current(TTL)  
VOL  
VOH  
ISB  
IOL = 2.1mA  
-
2.4  
-
-
-
-
-
0.4  
-
V
V
IOH = -1.0mA  
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL  
0.4 mA  
25  
K6X8008C2B-B  
-
Other input =0~Vcc,  
Standby Current(CMOS)  
ISB1  
1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V (CS1 con-  
trolled) or 2) 0V≤CS2≤0.2V(CS2 controlled)  
K6X8008C2B-F  
K6X8008C2B-Q  
-
-
-
-
25  
µA  
100  
Revision 2.0  
March 2005  
4
K6X8008C2B Family  
CMOS SRAM  
AC OPERATING CONDITIONS  
TEST CONDITIONS(Test Load and Input/Output Reference)  
Input pulse level: 0.8 to 2.4V  
Input rising and falling time: 5ns  
)
1
Input and output reference voltage: 1.5V  
Output load(see right): CL=100pF+1TTL  
CL=50pF+1TTL  
CL  
1.Including scope and jig capacitance  
AC CHARACTERISTICS  
(VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C)  
Speed Bins  
Parameter List  
Symbol  
Units  
55ns  
70ns  
Min  
55  
-
Max  
Min  
70  
-
Max  
Read Cycle Time  
tRC  
tAA  
-
55  
55  
25  
-
-
70  
70  
35  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
tLZ  
-
-
Output Enable to Valid Output  
Chip Select to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Write Cycle Time  
-
-
Read  
10  
5
10  
5
tOLZ  
tHZ  
-
-
0
20  
20  
-
0
25  
25  
-
tOHZ  
tOH  
tWC  
tCW  
tAS  
0
0
10  
55  
45  
0
10  
70  
60  
0
-
-
Chip Select to End of Write  
Address Set-up Time  
-
-
-
-
Address Valid to End of Write  
Write Pulse Width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
45  
40  
0
-
60  
50  
0
-
-
-
Write  
Write Recovery Time  
-
-
Write to Output High-Z  
0
20  
-
0
20  
-
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Output Low-Z  
25  
0
30  
0
-
-
tOW  
5
-
5
-
DATA RETENTION CHARACTERISTICS  
Item  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
CS1≥Vcc-0.2V1)  
Vcc for data retention  
VDR  
2.0  
-
5.5  
15  
15  
80  
-
V
K6X8008C2B-B  
K6X8008C2B-F  
K6X8008C2B-Q  
Vcc=3.0V, CS1≥Vcc-0.2V1)  
Data retention current  
IDR  
-
-
µA  
Data retention set-up time  
Recovery time  
tSDR  
tRDR  
0
5
-
-
See data retention waveform  
ms  
-
1. CS1≥Vcc-0.2V,CS2≥Vcc-0.2V(CS1 controlled) or CS2≥Vcc-0.2V(CS2 controlled).  
Revision 2.0  
March 2005  
5
K6X8008C2B Family  
CMOS SRAM  
TIMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)  
tRC  
Address  
tAA  
tOH  
Data Valid  
Data Out  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tOH  
tAA  
tCO1  
CS1  
tHZ(1,2)  
CS2  
tCO2  
tOE  
OE  
tOHZ  
tOLZ  
tLZ  
High-Z  
Data out  
Data Valid  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
Revision 2.0  
March 2005  
6
K6X8008C2B Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
Address  
tWR(4)  
tCW(2)  
CS1  
tAW  
CS2  
tCW(2)  
tWP(1)  
WE  
tAS(3)  
tDW  
tDH  
Data Valid  
Data in  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)  
tWC  
Address  
CS1  
tCW(2)  
tAS(3)  
tWR(4)  
tAW  
CS2  
tWP(1)  
WE  
tDW  
tDH  
Data in  
Data out  
Data Valid  
High-Z  
High-Z  
Revision 2.0  
March 2005  
7
K6X8008C2B Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)  
tWC  
Address  
tAS(3)  
tCW(2)  
tWR(4)  
CS1  
tAW  
CS2  
tCW(2)  
tWP(1)  
WE  
tDH  
tDW  
Data Valid  
Data in  
High-Z  
High-Z  
Data out  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,  
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,  
tWP is measured from the begining of write to the end of write.  
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied  
in case a write ends as CS2 going to low.  
DATA RETENTION WAVE FORM  
CS1 controlled  
Data Retention Mode  
tSDR  
tRDR  
VCC  
4.5V  
2.2V  
VDR  
CS1≥VCC - 0.2V  
CS1  
GND  
CS2 controlled  
Data Retention Mode  
VCC  
4.5V  
CS2  
tSDR  
tRDR  
VDR  
CS2≤0.2V  
0.4V  
GND  
Revision 2.0  
March 2005  
8
K6X8008C2B Family  
CMOS SRAM  
PACKAGE DIMENSIONS  
Unit: millimeters(inches)  
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)  
0~8°  
0.25  
0.010  
(
)
#44  
#23  
0.45 ~0.75  
0.018 ~ 0.030  
11.76±0.20  
0.463±0.008  
0.50  
0.020  
(
)
#1  
#22  
1.00±0.10  
0.039±0.004  
18.81  
0.741  
1.20  
0.047  
MAX.  
MAX.  
18.41±0.10  
0.725±0.004  
0.10  
0.004  
MAX  
0.35± 0.10  
0.014±0.004  
0.80  
0.0315  
0.805  
0.032  
(
)
Revision 2.0  
March 2005  
9

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