K7A203200B-QC14 [SAMSUNG]
64Kx36 & 64Kx32-Bit Synchronous Pipelined Burst SRAM; 64Kx36和64Kx32位同步流水线突发SRAM
| 型号： | K7A203200B-QC14 |
| 厂家： | 
SAMSUNG |
| 描述： | 64Kx36 & 64Kx32-Bit Synchronous Pipelined Burst SRAM |
| 文件： | 总9页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6X8016C3B Family
CMOS SRAM
Document Title
512Kx16 bit Low Power Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial draft
October 31, 2002
Preliminary
0.1
Revised
December 11, 2002 Preliminary
- Deleted 44-TSOP2-400R package type.
- Added Commercial product.
0.11
1.0
Revised
March 26, 2003
Preliminary
- Errata correction : corrected commercial product family name from
K6X8016C3B-F to K6X8016C3B-B in PRODUCT FAMILY.
Finalized
September 16, 2003 Final
- Changed ICC from 12mA to 6mA
- Changed ICC1 from 12mA to 7mA
- Changed ICC2 from 60mA to 35mA
- Changed ISB from 3mA to 0.4mA
- Changed ISB1(Commercial) from 40mA to 25mA
- Changed ISB1(industrial) from 40mA to 25mA
- Changed ISB1(Automotive) from 50mA to 40mA
- Changed IDR(Commercial) from 30mA to 15mA
- Changed IDR(industrial) from 30mA to 15mA
- Changed IDR(Automotive) from 40mA to 30mA
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
1
September 2003
K6X8016C3B Family
CMOS SRAM
512Kx16 bit Low Power Full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: Full CMOS
· Organization: 512K x16
The K6X8016C3B families are fabricated by SAMSUNG¢s
advanced full CMOS process technology. The families support
various operating temperature range for user flexibility of sys-
tem design. The families also support low data retention voltage
for battery back-up operation with low data retention current.
· Power Supply Voltage: 4.5~5.5V
· Low Data Retention Voltage: 2.0V(Min)
· Three state output and TTL Compatible
· Package Type: 44-TSOP2-400F
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
K6X8016C3B-B
K6X8016C3B-F
K6X8016C3B-Q
Commercial(0~70°C)
Industrial(-40~85°C)
Automotive(-40~125°C)
25mA
25mA
40mA
4.5~5.5V
551)/70ns
35mA
44-TSOP2-400F
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A4
A3
A2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
A8
Clk gen.
Precharge circuit.
3
4
5
6
A1
A0
Vcc
Vss
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A18
A17
A16
A15
A14
7
8
9
Row
Addresses
Memory array
Row
select
10
11
12
13
14
15
16
17
18
19
20
21
22
44-TSOP2
Forward
I/O Circuit
Column select
Data
cont
A9
I/O1~I/O8
A10
A11
A12
A13
Data
cont
I/O9~I/O16
Data
cont
Name
CS
Function
Name
Function
Column Addresses
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Vcc Power
Vss Ground
OE
CS
OE
WE
UB
LB
WE
UB
LB
Upper Byte(I/O9~16)
Lower Byte(I/O1~8)
A0~A18
Control Logic
I/O1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 1.0
September 2003
2
K6X8016C3B Family
CMOS SRAM
PRODUCT LIST
Commercial Products(0~70°C)
Industrial Products(-40~85°C)
Automotive Products(-40~125°C)
Part Name
Function
Part Name
Function
Part Name
Function
K6X8016C3B-TB55
K6X8016C3B-TB70
44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
K6X8016C3B-TF55
K6X8016C3B-TF70
44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
K6X8016C3B-TQ55
K6X8016C3B-TQ70
44-TSOP2-F, 55ns, L
44-TSOP2-F, 70ns, L
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X
H
X
L
WE
X
LB
X
X
H
L
UB
X
X
H
H
L
I/O1~8
High-Z
I/O9~16
Mode
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
High-Z
High-Z
High-Z
High-Z
Dout
Deselected
H
X
High-Z
High-Z
Dout
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
L
H
H
H
L
L
L
H
L
High-Z
Dout
L
L
L
Dout
L
L
H
L
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
X
X
X
L
L
H
L
High-Z
Din
L
L
L
Din
Note: X means don¢t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOUT
VCC
Ratings
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to
Power Dissipation
-0.5 to VCC+0.5V(max.7.0V)
-
-0.3 to 7.0
1.0
V
-
PD
W
-
Storage temperature
TSTG
-65 to 150
0 to 70
°C
°C
°C
°C
-
K6X8016C3B-B
K6X8016C3B-F
K6X8016C3B-Q
Operating Temperature
TA
-40 to 85
-40 to 125
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 1.0
3
September 2003
K6X8016C3B Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
4.5
0
Typ
Max
5.5
0
Unit
V
Supply voltage
Ground
5.0
Vss
0
-
V
Vcc+0.52)
0.8
Input high voltage
Input low voltage
Note:
VIH
2.2
V
-0.53)
VIL
-
V
1. Commercial Product: TA=0 to 70°C, otherwise specified.
Industrial Product: TA=-40 to 85°C, otherwise specified.
Automotive Product: TA=-40 to 125°C, otherwise specified.
2. Overshoot: VCC+3.0V in case of pulse width £30ns.
3. Undershoot: -3.0V in case of pulse width £30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
-
1
1
6
mA
mA
Output leakage current
Operating power supply current
ILO
CS=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS=VIL, WE=VIH, VIN=VIH or VIL
ICC
mA
Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V, VIN£0.2V or
VIN³ VCC-0.2V
ICC1
-
-
7
mA
Average operating current
ICC2
VOL
VOH
ISB
Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIL or VIH
-
-
-
-
-
-
-
-
35
0.4
-
mA
V
Output low voltage
Output high voltage
Standby Current(TTL)
IOL = 2.1mA
-
IOH = -1.0mA
2.4
V
CS=VIH, Other inputs=VIH or VIL
K6X8016C3B-B
-
-
-
-
0.4
25
25
40
mA
Standby Current(CMOS)
ISB1
CS³ Vcc-0.2V, Other inputs=0~Vcc
mA
K6X8016C3B-F
K6X8016C3B-Q
Revision 1.0
September 2003
4
K6X8016C3B Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
)
1
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
CL
1.Including scope and jig capacitance
AC CHARACTERISTICS
(VCC=4.5~5.5V, Commercial product:TA=0 to 70°C, Industrial product:TA=-40 to 85°C, Automotive product:TA=-40 to 125°C)
Speed Bins
Parameter List
Symbol
Units
55ns
70ns
Min
55
-
Max
Min
70
-
Max
Read cycle time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
tCO
tOE
-
-
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Chip disable to high-Z output
Output Disable to High-Z Output
Output hold from address change
LB, UB valid to data output
UB, LB disable to high-Z output
Write cycle time
-
-
tLZ
10
5
10
5
tOLZ
tBLZ
tHZ
-
-
Read
5
-
5
-
0
20
20
-
0
25
25
-
tOHZ
tOH
tBA
0
0
10
-
10
-
25
20
-
35
25
-
tBHZ
tWC
tCW
tAS
0
0
55
45
0
70
60
0
Chip select to end of write
Address set-up time
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
-
60
55
0
-
-
-
Write
Write recovery time
-
-
Write to output high-Z
0
20
-
0
25
-
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
20
0
30
0
-
-
tOW
tBW
5
-
5
-
45
-
60
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
5.5
15
15
30
-
Unit
Vcc for data retention
VDR
CS³ Vcc-0.2V
2.0
-
-
-
-
-
-
-
V
K6X8016C3B-B
K6X8016C3B-F
K6X8016C3B-Q
Vcc=3.0V, CS³ Vcc-0.2V
CS³ Vcc-0.2V
Data retention current
IDR
mA
-
-
Data retention set-up time
Recovery time
tSDR
tRDR
0
5
See data retention waveform
ms
-
Revision 1.0
5
September 2003
K6X8016C3B Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 1.0
September 2003
6
K6X8016C3B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS
tWR(4)
tCW(2)
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
WE
tWP(1)
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
Revision 1.0
7
September 2003
K6X8016C3B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS
tCW(2)
tWR(4)
tAW
tBW
UB, LB
WE
tAS(3)
tWP(1)
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
Revision 1.0
8
September 2003
K6X8016C3B Family
CMOS SRAM
Unit: millimeters(inches)
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8°
0.25
0.010
(
)
#44
#23
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
0.020
(
)
#1
#22
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41±0.10
0.725±0.004
0.10
0.004
MAX
0.35± 0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
Revision 1.0
September 2003
9
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