K7A203600 [SAMSUNG]
64Kx36-Bit Synchronous Pipelined Burst SRAM; 64Kx36位同步流水线突发SRAM
| 型号： | K7A203600 |
| 厂家： | 
SAMSUNG |
| 描述： | 64Kx36-Bit Synchronous Pipelined Burst SRAM |
| 文件： | 总15页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
Document Title
64Kx36-Bit Synchronous Pipelined Burst SRAM
Revision History
Remark
Rev. No.
History
Draft Date
Preliminary
Preliminary
0.0
0.1
Initial draft
May. 19. 1998
July. 13. 1998
Change tOH Min value from 1.3 to 1.0 at tCYC 5.0
Change tHZC Min value from 1.3 to 1.0 at tCYC 5.0
Preliminary
0.2
Add tCYC 183MHz, 225MHz
Aug. 31. 1998
Change DC Characteristics.
Icc value from 260mA to 280mA at -72
ISB1 value from 10mA to 20mA
ISB2 value from 10mA to 20mA
Final
Final
1.0
2.0
Final spec release.
Nov. 16. 1998
Dec. 02. 1998
Add VDDQ Supply voltage( 2.5V )
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
64Kx36-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
GENERAL DESCRIPTION
The K7A203600A is a 2,359,296-bit Synchronous Static Ran-
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
dom Access Memory designed for high performance second
level cache of Pentium and Power PC based System.
It is organized as 64K words of 36bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applica-
tions; GW, BW, LBO, ZZ. Write cycles are internally self-timed
and synchronous.
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a
linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2 cycle Enable, 1 cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system¢s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
• 100-TQFP-1420A
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7A203600A is fabricated using SAMSUNG¢s high perfor-
mance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
FAST ACCESS TIMES
PARAMETER
Symbol -22 -20 -18 -16 -15 -14 Unit
Cycle Time
tCYC
tCD
4.4 5.0 5.4 6.0 6.7 7.2
3.1 3.1 3.1 3.5 3.8 4.0
3.1 3.1 3.1 3.5 3.8 4.0
ns
ns
ns
Clock Access Time
Output Enable Access Time
tOE
LOGIC BLOCK DIAGRAM
CLK
LBO
64Kx36
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
COUNTER
ADV
ADSC
A¢0~A¢1
ARRAY
A0~A1
A2~A15
ADDRESS
REGISTER
A0~A15
ADSP
DATA-IN
REGISTER
CS1
CS2
CS2
GW
BW
WEa
WEb
WEc
WEd
OUTPUT
REGISTER
CONTROL
LOGIC
BUFFER
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
- 2 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
1
2
3
4
5
6
7
8
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
N.C.
VDD
ZZ
VDD
N.C.
VSS
(20mm x 14mm)
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
PIN NAME
SYMBOL
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0-A15
32,33,34,35,36,37,
44,45,46,47,48,49,
81,82,99,100
VDD
VSS
N.C.
Power Supply(+3.3V)
Ground
No Connect
15,41,65,91
17,40,67,90
14,16,38,39,42,43,50,66
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
83
84
85
89
98
97
92
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
VDDQ
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
93,94,95,96
86
88
87
64
31
VSSQ
5,10,21,26,55,60,71,76
- 3 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A203600A is a synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC
based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration
of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2 cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC) using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BURST SEQUENCE TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
- 4 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS2
X
X
H
X
H
L
ADSP ADSC ADV WRITE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW
H
BW
H
L
WEa
X
WEb
X
WEc
X
WEd
X
OPERATION
READ
H
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ
H
L
OE
X
I/O STATUS
High-Z
Notes
1. X means
"Don¢t Care".
Sleep Mode
2. ZZ
pin is pulled down i
nternally
3. For write cycles
be disab
4. Sle
that following rea
d cycles, the outpu
t buffers must
L
DQ
Read
led with OE, otherw
ise data bus conten
power down state
d on cycle time.
ed means power
tion will occur.
of which stand-by
L
H
X
High-Z
ep Mode means
current
does not depen
5. Deselect
de
Write
L
Din, High-Z
High-Z
down state of wh
ich stand-by curre
nt
pends on cycle tim
e.
Deselected
L
X
- 5 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
PASS-THROUGH TRUTH TABLE
PREVIOUS CYCLE
PRESENT CYCLE
NEXT CYCLE
OPERATION
WRITE
OPERATION
CS1
WRITE
OE
Initiate Read Cycle
Address=An
Data=Qn-1 for all bytes
Write Cycle, All bytes
Address=An-1, Data=Dn-1
Read Cycle
Data=Qn
All L
L
H
L
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for all bytes
No carryover from
previous cycle
All L
All L
H
H
H
H
L
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=High-Z
No carryover from
previous cycle
H
Initiate Read Cycle
Address=An
Data=Qn-1 for one byte
Write Cycle, One byte
Address=An-1, Data=Dn-1
Read Cycle
Data=Qn
One L
One L
L
H
H
L
L
Write Cycle, One byte
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for one byte
No carryover from
previous cycle
H
Note : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
VDD
UNIT
V
VDDQ
VIN
V
-0.3 to 6.0
-0.3 to VDDQ+0.5
1.2
V
VIO
V
PD
W
°C
°C
°C
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0°C£ TA£70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.6
3.6
0
UNIT
V
V
V
VDDQ
VSS
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.6
2.9
0
UNIT
V
V
V
VDDQ
VSS
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
SYMBOL
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
CIN
-
-
5
7
pF
pF
Output Capacitance
COUT
VOUT=0V
*Note : Sampled not 100% tested.
- 6 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
MIN
MAX
+2
PARAMETER
SYMBOL
TEST CONDITIONS
VDD=Max ; VIN=VSS to VDD
UNIT
mA
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
-2
-2
-
mA
IOL
Output Disabled, VOUT=VSS to VDDQ
+2
-22
-20
-18
-16
-15
-14
-22
-20
-18
-16
-15
-14
440
400
380
360
320
280
110
100
100
90
-
Device Selected, IOUT=0mA,
ZZ£VIL, All Inputs=VIL or VIH
Cycle Time³ tCYC min
-
Operating Current
ICC
mA
-
-
-
-
-
Device deselected, IOUT = 0mA,
ZZ£VIL, f = Max,
All Inputs£0.2V or³ VDD-0.2V
-
ISB
mA
-
-
80
Standby Current
-
70
Device deselected, IOUT = 0mA, ZZ£0.2V,
ISB1
ISB2
-
-
20
20
mA
mA
f=0, All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA,
ZZ³ VDD-0.2V, f = Max, All Inputs£VIL or³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL = 8.0mA
IOH = -4.0mA
IOL = 1.0mA
IOH = -1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.5*
2.0
-0.3*
1.7
0.8
VIH
VIL
VDD+0.5**
0.7
VIH
VDD+0.5**
*
VIL(Min)=-2.0(Pulse Width £ tCYC/2)
** VIH(Max)=4.6(Pulse Width £ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
PARAMETER
VALUE
0 to 3V
0 to 2.5V
1ns
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
1ns
1.5V
VDDQ/2
See Fig. 1
- 7 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
Output Load(A)
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
Dout
RL=50W
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
319W / 1667W
30pF*
Dout
Z0=50W
353W / 1538W
5pF*
* Capacitive Load consists of all components of
the test environment.
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
-22
-20
-18
-16
-15
-14
Unit
SYMBOL
PARAMETER
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Cycle Time
tCYC
tCD
4.4
-
-
3.1
3.1
-
5.0
-
-
3.1
3.1
-
5.4
-
-
3.1
3.1
-
6.0
-
-
3.5
3.5
-
6.7
-
-
3.8
3.8
-
7.2
-
-
4.0
4.0
-
ns
ns
ns
ns
ns
ns
ns
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
tOE
-
-
-
-
-
-
tLZC
tOH
0
0
0
0
0
0
1.0
0
-
1.0
0
-
1.0
0
-
1.5
0
-
1.5
0
-
1.5
0
-
tLZOE
-
-
-
-
-
-
Output Enable High to Output High-Z
tHZOE
tHZC
tCH
-
3.1
-
3.1
-
3.1
-
3.5
-
3.8
-
4.0
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
1.0
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.5
0.5
0.5
0.5
0.5
0.5
2
3.1
-
1.0
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.5
0.5
0.5
0.5
0.5
0.5
2
3.1
-
1.0
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.5
0.5
0.5
0.5
0.5
0.5
2
3.1
-
1.5
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.5
-
1.5
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.8
-
1.5
2.8
2.8
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
4.0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCL
-
-
-
-
-
-
Address Setup to Clock High
tAS
-
-
-
-
-
-
Address Status Setup to Clock High
Data Setup to Clock High
tSS
-
-
-
-
-
-
tDS
-
-
-
-
-
-
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
tWS
-
-
-
-
-
-
tADVS
tCSS
tAH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Address Status Hold from Clock High
tSH
-
-
-
-
-
-
Data Hold from Clock High
tDH
-
-
-
-
-
-
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
tWH
tADVH
tCSH
tPDS
tPUS
-
-
-
-
-
-
-
-
-
-
-
-
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
-
-
-
-
-
-
ns
cycle
-
-
-
-
-
-
cycle
2
-
2
-
2
-
2
-
2
-
2
-
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
- 8 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
- 9 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
- 10 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
- 11 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
- 12 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
- 13 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 64Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 64K depth to 128K depth without extra logic.
I/O[0:71]
Data
Address
A[0:16]
A[16]
A[0:15]
A[16]
A[0:15]
Address Data
CS
CS
Address Data
CLK
2
CS
2
2
2
CS
64-Bits
Microprocessor
64Kx36
SPB
SRAM
64Kx36
SPB
SRAM
CLK
ADSC
WEx
OE
CLK
ADSC
WEx
OE
Address
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A2
A1
ADDRESS
[0:n]
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tHZC
tLZOE
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
Don¢t Care
Undefined
- 14 -
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
PACKAGE DIMENSIONS
Units:millimeters/inches
100-TQFP-1420A
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
14.00 ±0.20
0.10 MAX
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
- 15 -
December 1998
Rev 2.0
相关型号：
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