K7A323600M-HI220_技术文档

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

Document Title

1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM

Revision History

Rev. No.

History

Draft Date

Remark

0.0

0.1

0.2

1. Initial draft

May. 10. 2001

Aug. 29. 2001

Dec. 31. 2001

Advance

1. Add 165FBGA package

Preliminary

1. Update JTAG scan order

2. Speed bin merge.

From K7A3236(18)09M to K7A3236(18)00M.

3. AC parameter change.

tOH(min)/tHZC(min) from 0.8 to 1.5 at -25

tOH(min)/tHZC(min) from 1.0 to 1.5 at -22

tOH(min)/tHZC(min) from 1.0 to 1.5 at -20

0.3

0.4

1. Change pin out for 165FBGA

- x18/x36 ; 11B => from A to NC

Feb. 14. 2002

Apr. 20. 2002

Preliminary

, 2R ==> from NC to A .

1. Insert pin at JTAG scan order of 165FBGA in connection with pin out change

- x18/x36 ; insert Pin ID of 2R to BIT number of 69

0.5

1.0

1.1

1.2

1. Add Icc, Isb,Isb1 and Isb2 values

1. Correct the pin name of 100TQFP.

1. Add the Industrial temperature range.

1. Change the Stand-by current (Isb)

May.10. 2002

Oct. 15. 2002

Mar. 19, 2003

Oct. 17, 2003

Preliminary

Final

Before

Isb - 25 : 120

After

170

160

150

140

110

100

- 22 : 110

- 20 : 100

- 16 :

- 15 :

- 14 :

90

Isb1

Isb2

:

90

80

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

32Mb SB/SPB Synchronous SRAM Ordering Information

Speed

Org.

Part Number

Mode

VDD

SB ; Access Time(ns)

SPB ; Cycle Time(MHz)

PKG

Temp

K7B321825M-Q(H/F)C65/75/85

SB

3.3

6.5/7.5/8.5ns

C

(Commercial

Temperature

Range)

2Mx18

K7A321800M-Q(H/F)C(I)25/22/20/16/15/14 SPB(2E1D) 3.3 250/225/200/167/150/138MHz

Q: 100TQFP

H: 119BGA

F: 165FBGA

K7A321801M-QC25/22/20/16/15/14

K7B323625M-Q(H/F)C65/75/85

SPB(2E2D) 3.3 250/225/200/167/150/138MHz

SB 3.3 6.5/7.5/8.5ns

I

(Industrial

Temperature

Range)

1Mx36

K7A323600M-Q(H/F)C(I)25/22/20/16/15/14 SPB(2E1D) 3.3 250/225/200/167/150/138MHz

K7A323601M-QC25/22/20/16/15/14 SPB(2E2D) 3.3 250/225/200/167/150/138MHz

- 2 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM

FEATURES

GENERAL DESCRIPTION

• Synchronous Operation.

• 2 Stage Pipelined operation with 4 Burst.

• On-Chip Address Counter.

The K7A323600M and K7A321800M are 37,748,736-bit

Synchronous Static Random Access Memory designed for

high performance second level cache of Pentium and

Power PC based System.

• Self-Timed Write Cycle.

• On-Chip Address and Control Registers.

• VDD= 3.3V +0.165V/-0.165V Power Supply.

• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O.

It is organized as 1M(2M) words of 36(18) bits and inte-

grates address and control registers, a 2-bit burst address

counter and added some new functions for high perfor-

mance cache RAM applications; GW, BW, LBO, ZZ. Write

cycles are internally self-timed and synchronous.

Full bus-width write is done by GW, and each byte write is

performed by the combination of WEx and BW when GW is

high. And with CS1 high, ADSP is blocked to control sig-

nals.

• 5V Tolerant Inputs Except I/O Pins.

• Byte Writable Function.

• Global Write Enable Controls a full bus-width write.

• Power Down State via ZZ Signal.

• LBO Pin allows a choice of either a interleaved burst or a linear

burst.

• Three Chip Enables for simple depth expansion with No Data Con-

tention only for TQFP ; 2cycle Enable, 1cycle Disable.

• Asynchronous Output Enable Control.

• ADSP, ADSC, ADV Burst Control Pins.

• TTL-Level Three-State Output.

• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)

• 165FBGA(11x15 ball aray) with body size of 15mmx17mm.

• Operating in commeical and industrial temperature range.

Burst cycle can be initiated with either the address status

processor(ADSP) or address status cache control-

ler(ADSC) inputs. Subsequent burst addresses are gener-

ated internally in the system¢s burst sequence and are

controlled by the burst address advance(ADV) input.

LBO pin is DC operated and determines burst

sequence(linear or interleaved).

ZZ pin controls Power Down State and reduces Stand-by

current regardless of CLK.

FAST ACCESS TIMES

The K7A323600M and K7A321800M are fabricated using

SAMSUNG¢s high performance CMOS technology and is

available in a 100pin TQFP, 119BGA and 165FBGA pack-

age. Multiple power and ground pins are utilized to mini-

mize ground bounce.

PARAMETER

Cycle Time

Clock Access Time

Symbol -25 -22 -20 -16 -15 -14 Unit

tCYC

tCD

4.0 4.4 5.0 6.0 6.7 7.2 ns

2.6 2.8 3.1 3.5 3.8 4.0 ns

Output Enable Access Time tOE

LOGIC BLOCK DIAGRAM

CLK

LBO

1Mx36 , 2Mx18

BURST CONTROL

LOGIC

BURST

MEMORY

ADDRESS

COUNTER

ADV

ADSC

A¢0~A¢1

ARRAY

A0~A1

A

2

~A19

or A2~A20

A

0

~A19

ADDRESS

REGISTER

or A0~A20

ADSP

DATA-IN

REGISTER

CS

1

2

GW

BW

OUTPUT

REGISTER

CONTROL

LOGIC

BUFFER

WEx

(x=a,b,c,d or a,b)

OE

ZZ

DQa0 ~ DQd 7 or DQa0 ~ DQb7

DQPa ~ DQPd DQPa,DQPb

- 3 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQPb

DQb7

DQb6

VDDQ

VSSQ

DQb5

DQb4

DQb3

DQb2

VSSQ

VDDQ

DQb1

DQb0

VSS

DQPc

DQc0

DQc1

VDDQ

VSSQ

DQc2

DQc3

DQc4

DQc5

VSSQ

VDDQ

DQc6

DQc7

N.C.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

N.C.

VDD

N.C.

VSS

(20mm x 14mm)

VDD

ZZ

DQd0

DQd1

VDDQ

VSSQ

DQd2

DQd3

DQd4

DQd5

VSSQ

VDDQ

DQd6

DQd7

DQPd

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa

K7A323600M(1Mx36)

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A19

Address Inputs

32,33,34,35,36,37,39 VDD

42,43,44,45,46,47,48, VSS

49,50,81,82,99,100

Power Supply(+3.3V) 15,41,65,91

Ground

17,40,67,90

14,16,38,66

ADV

ADSP

ADSC

CLK

CS1

CS2

Burst Address Advance

Address Status Processor 84

Address Status Controller 85

83

No Connect

Data Inputs/Outputs

N.C.

52,53,56,57,58,59,62,63

68,69,72,73,74,75,78,79

2,3,6,7,8,9,12,13

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

Clock

89

98

97

Chip Select

18,19,22,23,24,25,28,29

51,80,1,30

CS2

92

WEx(x=a,b,c,d) Byte Write Inputs

93,94,95,96

OE

Output Enable

86

88

87

64

31

Output Power Supply 4,11,20,27,54,61,70,77

(3.3V or 2.5V)

VDDQ

VSSQ

GW

BW

ZZ

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

Output Ground

5,10,21,26,55,60,71,76

LBO

Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

- 4 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

PIN CONFIGURATION(TOP VIEW)

A10

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

N.C.

VDDQ

VSSQ

N.C.

DQb0

DQb1

VSSQ

VDDQ

DQb2

DQb3

N.C.

VDD

1

2

3

4

5

6

7

N.C.

VDDQ

VSSQ

N.C.

DQPa

DQa7

DQa6

VSSQ

VDDQ

DQa5

DQa4

VSS

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

(20mm x 14mm)

N.C.

VDD

ZZ

N.C.

VSS

DQb4

DQb5

VDDQ

VSSQ

DQb6

DQb7

DQPb

N.C.

VSSQ

VDDQ

N.C.

DQa3

DQa2

VDDQ

VSSQ

DQa1

DQa0

N.C.

VSSQ

VDDQ

N.C.

K7A321800M(2Mx18)

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A20

Address Inputs

32,33,34,35,36,37,39

VDD

Power Supply(+3.3V) 15,41,65,91

42,43,44,45,46,47,48, VSS

49,50 80,81,82,99,100

Ground

17,40,67,90

ADV

ADSP

ADSC

CLK

CS1

Burst Address Advance

83

No Connect

1,2,3,6,7,14,16,25,28,29

30,38,51,52,53,56,57

66,75,78,79,95,96

N.C.

Address Status Processor 84

Address Status Controller

Clock

85

89

Chip Select

98

97

92

Data Inputs/Outputs

58,59,62,63,68,69,72,73

8,9,12,13,18,19,22,23

74,24

DQa0 ~ a7

DQb0 ~ b7

DQPa, Pb

CS2

WEx(x=a,b) Byte Write Inputs

93,94

86

OE

Output Enable

Output Power Supply 4,11,20,27,54,61,70,77

(3.3V or 2.5V)

VDDQ

VSSQ

GW

BW

ZZ

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

88

87

64

31

Output Ground

5,10,21,26,55,60,71,76

LBO

Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

- 5 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7A323600M(1Mx36)

1

2

A

3

4

ADSP

ADSC

VDD

NC

5

6

A

7

A

B

C

D

E

F

VDDQ

NC

A

VDDQ

NC

A

NC

A

NC

DQc

VDDQ

DQc

VDDQ

DQd

VDDQ

DQd

NC

DQPc

DQc

VDD

DQd

DQPd

A

VSS

WEc

VSS

NC

VSS

WEd

VSS

LBO

A

VSS

WEb

VSS

NC

VSS

WEa

VSS

NC

A

DQPb

DQb

VDD

DQa

DQPa

A

DQb

VDDQ

DQb

VDDQ

DQa

VDDQ

DQa

NC

CS1

OE

G

H

J

ADV

GW

VDD

CLK

NC

K

L

M

N

P

R

T

BW

A1*

A0*

VDD

A

NC

A

ZZ

U

*

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Note :

A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

Power Supply(+3.3V)

A

Address Inputs

VDD

VSS

A0, A1

Burst Count Address

Ground

ADV

Burst Address Advance

Address Status Processor

Address Status Controller

Clock

N.C.

No Connect

ADSP

ADSC

CLK

DQa

DQb

DQc

DQd

Data Inputs/Outputs

Data Inputs/Outpus

CS1

WEx

(x=a,b,c,d)

Chip Select

Byte Write Inputs

DQPa~Pd

OE

GW

BW

ZZ

Output Enable

VDDQ

Output Power Supply

(2.5V or 3.3V)

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

LBO

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

- 6 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7A321800M(2Mx18)

1

2

A

3

4

ADSP

ADSC

VDD

NC

5

6

A

7

A

B

C

D

E

F

VDDQ

NC

A

VDDQ

NC

A

NC

A

NC

DQb

NC

VSS

WEb

VSS

NC

VSS

LBO

A

VSS

NC

VSS

WEa

VSS

NC

A

DQPa

NC

DQa

NC

DQa

VDD

NC

DQa

NC

DQa

NC

A

NC

DQb

NC

CS1

OE

DQa

VDDQ

DQa

NC

VDDQ

NC

G

H

J

DQb

NC

ADV

GW

VDD

CLK

NC

DQb

VDDQ

NC

VDD

DQb

NC

VDDQ

DQa

NC

K

L

DQb

VDDQ

DQb

NC

M

N

P

R

T

DQb

NC

BW

VDDQ

NC

A1*

DQPb

A0*

DQa

NC

VDD

A

NC

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

Power Supply(+3.3V)

A

A0,A1

Address Inputs

VDD

VSS

Burst Count Address

Ground

ADV

Burst Address Advance

Address Status Processor

Address Status Controller

Clock

N.C.

No Connect

ADSP

ADSC

CLK

DQa

DQb

DQPa~Pb

Data Inputs/Outputs

Data Inputs/Outpus

CS1

Chip Select

WEx

Byte Write Inputs

(x=a,b)

VDDQ

Output Power Supply

(2.5V or 3.3V)

OE

Output Enable

GW

BW

ZZ

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

LBO

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

- 7 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)

K7A323600M(1Mx36)

1

2

3

4

5

6

7

8

ADSC

OE

9

10

A

11

NC

CS2

A

B

C

D

E

F

NC

A

CS 1

WEc

WEd

VSS

VDD

VSS

A

WEb

WEa

VSS

NC

BW

ADV

NC

A

CS2

CLK

VSS

A

GW

VSS

TDO

TCK

ADSP

VDDQ

NC

A

NC

DQPc

DQc

NC

VDDQ

NC

VSS

VDD

VSS

A

NC

DQPb

DQb

ZZ

DQc

VSS

DQd

NC

DQb

NC

G

H

J

DQd

DQPd

NC

VDDQ

A

VDDQ

A

DQa

NC

DQa

DQPa

A

K

L

M

N

P

R

NC

TDI

TMS

A1*

A

LBO

A

A0*

A

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

Power Supply(+3.3V)

A

Address Inputs

VDD

VSS

A0, A1

Burst Count Address

Ground

ADV

Burst Address Advance

Address Status Processor

Address Status Controller

Clock

N.C.

No Connect

ADSP

ADSC

CLK

DQa

DQb

DQc

DQd

Data Inputs/Outputs

Data Inputs/Outpus

CS1

Chip Select

WEx

(x=a,b,c,d)

Byte Write Inputs

DQPa~Pd

OE

GW

BW

ZZ

Output Enable

VDDQ

Output Power Supply

(2.5V or 3.3V)

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

LBO

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

- 8 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)

K7A321800M(2Mx18)

1

NC

2

A

3

4

5

6

7

8

ADSC

OE

9

10

A

11

A

CS2

A

B

C

D

E

F

CS 1

WEb

NC

BW

ADV

NC

A

CS2

WEa

VSS

NC

CLK

VSS

A

GW

VSS

TDO

TCK

ADSP

VDDQ

NC

A

NC

DQPa

DQa

ZZ

NC

DQb

VSS

NC

A

VDDQ

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

NC

DQa

NC

A

NC

G

H

J

NC

DQb

DQPb

NC

VDDQ

A

VDDQ

A

NC

A

K

L

M

N

P

R

TDI

TMS

A1*

LBO

A

A0*

A

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

Power Supply(+3.3V)

A

A0,A1

Address Inputs

VDD

VSS

Burst Count Address

Ground

ADV

Burst Address Advance

Address Status Processor

Address Status Controller

Clock

N.C.

No Connect

ADSP

ADSC

CLK

DQa

DQb

DQPa~Pb

Data Inputs/Outputs

Data Inputs/Outpus

CS1

Chip Select

WEx

Byte Write Inputs

(x=a,b)

VDDQ

Output Power Supply

(2.5V or 3.3V)

OE

Output Enable

GW

BW

ZZ

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

LBO

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

- 9 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

FUNCTION DESCRIPTION

The K7A323600M and K7A321800M are synchronous SRAM designed to support the burst address accessing sequence of the

Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and

duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.

The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with

ADV.

When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ

returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.

Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address

register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-

ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-

ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output

pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address

increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to

control signals by disabling CS 1.

All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx

when GW is high.

Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-

ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled

Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the

next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte

write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7

and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-

ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;

ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).

Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external

address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state

of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is

selected.

BURST SEQUENCE TABLE

(Interleaved Burst)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

BQ TABLE

(Linear Burst)

Case 1

Case 2

Case 3

Case 4

A0

LBO PIN

LOW

First Address

A1

A0

A1

A0

A1

A0

A1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

ASYNCHRONOUS TRUTH TABLE

Operation

ZZ

H

L

OE

X

I/O STATUS

High-Z

Notes

1. X means "Don¢t Care".

2. ZZ pin is pulled down internally

3. For write cycles that following read cycles, the output buffers must be

disabled with OE, otherwise data bus contention will occur.

4. Sleep Mode means power down state of which stand-by current does

not depend on cycle time.

Sleep Mode

L

DQ

Read

L

H

High-Z

Write

L

X

Din, High-Z

High-Z

5. Deselected means power down state of which stand-by current

depends on cycle time.

Deselected

L

X

- 10 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1

H

L

CS2

X

L

CS 2 ADSP ADSC ADV WRITE CLK

ADDRESS ACCESSED

N/A

OPERATION

Not Selected

X

H

X

H

L

X

L

X

L

X

L

•

X

L

N/A

Not Selected

L

X

L

N/A

Not Selected

L

X

L

N/A

Not Selected

L

X

H

X

L

N/A

Not Selected

L

X

L

External Address

Next Address

Current Address

Begin Burst Read Cycle

Begin Burst Write Cycle

Begin Burst Read Cycle

Continue Burst Read Cycle

Continue Burst Write Cycle

Suspend Burst Read Cycle

Suspend Burst Write Cycle

L

H

X

H

X

H

X

H

X

L

H

L

X

H

X

H

X

H

X

H

X

H

L

H

L

Notes : 1. X means "Don¢t Care".

2. The rising edge of clock is symbolized by • .

3. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

4. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE(x36)

GW

H

BW

H

L

WEa

X

WEb

X

WEc

X

WEd

OPERATION

READ

X

H

L

H

READ

H

L

H

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c and d

WRITE ALL BYTEs

H

L

H

L

H

L

H

L

H

L

X

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

WRITE TRUTH TABLE(x18)

GW

H

BW

H

L

WEa

X

WEb

OPERATION

X

H

L

READ

H

READ

H

L

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

H

L

H

L

X

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

- 11 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on VDDQ Supply Relative to VSS

Voltage on Input Pin Relative to VSS

Voltage on I/O Pin Relative to VSS

Power Dissipation

SYMBOL

VDD

RATING

-0.3 to 4.6

VDD

UNIT

V

VDDQ

VIN

V

-0.3 to VDD+0.3

-0.3 to VDDQ+0.3

1.6

V

VIO

V

PD

W

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

°C

Commercial

Industrial

Operating Temperature

-40 to 85

-10 to 85

Storage Temperature Range Under Bias

*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

MIN

3.135

0

Typ.

3.3

0

MAX

3.465

0

UNIT

VDD

V

VDDQ

VSS

OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

MIN

3.135

2.375

0

Typ.

3.3

2.5

0

MAX

3.465

2.9

UNIT

VDD

V

VDDQ

VSS

0

CAPACITANCE*(TA=25°C, f=1MHz)

PARAMETER

Input Capacitance

SYMBOL

TEST CONDITION

VIN=0V

MIN

MAX

UNIT

CIN

-

5

7

pF

Output Capacitance

COUT

VOUT=0V

*Note : Sampled not 100% tested.

- 12 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = Max ; VIN=VSS to VDD

MIN

MAX

+2

UNIT NOTES

Input Leakage Current(except ZZ)

Output Leakage Current

IIL

-2

-

mA

IOL

Output Disabled, VOUT=VSS to VDDQ

+2

-25

-22

-20

-16

-15

-14

-25

-22

-20

-16

-15

-14

460

440

410

360

330

310

170

160

150

140

-

Device Selected, IOUT=0mA,

ZZ£VIL , Cycle Time ³ tCYC Min

Operating Current

ICC

mA

1,2

-

Device deselected, IOUT=0mA,

ZZ£VIL, f=Max,

-

ISB

mA

-

All Inputs£0.2V or ³ V DD-0.2V

-

Standby Current

-

Device deselected, IOUT=0mA, ZZ£0.2V,

f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)

ISB1

ISB2

-

110

100

mA

Device deselected, IOUT=0mA, ZZ³ VDD-

0.2V, f=Max, All Inputs£VILor ³ VIH

Output Low Voltage(3.3V I/O)

Output High Voltage(3.3V I/O)

Output Low Voltage(2.5V I/O)

Output High Voltage(2.5V I/O)

Input Low Voltage(3.3V I/O)

nput High Voltage(3.3V I/O)

Input Low Voltage(2.5V I/O)

Input High Voltage(2.5V I/O)

VOL

VOH

VOL

VOH

VIL

IOL=8.0mA

IOH=-4.0mA

IOL=1.0mA

IOH=-1.0mA

-

0.4

V

2.4

-

0.4

-

2.0

-0.3*

2.0

-0.3*

1.7

0.8

VDD+0.3**

0.7

3

VIH

VIL

VIH

VDD+0.3**

Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.

2. Data states are all zero.

3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V.

VIH

VSS

VSS-1.0V

20% tCYC (MIN)

TEST CONDITIONS

(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)

PARAMETER

VALUE

0 to 3.0V

0 to 2.5V

1.0V/ns

1.5V

Input Pulse Level(for 3.3V I/O)

Input Pulse Level(for 2.5V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)

Input and Output Timing Reference Levels for 3.3V I/O

Input and Output Timing Reference Levels for 2.5V I/O

Output Load

VDDQ/2

See Fig. 1

- 13 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

Output Load(A)

Output Load(B),

(for tLZC, tLZOE, tHZOE & tHZC)

+3.3V for 3.3V I/O

/+2.5V for 2.5V I/O

RL=50W

Dout

VL=1.5V for 3.3V I/O

VDDQ /2 for 2.5V I/O

319W / 1667W

30pF*

Dout

Zo=50W

353W / 1538W

5pF*

* Including Scope and Jig Capacitance

Fig. 1

AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

-25

-22

-20

-16

-15

-14

Parameter

Symbol

Unit

Min MAX Min Max MIN MAX Min Max Min Max Min Max

Cycle Time

tCYC

tCD

4.0

-

2.6

-

4.4

-

2.8

-

5.0

-

3.1

-

6.0

-

3.5

-

6.7

-

3.8

-

7.2

-

4.0

-

ns

Clock Access Time

-

Output Enable to Data Valid

tOE

-

ns

Clock High to Output Low-Z

Output Hold from Clock High

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

Clock High Pulse Width

tLZC

tOH

tLZOE

tHZOE

tHZC

tCH

0

ns

1.5

0

-

1.5

0

-

1.5

0

-

1.5

0

-

1.5

0

-

1.5

0

-

ns

-

ns

-

2.6

-

2.8

-

3.0

-

3.0

-

3.0

-

3.5

ns

1.5 2.6 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.5

ns

1.7

1.2

0.3

2

-

1.8

1.4

0.4

2

-

2.0

1.4

0.4

2

-

2.1

1.5

0.5

2

-

2.3

1.5

0.5

2

-

2.5

1.5

0.5

2

-

ns

Clock Low Pulse Width

tCL

ns

Address Setup to Clock High

Address Status Setup to Clock High

Data Setup to Clock High

tAS

ns

tSS

ns

tDS

ns

Write Setup to Clock High (GW, BW, WEX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

Address Status Hold from Clock High

Data Hold from Clock High

tWS

ns

tADVS

tCSS

tAH

ns

tSH

ns

tDH

ns

Write Hold from Clock High (GW, BW,

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWH

ns

tADVH

tCSH

tPDS

tPUS

ns

cycle

ZZ Low to Power Up

2

Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and

CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.

3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.

- 14 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

JTAG Block Diagram

JTAG Instruction Coding

IR2 IR1 IR0 Instruction

TDO Output

Notes

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EXTEST

IDCODE

SAMPLE-Z

BYPASS

SAMPLE

Boundary Scan Register

Identification Register

Boundary Scan Register

Bypass Register

1

3

2

4

5

6

4

Boundary Scan Register

RESERVED Do Not Use

SRAM

CORE

BYPASS

Bypass Register

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

TDI

BYPASS Reg.

TDO

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

Identification Reg.

Instruction Reg.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

Control Signals

TAP Controller

TMS

TCK

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

TAP Controller State Diagram

1

0

Test Logic Reset

0

1

0

1

Run Test Idle

Select DR

0

Select IR

0

1

Capture DR

0

Capture IR

0

Shift DR

1

Shift IR

1

Exit1 DR

0

Exit1 IR

0

Pause DR

1

Pause IR

1

Exit2 DR

1

Exit2 IR

1

0

Update DR

0

Update IR

1

- 15 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

SCAN INFORMATION ( 119 BGA )

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

1 bits

ID Register

32 bits

Boundary Scan

77 bits

1Mx36

2Mx18

3 bits

1 bits

32 bits

77 bits

ID REGISTER DEFINITION

Revision Number

Part

Part Configuration Vendor Definition Samsung JEDEC Code

Start Bit(0)

(31:28)

(27:18)

(17:12)

XXXXXX

(11: 1)

1Mx36

2Mx18

0000

01000 00100

01001 00011

00001001110

1

BOUNDARY SCAN EXIT ORDER

BIT

PIN ID(x18)

PIN ID(x36)

BIT

PIN ID(x18)

PIN ID(x36)

1

4H

4T

5T

6T

5L

6R

5R

7R

5J

4H

4T

5T

6T

5L

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

4B

4E

4G

4A

3G

3C

2B

3B

3A

2C

2A

1B

2D

1E

2F

1G

2H

1D

2E

2G

1H

2K

1L

4B

4E

4G

4A

3G

3C

2B

3B

3A

2C

2A

1B

2D

1E

2F

1G

2H

1D

2E

2G

1H

2K

1L

2M

1N

1P

1K

2L

2N

2P

2T

3R

1T

3L

2R

3T

4N

4P

2

3

4

5

6

6R

5R

7R

5J

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

7T

6P

7N

6M

7L

6K

7P

6N

6L

7K

6H

7G

6F

7E

6D

7H

6G

6E

7D

7B

6C

6A

5C

5B

5G

6B

4F

4M

5A

4K

7T

6P

7N

6M

7L

6K

7P

6N

6L

7K

6H

7G

6F

7E

7D

7H

6G

6E

6D

7B

6C

6A

5C

5B

5G

6B

4F

4M

5A

4K

2M

1N

2P

1K

2L

2N

1P

1T

3R

2T

3L

2R

3T

4N

4P

Note: 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. don¢t care).

- 16 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

SCAN INFORMATION (165 FBGA )

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

1 bits

ID Register

32 bits

Boundary Scan

75 bits

1Mx36

2Mx18

3 bits

1 bits

32 bits

75 bits

ID REGISTER DEFINITION

Revision Number

Part

Part Configuration Vendor Definition Samsung JEDEC Code

Start Bit(0)

(31:28)

(27:18)

(17:12)

XXXXXX

(11: 1)

1Mx36

2Mx18

0000

01000 00100

01001 00011

00001001110

1

BOUNDARY SCAN EXIT ORDER

BIT

PIN ID(x18)

PIN ID(x36)

BIT

PIN ID(x18)

PIN ID(x36)

1

6N

8P

6N

8P

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1A

1C

1D

1E

1F

1G

2D

2E

2F

2G

1J

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1A

1C

1D

1E

1F

1G

2D

2E

2F

2G

1J

2

3

8R

4

9R

5

9P

6

10P

10R

11R

11P

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

11C

10F

10E

10D

10G

11A

11B

10A

10B

9A

10P

10R

11R

11P

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

10G

10F

10E

10D

11C

11A

11B

10A

10B

9A

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

1K

1L

1K

1L

1M

2J

1M

1N

2K

2L

2K

2L

2M

1N

2R

1R

3P

3R

4R

4P

6P

6R

2M

2J

2R

1R

3P

3R

4R

4P

6P

6R

9B

8A

8B

7A

7B

6B

Note: 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. don¢t care).

- 17 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

JTAG DC OPERATING CONDITIONS

Parameter

Power Supply Voltage

Symbol

Min

3.135

2.0 / 1.7

-0.3

Typ

Max

3.465

Unit

V

Note

VDD

VIH

VIL

3.3

Input High Level ( 3.3V I/O / 2.5V I/O )

Input Low Level ( 3.3V I/O / 2.5V I/O )

Output High Voltage( 3.3V I/O / 2.5V I/O )

Output Low Voltage( 3.3V I/O / 2.5V I/O )

-

VDD+0.3

0.8 / 0.7

-

V

VOH

VOL

2.4 / 2.0

-

V

0.4 / 0.4

V

NOTE : The input level of SRAM pin is to follow the SRAM DC specification.

JTAG AC TEST CONDITIONS

Parameter

Symbol

VIH/VIL

TR/TF

Min

Unit

V

Note

Input High/Low Level( 3.3V I/O , 2.5V I/O )

Input Rise/Fall Time( 3.3V I/O , 2.5V I/O )

Input and Output Timing Reference Level

3.0/0 , 2.5/0

1.0/1.0 , 1.0/1.0

VDDQ/2

ns

V

JTAG AC Characteristics

Parameter

TCK Cycle Time

Symbol

Min

50

20

5

Max

Unit

Note

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tDVCH

tCHDX

tSVCH

tCHSX

tCLQV

-

ns

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

5

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

5

0

10

JTAG TIMING DIAGRAM

TCK

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tCHDX

TMS

TDI

tDVCH

tSVCH

tCHSX

PI

(SRAM)

tCLQV

TDO

- 18 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

- 19 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

- 20 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

- 21 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

- 22 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

- 23 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

APPLICATION INFORMATION

DEPTH EXPANSION

The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.

This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.

I/O[0:71]

Data

Address

A[0:19]

A[19]

A[0:18]

A[19]

A[0:18]

Address Data

CS2

CLK

CS2

CLK

ADSC

WEx

OE

CS2

CLK

ADSC

WEx

OE

512Kx36

SPB

SRAM

512Kx36

SPB

SRAM

Microprocessor

Address

CLK

(Bank 1)

(Bank 0)

Cache

Controller

CS1

ADV ADSP

ADS

INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)

(ADSP CONTROLLED , ADSC=HIGH)

Clock

tSS

tSH

ADSP

tAS

tAH

A1

A2

ADDRESS

[0:n]

tWS

tWH

WRITE

CS1

tCSS

tCSH

Bank 0 is selected by CS2, and Bank 1 deselected by CS2

An+1

ADV

OE

Bank 0 is deselected by CS2, and Bank 1 selected byCS2

tADVS

tADVH

tOE

tHZC

tLZOE

Data Out

(Bank 0)

Q1-1

Q1-2

Q1-3

Q1-4

tCD

tLZC

Data Out

(Bank 1)

Q2-1

Q2-2

Q2-3

Q2-4

*Notes : n = 14 32K depth ,

15 64K depth

16 128K depth , 17 256K depth

18 512K depth , 19 1M depth

Don¢t Care

Undefined

- 24 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

APPLICATION INFORMATION

DEPTH EXPANSION

The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.

This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.

I/O[0:71]

Data

Address

A[20]

A[0:20]

A[0:19]

Address Data

CS

Address Data

CS

CLK

2

Microprocessor

CLK

ADSC

WEx

OE

1Mx18

SPB

SRAM

CLK

ADSC

WEx

OE

1Mx18

SPB

SRAM

Address

CLK

(Bank 0)

(Bank 1)

Cache

Controller

CS1

ADV ADSP

ADS

INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)

(ADSP CONTROLLED , ADSC=HIGH)

Clock

tSS

tSH

ADSP

tAS

tAH

A1

A2

ADDRESS

[0:n]

tWS

tWH

WRITE

CS 1

tCSS

tCSH

Bank 0 is selected by CS2, and Bank 1 deselected byCS2

An+1

ADV

OE

Bank 0 is deselected byCS2, and Bank 1 selected by CS2

tADVS

tADVH

tOE

tLZOE

tHZC

Data Out

(Bank 0)

Q1-1

Q1-2

Q1-3

Q1-4

tCD

tLZC

Data Out

(Bank 1)

Q2-1

Q2-2

Q2-3

Q2-4

*Notes

:

n = 14 32K depth ,

15 64K depth

16 128K depth , 17 256K depth

18 512K depth , 19 1M depth

20 2M depth

Undefined

Don¢t Care

- 25 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

PACKAGE DIMENSIONS

100-TQFP-1420A

Units ; millimeters/Inches

22.00 ± 0.30

20.00 ± 0.20

0~8°

0.127^{+ 0.10}

- 0.05

16.00 ±0.30

0.10 MAX

14.00 ± 0.20

(0.83)

0.50 ±0.10

#1

0.65

(0.58)

0.30 ± 0.10

0.10 MAX

1.40 ± 0.10

1.60 MAX

0.05 MIN

0.50 ±0.10

- 26 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

119 BGA PACKAGE DIMENSIONS

1.27

14.00±0.10

22.00±0.10

Indicator of

Ball(1A) Location

20.50±0.10

C0.70

C1.00

0.750±0.15

1.50REF

0.60±0.10

NOTE :

1. All Dimensions are in Millimeters.

12.50±0.10

2. Solder Ball to PCB Offset : 0.10 MAX.

3. PCB to Cavity Offset : 0.10 MAX.

- 27 -

Oct. 2003

Rev 1.2

K7A323600M

K7A321800M

1Mx36 & 2Mx18 Synchronous SRAM

165 FBGA PACKAGE DIMENSIONS

15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array

A

B

Top View

C

Side View

D

A

F

E

B

G

Bottom View

Æ H

E

Symbol

Value

17 ± 0.1

15 ± 0.1

1.3 ± 0.1

0.35 ± 0.05

Units

mm

Note

Symbol

Value

1.0

Units

mm

Note

A

B

C

D

E

F

14.0

10.0

mm

G

H

mm

0.5 ± 0.05

mm

- 28 -

Oct. 2003

Rev 1.2


型号：	K7A323600M-HI220
厂家：	SAMSUNG
描述：	Cache SRAM, 1MX36, 2.8ns, CMOS, PBGA119, BGA-119 静态存储器
文件：	总28页 (文件大小：351K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7A323600M-HI220 [SAMSUNG]

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