K7A323601M-QC200 [SAMSUNG]
Cache SRAM, 1MX36, 3.1ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100;
| 型号： | K7A323601M-QC200 |
| 厂家： | 
SAMSUNG |
| 描述： | Cache SRAM, 1MX36, 3.1ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
Document Title
1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
History
Draft Date
Remark
May. 10. 2001
Dec. 31. 2001
0.0
0.1
1. Initial draft
Advance
1. Speed bin merge.
Preliminary
From K7A3236(18)08M to K7A3236(18)01M.
2. AC parameter change.
tOH(min)/tHZC(min) from 0.8 to 1.5 at -25
tOH(min)/tHZC(min) from 1.0 to 1.5 at -22
tOH(min)/tHZC(min) from 1.0 to 1.5 at -20
May. 10. 2002
Oct. 15. 2002
Oct. 17, 2003
0.2
1.0
1.1
1. Add Icc, Isb, Isb1 and Isb2 values.
1. Correct the pin name of 100TQFP.
Preliminary
Final
1. Change the Stand-by current (Isb)
Before After
Final
Isb - 25 : 120
- 22 : 110
- 20 : 100
170
160
150
140
140
140
110
100
- 16 :
- 15 :
90
90
90
- 14 :
Isb1
Isb2
:
:
90
80
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
32Mb SB/SPB Synchronous SRAM Ordering Information
Speed
Org.
Part Number
Mode
VDD
SB ; Access Time(ns)
SPB ; Cycle Time(MHz)
PKG
Temp
K7B321825M-Q(H/F)C65/75/85
SB
3.3
6.5/7.5/8.5ns
2Mx18
K7A321800M-Q(H/F)C25/22/20/16/15/14 SPB(2E1D)
3.3 250/225/200/167/150/138MHz
3.3 250/225/200/167/150/138MHz
C
Q: 100TQFP
H: 119BGA
F: 165FBGA
K7A321801M-QC25/22/20/16/15/14
K7B323625M-Q(H/F)C65/75/85
SPB(2E2D)
SB
(Commercial
Temperature
Range)
3.3
6.5/7.5/8.5ns
1Mx36
K7A323600M-Q(H/F)C25/22/20/16/15/14 SPB(2E1D)
K7A323601M-QC25/22/20/16/15/14 SPB(2E2D)
3.3 250/225/200/167/150/138MHz
3.3 250/225/200/167/150/138MHz
- 2 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
The K7A323601M and K7A321801M are 37,748,736-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V +0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
It is organized as 1M(2M) words of 36(18) bits and integrates
address and control registers, a 2-bit burst address counter and
added some new functions for high performance cache RAM
applications; GW, BW, LBO, ZZ. Write cycles are internally self-
timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system¢s burst sequence and are controlled by the burst
address advance(ADV) input.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 2cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
• 100-TQFP-1420A Package
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time tOE
Symbol -25 -22 -20 -16 -15 -14 Unit
The K7A323601M and K7A321801M are fabricated using SAM-
SUNG¢s high performance CMOS technology and is available
in a 100pin TQFP package. Multiple power and ground pins are
utilized to minimize ground bounce.
tCYC 4.0 4.4 5.0 6.0 6.7 7.2 ns
tCD
2.6 2.8 3.1 3.5 3.8 4.0 ns
2.6 2.8 3.1 3.5 3.8 4.0 ns
LOGIC BLOCK DIAGRAM
CLK
LBO
1Mx36 , 2Mx18
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
COUNTER
ADV
ADSC
A¢0~A¢1
ARRAY
A0~A1
A2~A19
or A2~A20
A0~A19
ADDRESS
REGISTER
or A0~A20
ADSP
DATA-IN
REGISTER
CS1
CS2
CS2
GW
OUTPUT
REGISTER
CONTROL
LOGIC
BW
BUFFER
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb7
DQPa ~ DQPd
DQPa,DQPb
- 3 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
VDD
N.C.
VSS
VDD
ZZ
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
K7A323601M(1Mx36)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A19
Address Inputs
32,33,34,35,36,37,39 VDD
42,43,44,45,46,47,48 VSS
49,50,81,82,99,100
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
14,16,38,66
ADV
ADSP
ADSC
CLK
Burst Address Advance
Address Status Processor 84
Address Status Controller 85
83
No Connect
N.C.
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Clock
89
98
CS 1
Chip Select
Chip Select
Chip Select
CS 2
CS 2
97
92
18,19,22,23,24,25,28,29
51,80,1,30
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
88
87
64
31
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
VDDQ
VSSQ
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
Output Ground
5,10,21,26,55,60,71,76
LBO
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 4 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
A10
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
1
2
3
4
5
6
7
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
VDD
ZZ
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7A321801M(2Mx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A20
Address Inputs
32,33,34,35,36,37,39
VDD
Power Supply(+3.3V)
Ground
15,41,65,91
17,40,67,90
42,43,44,45,46,47,48, VSS
49,50 80,81,82,99,100
ADV
Burst Address Advance
83
No Connect
1,2,3,6,7,14,16,25,28,29
30,38,51,52,53,56,57
66,75,78,79,95,96
N.C.
ADSP
ADSC
Address Status Processor 84
Address Status Controller 85
CLK
CS1
CS2
CS2
Clock
89
Chip Select
Chip Select
Chip Select
98
97
92
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
DQa0 ~ a7
DQb0 ~ b7
DQPa, Pb
WEx(x=a,b) Byte Write Inputs
93,94
86
OE
Output Enable
Output Power Supply
(3.3V or 2.5V)
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
VDDQ
VSSQ
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
88
87
64
31
Output Ground
LBO
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 5 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A323601M and K7A321801M are synchronous SRAM designed to support the burst address accessing sequence of the
Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and
duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS 1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BQ TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
A0
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
ASYNCHRONOUS TRUTH TABLE
OPERATION
ZZ
H
L
OE
X
I/O Status
High-Z
Notes
1. X means "Don¢t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
Sleep Mode
L
DQ
Read
L
H
High-Z
Write
L
X
Din, High-Z
High-Z
5. Deselected means power down state of which stand-by current
depends on cycle time.
Deselected
L
X
- 6 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS 2 ADSP ADSC ADV WRITE CLK
ADDRESS ACCESSED
N/A
Operation
X
X
H
X
H
L
X
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Not Selected
X
X
L
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
GW
H
BW
H
L
WEa
X
WEb
X
WEc
X
WEd
OPERATION
READ
X
H
H
H
L
H
H
H
H
READ
H
L
L
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
H
L
H
H
L
H
L
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
GW
H
BW
H
L
WEa
X
WEb
OPERATION
X
H
H
L
READ
H
H
READ
H
L
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
H
L
L
L
L
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
- 7 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
VDD
UNIT
V
VDDQ
VIN
V
-0.3 to VDD+0.3
-0.3 to VDDQ+0.3
1.6
V
VIO
V
PD
W
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
Max
3.465
3.465
0
Unit
V
VDDQ
V
VSS
V
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
Max
3.465
2.9
Unit
V
VDDQ
V
VSS
0
V
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
SYMBOL
TEST CONDITION
VIN=0V
Min
Max
Unit
pF
Input Capacitance
CIN
-
-
5
7
Output Capacitance
COUT
VOUT=0V
pF
*Note : Sampled not 100% tested.
- 8 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = Max ; VIN=VSS to VDD
MIN
MAX
+2
UNIT NOTES
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
-2
-2
-
mA
mA
IOL
Output Disabled, VOUT=VSS to VDDQ
+2
-25
-22
-20
-16
-15
-14
-25
-22
-20
-16
-15
-14
460
440
410
360
330
310
170
160
150
140
140
140
-
-
Device Selected, IOUT=0mA,
ZZ£VIL , Cycle Time ³ tCYC Min
Operating Current
ICC
mA
1,2
-
-
-
-
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max,
-
ISB
mA
-
All Inputs£0.2V or ³ V DD-0.2V
-
Standby Current
-
Device deselected, IOUT=0mA, ZZ£0.2V,
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)
ISB1
ISB2
-
-
110
100
mA
mA
Device deselected, IOUT=0mA, ZZ³ VDD-
0.2V, f=Max, All Inputs£VILor ³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
nput High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.3*
2.0
-0.3*
1.7
0.8
VDD+0.3**
0.7
3
3
VIH
VIL
VIH
VDD+0.3**
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V.
VIH
VSS
VSS-1.0V
20% tCYC (MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
Parameter
Value
0 to 3.0V
0 to 2.5V
1.0V/ns
1.0V/ns
1.5V
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VDDQ/2
See Fig. 1
- 9 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50W
Dout
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
319W / 1667W
30pF*
Dout
Zo=50W
353W / 1538W
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
-25
-22
-20
-16
-15
-14
Parameter
Symbol
Unit
Min MAX Min Max MIN MAX Min Max Min Max Min Max
Cycle Time
tCYC
tCD
4.0
-
-
2.6
2.6
-
4.4
-
2.8
2.8
-
5.0
-
3.1
3.1
-
6.0
-
3.5
3.5
-
6.7
-
3.8
3.8
-
7.2
-
4.0
4.0
-
ns
ns
Clock Access Time
-
-
-
-
-
-
-
-
-
-
Output Enable to Data Valid
tOE
-
ns
Clock High to Output Low-Z
tLZC
tOH
0
0
0
0
0
0
ns
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
1.5
0
-
1.5
0
-
1.5
0
-
1.5
0
-
1.5
0
-
1.5
0
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
-
-
-
-
ns
-
2.6
-
2.8
-
3.0
-
3.0
-
3.0
-
3.5
ns
1.5 2.6 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.5
ns
1.7
1.7
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.8
1.8
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.1
2.1
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.3
2.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
Clock Low Pulse Width
tCL
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
ns
tSS
ns
tDS
ns
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tWS
ns
tADVS
tCSS
tAH
ns
ns
ns
tSH
ns
tDH
ns
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
ns
ns
ns
cycle
cycle
ZZ Low to Power Up
2
2
2
2
2
2
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
- 10 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
- 11 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
- 12 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
- 13 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
- 14 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
- 15 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 1Mx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.
I/O[0:71]
Data
Address
A[0:20]
A[20]
A[0:19]
A[20]
A[0:19]
Address Data
Address Data
CLK
CS2
CS2
CLK
ADSC
WEx
OE
CS2
CS2
CLK
ADSC
WEx
OE
1Mx36
SPB
SRAM
1Mx36
SPB
SRAM
Microprocessor
Address
CLK
(Bank 0)
(Bank 1)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
ADDRESS
[0:n*]
A1
A2
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1*
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes
:
n = 14 32K depth ,
15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
Don¢t Care
Undefined
- 16 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 2Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 2M depth to 4M depth without extra logic.
I/O[0:71]
Data
Address
A[21]
A[21]
A[0:21]
A[0:20]
A[0:20]
Address Data
CS
CS
Address Data
CS
CS
CLK
2
2
2
2
Microprocessor
CLK
ADSC
WEx
OE
2Mx18
SPB
SRAM
CLK
ADSC
WEx
OE
2Mx18
SPB
SRAM
Address
CLK
(Bank 0)
(Bank 1)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
ADDRESS
[0:n*]
A1
A2
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1*
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth ,
15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
20 2M depth
Don¢t Care
Undefined
- 17 -
Oct. 2003
Rev 1.1
K7A323601M
K7A321801M
1Mx36 & 2Mx18 Synchronous SRAM
PACKAGE DIMENSIONS
Units ; millimeters/Inches
100-TQFP-1420A
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
14.00 ±0.20
0.10 MAX
(0.83)
0.50 ±0.10
#1
0.65
0.30 ±0.10
0.10MAX
(0.58)
1.40 ±0.10
1.60MAX
0.05 MIN
0.50 ±0.10
- 18 -
Oct. 2003
Rev 1.1
相关型号：
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Cache SRAM, 1MX36, 3.1ns, CMOS, PQFP100, 20 X 14 MM, ROHS COMPLIANT, TQFP-100
SAMSUNG
K7A323630C-PC20T
Cache SRAM, 1MX36, 3.1ns, CMOS, PQFP100, 20 X 14 MM, ROHS COMPLIANT, TQFP-100
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