K7A403209B-QI200 [SAMSUNG]
Cache SRAM, 128KX32, 2.8ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100;
| 型号： | K7A403209B-QI200 |
| 厂家： | 
SAMSUNG |
| 描述： | Cache SRAM, 128KX32, 2.8ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
4Mb Sync. Pipelined Burst SRAM
Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 3.0 July 2006
- 1 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Document Title
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Remark
Rev. No
History
Draft Date
Preliminary
Preliminary
0.0
0.1
1. Initial draft
May. 15. 2001
June. 12. 2001
1. Changed DC parameters
Icc ; from 570mA to 490mA at -30,
from 520mA to 440mA at -27,
from 470mA to 400mA at -25,
from 440mA to 360mA at -22,
from 400mA to 330mA at -20,
from 370mA to 310mA at -18,
ISB ; from 200mA to 180mA at -30,
from 190mA to 170mA at -27,
from 180mA to 160mA at -25,
from 170mA to 155mA at -22,
from 160mA to 150mA at -20,
from 150mA to 140mA at -18,
ISB1 ; from 100mA to 80mA
2. Input set-up(tAS,tSS,tDS,tWS,tADVS,tCSS) from 0.6ns to 0.7ns at -30
Preliminary
Preliminary
0.2
0.3
1. Delete Pass-Through
June. 25. 2001
July. 31. 2001
1. Changed Input set-up(tAS,tSS,tDS,tWS,tADVS,tCSS)
- from 0.8ns to 1.0ns at -25
- from 075ns to 0.8ns at -27
- from 0.7ns to 0.8ns at -30
Preliminary
Final
0.4
1.0
1. Add x32 org and industrial range temperature
Aug. 11. 2001
Nov. 15. 2001
1. Final spec release
2. Changed Pin Capacitance
- Cin ; from 5pF to 4pF
- Cout ; from 7pF to 6pF
Final
Final
2.0
3.0
1. Remove tCYC 300/275/225MHz( -30/-27/-22)
1. Add Pb-free package
Nov. 17. 2003
Jul. 03. 2006
Rev. 3.0 July 2006
- 2 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
4Mb SPB SRAM Ordering Information
Org.
VDD (V)
Speed (MHz)
Access Time (ns)
Part Number
RoHS Avail.
K7A401809B-P(Q)1C(I)225
K7A401809B-Q3C(I)20
K7A403209B-P(Q)1C(I)225
K7A403209B-Q3C(I)20
K7A403609B-P(Q)1C(I)225
K7A403609B-Q3C(I)20
250
200
250
200
250
200
2.4
2.8
2.4
2.8
2.4
2.8
√
256Kx18
•
√
128Kx32
128Kx36
3.3
•
√
•
Note 1. P(Q) [Package type]: P-Pb Free, Q-Pb
2. C(I) [Operating Temperature]: C-Commercial, I-Industrial
3. Support only Pb package parts at this frequency. To use Pb-Free package, use faster frequency parts.
Rev. 3.0 July 2006
- 3 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
The K7A403609B, K7A403209B and K7A401809B are
4,718,592-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pen-
tium and Power PC based System.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
It is organized as 128K(256K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system′s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403609B, K7A403209B and K7A401809B are fab-
ricated using SAMSUNG′s high performance CMOS tech-
nology and is available in a 100pin TQFP package. Multiple
power and ground pins are utilized to minimize ground
bounce.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Cont-
nention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A .
• Operating in commercial and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Symbol
tCYC
tCD
-25
4.0
2.4
2.4
-20
5.0
2.8
2.8
Unit
ns
Cycle Time
Clock Access Time
ns
Output Enable Access Time
tOE
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
128Kx36/32 , 256Kx18
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
ADV
ADSC
A′
0~A 1
′
ARRAY
COUNTER
A0~A1
A2~A16
or A2~A17
ADDRESS
REGISTER
A0~A16
or A0~A17
ADSP
DATA-IN
REGISTER
CS1
CS2
CS2
OUTPUT
GW
BW
CONTROL
LOGIC
REGISTER
BUFFER
WEx
(x=a,b,c,d or a,b)
OE
ZZ
36/32 or 18
DQa0 ~ DQd7
DQPa ~ DQPd
or DQa0 ~ DQb7
DQPa ~ DQPb
Rev. 3.0 July 2006
- 4 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQPc/NC
1
DQb
DQb
7
6
DQc
0
1
2
DQc
3
V
DDQ
V
DDQ
4
VSSQ
VSSQ
5
DQb
DQb
DQb
DQb
5
4
3
2
DQc
DQc
DQc
DQc
2
3
4
5
6
7
8
9
V
SSQ
DDQ
V
SSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DQb
DQb
V
DDQ
100 Pin TQFP
1
0
DQc
6
7
DQc
V
SS
N.C.
N.C.
(20mm x 14mm)
V
DD
V
DD
ZZ
N.C.
V
SS
0
1
K7A403609B(128Kx36)
K7A403209B(128Kx32)
DQa
DQa
7
6
DQd
DQd
VDDQ
SSQ
VDDQ
V
VSSQ
DQd
DQd
DQd
DQd
2
3
4
5
DQa
DQa
DQa
DQa
5
4
3
2
V
SSQ
V
SSQ
DDQ
V
DDQ
DQd
DQd
V
6
7
DQa
DQa
1
0
DQPd/NC
DQPa/NC
PIN NAME
SYMBOL
A0 - A16
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
PIN NAME
Power Supply(+3.3V)
Ground
TQFP PIN NO.
15,41,65,91
17,40,67,90
32,33,34,35,36,37
44,45,46,47,48,49
50,81,82,99,100
83
VDD
VSS
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
Burst Address Advance
Address Status Processor 84
Address Status Controller 85
No Connect
14,16,38,39,42,43,66
N.C.
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
/NC
Clock
89
Chip Select
Chip Select
Chip Select
Byte Write Inputs
98
97
92
WEx
(x=a,b,c,d)
OE
93,94,95,96
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Output Enable
86
88
87
64
31
VDDQ
VSSQ
GW
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
BW
ZZ
LBO
Rev. 3.0 July 2006
- 5 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
1
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
2
N.C.
3
VDDQ
VSSQ
N.C.
4
5
6
N.C.
7
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
N.C.
VDD
VDD
(20mm x 14mm)
N.C.
VSS
ZZ
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7A401809B(256Kx18)
VSSQ
VDDQ
N.C.
N.C.
N.C.
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
32,33,34,35,36,37,
44,45,46,47,48,49,
50,80,81,82,99,100
83
VDD
Power Supply(+3.3V) 15,41,65,91
VSS
Ground
17,40,67,90
N.C.
No Connect
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,43,51,52,53,
56,57,66,75,78,79,95,96
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
Burst Address Advance
Address Status Processor 84
Address Status Controller
Clock
85
89
DQa0~a7
DQb0~b7
DQPa, Pb
VDDQ
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
Chip Select
98
Chip Select
97
Chip Select
92
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
WEx
(x=a,b)
OE
Byte Write Inputs
93,94
VSSQ
5,10,21,26,55,60,71,76
Output Enable
86
88
87
64
31
GW
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
BW
ZZ
LBO
Rev. 3.0 July 2006
- 6 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A4036/3209B and K7A401809B are synchronous SRAM designed to support the burst address accessing sequence of the
P6 and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The
start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
BQ TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
LBO PIN
LOW
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
Notes
OPERATION
ZZ
H
L
OE
X
I/O STATUS
High-Z
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
Sleep Mode
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
L
DQ
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
5. Deselected means power down state of which stand-by current
depends on cycle time.
Deselected
L
X
Rev. 3.0 July 2006
- 7 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS2 ADSP ADSC ADV WRITE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36/32)
GW
H
BW
H
L
WEa
X
WEb
X
WEc
X
WEd
X
OPERATION
READ
H
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
WRITE TRUTH TABLE(x18)
GW
H
H
BW
H
L
WEa
X
H
WEb
X
H
OPERATION
READ
READ
H
H
H
L
L
L
L
X
L
H
L
X
H
L
L
X
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
Rev. 3.0 July 2006
- 8 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
VDD
RATING
-0.3 to 4.6
VDD
UNIT
V
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
VDDQ
VIN
V
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
-0.3 to VDD+0.3
-0.3 to VDDQ+0.3
2.2
V
VIO
V
PD
W
Storage Temperature
TSTG
TOPR
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
°C
Commercial
Industrial
Operating Temperature
-40 to 85
-10 to 85
Storage Temperature Range Under Bias
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0°C≤ TA≤70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.6
3.6
0
UNIT
V
V
V
VDDQ
VSS
* The above parameters are also guaranteed at industrial temperature range.
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.6
2.9
0
UNIT
V
V
V
VDDQ
VSS
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
SYMBOL
CIN
TEST CONDITION
VIN=0V
TYP
-
-
MAX
4
6
UNIT
pF
Output Capacitance
COUT
VOUT=0V
pF
*Note : Sampled not 100% tested.
Rev. 3.0 July 2006
- 9 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
Input Leakage Current(except ZZ)
Output Leakage Current
SYMBOL
TEST CONDITIONS
VDD = Max ; VIN=VSS to VDD
MIN
MAX
+2
UNIT
µA
IIL
-2
-2
-
IOL
Output Disabled, VOUT=VSS to VDDQ
+2
µA
Device Selected, IOUT=0mA, ZZ≤VIL,
-25
-20
-25
-20
400
330
160
150
mA
Operating Current
ICC
ISB
All Inputs=VIL or VIH , Cycle Time ≥cyc Min
-
-
mA
Device deselected, IOUT=0mA,ZZ≤VIL,
f=Max, All Inputs≤0.2V or ≥ VDD-0.2V
-
Device deselected, IOUT=0mA, ZZ≤0.2V,
Standby Current
ISB1
ISB2
-
-
80
50
mA
mA
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL = 8.0mA
IOH = -4.0mA
IOL = 1.0mA
IOH = -1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.5*
2.0
-0.3*
1.7
0.8
VIH
VIL
VDD+0.5**
0.7
VIH
VDD+0.5**
The above parameters are also guaranteed at industrial temperature range.
*
VIL(Min)=-2.0(Pulse Width ≤ tCYC/2)
** VIH(Max)=4.6(Pulse Width ≤ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, T
A=0 to 70°C)
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
0 to 3V
0 to 2.5V
1ns
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
1ns
1.5V
VDDQ/2
See Fig. 1
* The above parameters are also guaranteed at industrial temperature range.
Rev. 3.0 July 2006
- 10 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Output Load(A)
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
Dout
/+2.5V for 2.5V I/O
RL=50Ω
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
319Ω / 1667Ω
30pF*
Dout
Z0=50Ω
353Ω / 1538Ω
5pF*
* Capacitive Load consists of all components of
the test environment.
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
-25
-20
PARAMETER
Symbol
Unit
Min
Max
Min
Max
Cycle Time
tCYC
tCD
4.0
-
-
2.4
2.4
-
5.0
-
-
2.8
2.8
-
ns
ns
ns
ns
ns
ns
ns
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
tOE
-
-
tLZC
tOH
0
0
0.8
0
-
1.0
0
-
Output Enable Low to Output Low-Z
tLZOE
-
-
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tHZOE
tHZC
tCH
-
2.4
-
2.8
0.8
1.7
1.7
1.0
1.0
2.4
1.0
2.0
2.0
1.2
1.2
2.8
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
Clock Low Pulse Width
tCL
Address Setup to Clock High
tAS
Address Status Setup to Clock High
Data Setup to Clock High
tSS
1.0
1.0
1.0
1.0
1.2
1.2
1.2
1.2
tDS
tWS
-
-
-
-
-
-
ns
ns
ns
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
tADVS
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
tCSS
tAH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
0.3
0.3
0.3
0.3
0.3
0.3
2
0.4
0.4
0.4
0.4
0.4
0.4
2
tSH
ns
Data Hold from Clock High
tDH
ns
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
tWH
ns
tADVH
tCSH
tPDS
tPUS
ns
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
ns
cycle
cycle
2
2
Notes : 1 The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP
is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times
whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
Rev. 3.0 July 2006
- 11 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 3.0 July 2006
- 12 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 3.0 July 2006
- 13 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 3.0 July 2006
- 14 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 3.0 July 2006
- 15 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 3.0 July 2006
- 16 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
I/O[0:71]
Data
Address
A[0:17]
A[17]
A[0:16]
A[17]
A[0:16]
Address Data
Address Data
CLK
CS2
CS2
CS2
CS2
64-Bits
Microprocessor
CLK
ADSC
WEx
OE
128Kx36
SPB
CLK
ADSC
WEx
OE
128Kx36
SPB
Address
SRAM
SRAM
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS1
ADV
ADSP
ADV
ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A2
A1
ADDRESS
[0:n]
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tHZC
tLZOE
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth
15 64K depth
Don′t Care
Undefined
16 128K depth
17 256K depth
Rev. 3.0 July 2006
- 17 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx18 Synchronous Pipelinde Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
I/O[0:71]
[18]
Data
Address
A[18]
A[0:17]
A
A[0:17]
A[0:18]
Address Data
Address Data
CLK
CS2
CS2
CS2
CS2
Microprocessor
CLK
ADSC
WEx
OE
256Kx18
SPB
CLK
ADSC
WEx
OE
256Kx18
SPB
Address
CLK
SRAM
SRAM
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A2
A1
ADDRESS
[0:n]
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tHZC
tLZOE
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
Don′t Care
Undefined
Rev. 3.0 July 2006
- 18 -
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
PACKAGE DIMENSIONS
Units ; millimeters/Inches
100-TQFP-1420A
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
14.00 ±0.20
0.10 MAX
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
Rev. 3.0 July 2006
- 19 -
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