K7A801800B-HI16 [SAMSUNG]
Cache SRAM, 512KX18, 3.5ns, CMOS, PBGA119, BGA-119;型号: | K7A801800B-HI16 |
厂家: | SAMSUNG |
描述: | Cache SRAM, 512KX18, 3.5ns, CMOS, PBGA119, BGA-119 静态存储器 内存集成电路 |
文件: | 总24页 (文件大小:611K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
Document Title
256Kx36 & 256Kx32 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
0.1
0.2
0.3
1.0
Initial draft
May. 18 . 2001 Preliminary
June. 26. 2001 Preliminary
1. Delete pass- through
1. Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
Aug. 11. 2001
Aug. 28. 2001
Nov. 16. 2001
Preliminary
Preliminary
Final
1. Final spec release
2. Change ISB2 form 50mA to 60mA
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
8Mb SB/SPB Synchronous SRAM Ordering Information
Speed
Org.
Part Number
Mode
VDD
FT ; Access Time(ns)
PKG
Temp
Pipelined ; Cycle Time(MHz)
K7B801825B-Q(H)C(I)65/75/85
K7A801800B-Q(H)C(I)16/14
K7A801809B-Q(H)C(I)25/22/20
K7A801801B-QC(I)16/14
SB
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
6.5/7.5/8.5 ns
167/138 MHz
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
SPB(2E2D)
SB
512Kx18
250/225/200 MHz
167/138 MHz
K7A801808B-QC(I)25/22/20
K7B803225B-QC(I)65/75/85
K7A803200B-QC(I)16/14
250/225/200 MHz
6.5/7.5/8.5 ns
C:
Q:
Commercial
Temperature
Range
100TQFP
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
SPB(2E2D)
SB
167/138 MHz
256Kx32
256Kx36
K7A803209B-QC(I)25/22/20
K7A803201B-QC(I)16/14
250/225/200 MHz
167/138 MHz
H:
119BGA
I:
Industrial
Temperature
Range
K7A803208B-QC(I)25/22/20
K7B803625B-Q(H)C(I)65/75/85
K7A803600B-Q(H)C(I)16/14
K7A803609B-Q(H)C(I)25/22/20
K7A803601B-QC(I)16/14
250/225/200 MHz
6.5/7.5/8.5 ns
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
SPB(2E2D)
167/138 MHz
250/225/200 MHz
167/138 MHz
K7A803608B-QC(I)25/22/20
250/225/200 MHz
- 2 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
256Kx36 & 256Kx32 & 512Kx18-bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
The K7A803600B, K7A803200B and K7A801800B are
9,437,184-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pen-
tium and Power PC based System.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
It is organized as 256K(512K) words of 36/32(18) bits and
integrates address and control registers, a 2-bit burst
address counter and added some new functions for high
performance cache RAM applications; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system¢s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)
• Operating in commeical and industrial temperature range.
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
FAST ACCESS TIMES
The K7A803600B, K7A803200B and K7A801800B are fab-
ricated using SAMSUNG¢s high performance CMOS tech-
nology and is available in a 100pin TQFP and 119BGA
package (100pin TQFP only for K7A803200B).
PARAMETER
Cycle Time
Symbol
tCYC
tCD
-16 -14 Unit
6.0
3.5
3.5
7.2
3.8
3.8
ns
ns
ns
Clock Access Time
Output Enable Access Time
tOE
Multiple power and ground pins are utilized to minimize
ground bounce.
LOGIC BLOCK DIAGRAM
CLK
LBO
256Kx36/32 , 512Kx18
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
COUNTER
ADV
ADSC
A¢0~A¢1
ARRAY
A0~A1
A2~A17
or A2~A18
A
0
~A17
ADDRESS
REGISTER
or A
0~A18
ADSP
DATA-IN
REGISTER
CS
CS
CS
1
2
2
OUTPUT
REGISTER
GW
BW
CONTROL
LOGIC
BUFFER
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb7
DQPa,DQPb
DQPa ~ DQPd
- 3 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
DQPb/NC
80
DQPc/NC
1
DQb7
DQc0
79
2
DQb6
78
DQc1
3
VDDQ
VDDQ
VSSQ
5
DQc2
DQc3
7
DQc4
DQc5
9
VSSQ
VDDQ
11
DQc6
DQc7
13
N.C.
VDD
15
N.C.
VSS
17
DQd0
77
4
VSSQ
76
DQb5
75
6
DQb4
74
DQb3
73
8
DQb2
72
VSSQ
VDDQ
70
DQb1
DQb0
VSS
67
71
10
69
68
12
100 Pin TQFP
14
(20mm x 14mm)
N.C.
VDD
ZZ
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
16
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
18
K7A803600B(256Kx36)
K7A803200B(256Kx32)
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
19
20
21
22
23
24
25
26
27
28
29
30
DQd6
DQd7
DQPd/NC
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
32,33,34,35,36,37,43 VDD
44,45,46,47,48,49,50 VSS
Power Supply(+3.3V)
Ground
15,41,65,91
17,40,67,90
81,82,99,100
83
Address Status Processor 84
Address Status Controller 85
N.C.
No Connect
14,16,38,39,42,66
ADV
ADSP
ADSC
CLK
CS1
CS2
Burst Address Advance
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
/NC
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Clock
89
98
97
92
Chip Select
Chip Select
Chip Select
CS2
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
VDDQ
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
OE
Output Enable
86
88
87
64
31
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
VSSQ
LBO
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
3. DQPa~DQPd are NC for K7A803200B
- 4 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
A10
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7A801800B(512Kx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A18
Address Inputs
32,33,34,35,36,37,43 VDD
44,45,46,47,48,49,50 VSS
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
80,81,82,99,100
83
Address Status Processor 84
N.C.
No Connect
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,51,52,53,56,
57,66,75,78,79,95,96
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
Burst Address Advance
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
85
89
98
97
92
93,94
86
DQa0 ~ a7
DQb0 ~ b7
DQPa, Pb
VDDQ
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
Output Ground
Byte Write Inputs
Output Enable
VSSQ
5,10,21,26,55,60,71,76
GW
BW
ZZ
LBO
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
88
87
64
31
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
- 5 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7A803600B(256Kx36)
1
2
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
A
VDDQ
NC
CS2
A
A
A
A
NC
A
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
VSS
VSS
VSS
WEc
VSS
NC
VSS
WEd
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
WEb
VSS
NC
VSS
WEa
VSS
VSS
VSS
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
CS1
OE
G
H
J
ADV
GW
VDD
CLK
NC
K
L
M
N
P
R
T
BW
A1*
A0*
VDD
A
NC
NC
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
Power Supply(+3.3V)
A
A0,A1
Address Inputs
VDD
VSS
Burst Count Address
Ground
ADV
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
N.C.
No Connect
ADSP
ADSC
CLK
CS1
CS2
DQa
DQb
DQc
DQd
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
WEx
Byte Write Inputs
DQPa~Pd
(x=a,b,c,d)
VDDQ
Output Power Supply
(2.5V or 3.3V)
OE
Output Enable
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
TCK
TMS
TDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
TDO
- 6 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7A801800B(512Kx18)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
VDDQ
NC
CS2
A
A
A
A
NC
A
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
VSS
VSS
VSS
WEb
VSS
NC
VSS
VSS
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
WEa
VSS
VSS
VSS
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
CS1
OE
DQa
VDDQ
DQa
NC
VDDQ
NC
G
H
J
ADV
GW
VDD
CLK
NC
DQb
VDDQ
NC
VDDQ
DQa
NC
K
L
DQb
VDDQ
DQb
NC
M
N
P
R
T
BW
VDDQ
NC
A1*
A0*
DQa
NC
NC
VDD
NC
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
Power Supply(+3.3V)
A
A0,A1
Address Inputs
VDD
VSS
Burst Count Address
Ground
ADV
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
N.C.
No Connect
ADSP
ADSC
CLK
DQa
DQb
DQPa~Pb
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
CS1
Chip Select
CS2
Chip Select
WEx
(x=a,b)
Byte Write Inputs
VDDQ
Output Power Supply
(2.5V or 3.3V)
OE
Output Enable
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
TCK
TMS
TDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
TDO
- 7 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A803600B, K7A803200B and K7A801800B are synchronous SRAM designed to support the burst address accessing
sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock
edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
A0
LBO PIN
LOW
A1
A0
A1
A0
A1
A0
A1
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
ASYNCHRONOUS TRUTH TABLE
OPERATION
ZZ
H
L
OE
X
I/O STATUS
High-Z
Notes
1. X means "Don¢t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
Sleep Mode
L
DQ
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
5. Deselected means power down state of which stand-by current
depends on cycle time.
Deselected
L
X
- 8 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS2 ADSP ADSC ADV WRITE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
NOTE : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36/32)
GW
H
BW
H
L
WEa
X
WEb
X
WEc
X
WEd
X
OPERATION
READ
H
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
GW
H
BW
H
L
WEa
X
WEb
X
OPERATION
READ
H
H
H
READ
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
L
L
L
L
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
- 9 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
VDD
UNIT
V
VDDQ
VIN
V
-0.3 to VDD+0.3
-0.3 to VDDQ+0.3
1.6
V
VIO
V
PD
W
Storage Temperature
TSTG
TOPR
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
°C
Commercial
Industrial
Operating Temperature
-40 to 85
-10 to 85
Storage Temperature Range Under Bias
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.465
3.465
0
UNIT
VDD
V
V
V
VDDQ
VSS
* The above parameters are also guaranteed at industrial temperature range.
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.465
2.9
UNIT
V
V
V
VDDQ
VSS
0
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
SYMBOL
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
pF
CIN
-
-
5
7
Output Capacitance
COUT
VOUT=0V
pF
*Note : Sampled not 100% tested.
- 10 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0
°C to +70
°C)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = Max ; VIN=VSS to VDD
MIN
MAX
UNIT NOTES
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
-2
-2
-
+2
+2
mA
mA
IOL
Output Disabled, VOUT=VSS to VDDQ
-16
-14
-16
-14
350
300
130
120
Device Selected, IOUT=0mA,
ZZ£VIL , Cycle Time ³ tCYC Min
Operating Current
Standby Current
ICC
ISB
mA
mA
1,2
-
-
Device deselected, IOUT=0mA, ZZ£VIL,
f=Max, All Inputs£0.2V or ³ VDD-0.2V
-
Device deselected, IOUT=0mA, ZZ£0.2V,
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)
ISB1
ISB2
-
-
100
60
mA
mA
Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,
f=Max, All Inputs£VIL or ³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
-
V
V
V
V
V
V
V
V
2.4
-
0.4
-
2.0
-0.3*
2.0
-0.3*
1.7
0.8
VDD+0.3**
0.7
3
3
VIH
VIL
VIH
VDD+0.3**
Notes : 1.The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V.
VIH
VSS
VSS-1.0V
20% tCYC(MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
Parameter
Value
0 to 3.0V
0 to 2.5V
1.0V/ns
1.0V/ns
1.5V
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VDDQ/2
See Fig. 1
* The above parameters are also guaranteed at industrial temperature range.
- 11 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50W
30pF*
Dout
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
319W / 1667W
Dout
Zo=50W
353W / 1538W
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
-16
-14
PARAMETER
Symbol
UNIT
MIN
6.0
-
MAX
MIN
7.2
-
MAX
Cycle Time
tCYC
tCD
-
-
ns
ns
Clock Access Time
3.5
3.8
Output Enable to Data Valid
tOE
-
3.5
-
3.8
ns
Clock High to Output Low-Z
tLZC
tOH
0
-
0
-
ns
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
1.5
0
-
1.5
0
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
ns
ns
-
3.0
-
3.5
1.5
2.3
2.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.0
-
1.5
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.5
-
ns
Clock High Pulse Width
ns
Clock Low Pulse Width
tCL
-
-
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
-
-
ns
tSS
-
-
ns
tDS
-
-
ns
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tWS
-
-
ns
tADVS
tCSS
tAH
-
-
ns
-
-
ns
-
-
ns
tSH
-
-
ns
tDH
-
-
ns
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
-
-
ns
-
-
ns
-
-
ns
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
- 12 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
TDO Output
Notes
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
IDCODE
SAMPLE-Z
BYPASS
SAMPLE
Boundary Scan Register
Identification Register
Boundary Scan Register
Bypass Register
1
3
2
4
5
6
4
4
0
0
0
1
Boundary Scan Register
1
RESERVED Do Not Use
SRAM
CORE
1
1
BYPASS
BYPASS
Bypass Register
Bypass Register
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
TDI
BYPASS Reg.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
TDO
Identification Reg.
Instruction Reg.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
Control Signals
TAP Controller
TMS
TCK
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
TAP Controller State Diagram
1
0
Test Logic Reset
0
1
1
1
0
Run Test Idle
Select DR
0
Select IR
0
1
1
1
1
Capture DR
0
Capture IR
0
0
Shift DR
1
Shift IR
1
Exit1 DR
0
Exit1 IR
0
0
0
0
0
Pause DR
1
Pause IR
1
Exit2 DR
1
Exit2 IR
1
1
0
Update DR
0
Update IR
1
- 13 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
1 bits
ID Register
32 bits
Boundary Scan
70 bits
256Kx36
512Kx18
3 bits
3 bits
1 bits
32 bits
70 bits
ID REGISTER DEFINITION
Revision Number Part Configuration Vendor Definition Samsung JEDEC Code
Part
Start Bit(0)
(31:28)
(27:18)
(17:12)
XXXXXX
XXXXXX
(11: 1)
256Kx36
512Kx18
0000
00110 00100
00111 00011
00001001110
00001001110
1
1
0000
119BGA BOUNDARY SCAN EXIT ORDER(x36)
119BGA BOUNDARY SCAN EXIT ORDER(x18)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
4B
4E
4H
3G
3C
3B
3A
2B
2C
2A
2D
1E
2F
1G
2H
1D
2E
2G
1H
2K
1L
ADSC
CS1
GW
WEc
A
OE
ADV
CLK
BW
ADSP
WEb
A
4F
4G
4K
4M
4A
5G
5C
5B
5A
6B
6A
6C
6D
6E
6G
7H
7D
7E
6F
7G
6H
7K
6L
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
4B
4E
4H
3G
3C
3B
3A
2B
2C
2A
2D
1E
2F
1G
2H
1D
2E
2G
1H
2K
1L
ADSC
CS1
GW
WEb
A
OE
ADV
CLK
BW
ADSP
NC
A
4F
4G
4K
4M
4A
5G
5C
5B
5A
6B
6A
6C
7D
6E
6G
7H
6D
7E
6F
7G
6H
7K
6L
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
A
A
A
A
CS2
A
A
CS2
A
A
A
A
A
A
A
A
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
LBO
WEd
A
A
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
NC
LBO
NC
A
A
A
A
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQPa
ZZ
NC
NC
NC
NC
DQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
ZZ
2M
1N
1P
1K
2L
2M
1N
2P
1K
2L
6N
7P
6K
7L
6N
7P
6K
7L
2N
2P
3R
3L
2N
1P
3R
3L
6M
7N
6P
7T
6R
5L
8
6M
7N
6P
7T
6R
5L
8
7
7
6
6
2R
3T
4N
4P
2T
5
2R
3T
4N
4P
2T
5
A
A
4
A
A
4
A1
WEa
A
3
A1
WEa
A
3
A0
5T
4T
2
A0
5T
6T
2
NC
A
1
A
A
1
NOTE : NC ; Dont’ care.
- 14 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Symbol
Min
3.135
2.0 / 1.7
-0.3
Typ
Max
3.465
Unit
V
Note
VDD
VIH
3.3
Input High Level ( 3.3V I/O / 2.5V I/O )
Input Low Level ( 3.3V I/O / 2.5V I/O )
Output High Voltage ( 3.3V I/O / 2.5V I/O )
Output Low Voltage ( 3.3V I/O / 2.5V I/O )
-
-
-
-
VDD+0.3
0.8 / 0.7
-
V
1
VIL
V
VOH
VOL
2.4 / 2.0
-
V
0.4 / 0.4
V
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.
1. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
JTAG AC TEST CONDITIONS
Parameter
Symbol
VIH/VIL
TR/TF
Min
Unit
V
Note
Input High/Low Level ( 3.3V I/O / 2.5V I/O )
Input Rise/Fall Time ( 3.3V I/O / 2.5V I/O )
Input and Output Timing Reference Level
3.0 / 0 , 2.5 / 0
1.0 / 1.0 , 1.0 /1 .0
VDDQ/2
ns
V
JTAG AC Characteristics
Parameter
TCK Cycle Time
Symbol
Min
50
20
20
5
Max
Unit
Note
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
5
5
5
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
5
5
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tCHDX
TMS
TDI
tDVCH
tSVCH
tCHSX
PI
(SRAM)
tCLQV
TDO
- 15 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 16 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 17 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 18 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 19 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 20 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
I/O[0:71]
Data
Address
A
[0:18]
A
[18]
A
[0:17]
A[18]
A[0:17]
Address Data
Address Data
CS
CS
CLK
CS
CS
2
2
2
2
CLK
ADSC
WEx
OE
256Kx36
SPB
SRAM
CLK
ADSC
WEx
OE
256Kx36
SPB
SRAM
Microprocessor
Address
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS
1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tHZC
tLZOE
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth ,
15 64K depth
Don¢t Care
Undefined
16 128K depth , 17 256K depth
18 512K depth
- 21 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 512Kx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
I/O[0:71]
Data
Address
A
[0:18]
A
[19]
A[0:19]
A[0:18]
A[19]
Address Data
Address Data
CS
CS
CLK
CS
CS
2
2
2
2
Microprocessor
512Kx18
SPB
SRAM
CLK
ADSC
WEx
OE
512Kx18
SPB
SRAM
CLK
ADSC
WEx
OE
Address
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS
1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth ,
15 64K depth
Undefined
Don¢t Care
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
- 22 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
PACKAGE DIMENSIONS
Units ; millimeters/Inches
100-TQFP-1420A
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
14.00 ±0.20
0.10 MAX
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
- 23 -
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
119BGA PACKAGE DIMENSIONS
1.27
1.27
14.00±0.10
22.00±0.10
Indicator of
Ball(1A) Location
20.50±0.10
C0.70
C1.00
0.750±0.15
1.50REF
0.60±0.10
0.60±0.10
Notes
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 Max.
3. PCB to Cavity Offset : 0.10 Max.
12.50±0.10
- 24 -
Nov 2001
Rev 1.0
相关型号:
K7A801800B-PC160
Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 20 X 14 MM, ROHS COMPLIANT, TQFP-100
SAMSUNG
K7A801800B-PI160
Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 20 X 14 MM, ROHS COMPLIANT, TQFP-100
SAMSUNG
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