K7B161825A [SAMSUNG]
512Kx36 & 1Mx18 Synchronous SRAM; 512Kx36及1Mx18同步SRAM
| 型号： | K7B161825A |
| 厂家： | 
SAMSUNG |
| 描述： | 512Kx36 & 1Mx18 Synchronous SRAM |
| 文件： | 总19页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
Document Title
512Kx36 & 1Mx18-Bit Synchronous Burst SRAM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
1. Initial draft
Feb. 23. 2001
Preliminary
0.1
0.2
1. Add JTAG Scan Order
May. 10. 2001
Aug. 30. 2001
Preliminary
Preliminary
1. Add x32 org and industrial temperature .
2. Add 165FBGA package
1.0
1.1
1. Final spec release
May. 10. 2002
April 04. 2003
Final
Final
1. Delete 119BGA package.
2. Correct the Ball Size of 165 FBGA.
2.0
1. Delete x32 Org.
Nov. 17, 2003
Final
2. Delete 165FBGA package.
3. Delelte the 6.5 ns speed bin.
Nov. 2003
Rev 2.0
- 1 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
16Mb SB/SPB Synchronous SRAM Ordering Information
Speed
Org.
Part Number
Mode
VDD
SB ; Access Time(ns)
SPB ; Cycle Time(MHz)
PKG
Temp
K7B161825A-QC(I)75/85
K7A161800A-QC(I)25/16/14
K7A161801A-QC(I)20/16
K7B163625A-QC(I)75/85
K7A163600A-QC(I)25/16/14
K7A163601A-QC(I)20/16
SB
3.3
3.3
3.3
3.3
3.3
3.3
7.5/8.5ns
250/167/138MHz
200/167MHz
7.5/8.5ns
C
; Commercial
Temp.Range
1Mx18
SPB(2E1D)
SPB(2E2D)
SB
Q : 100TQFP
I
; Industrial
Temp.Range
512Kx36
SPB(2E1D)
SPB(2E2D)
250/167/138MHz
200/167MHz
Nov. 2003
Rev 2.0
- 2 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
The K7B163625A and K7B161825A are 18,874,368-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
It is organized as 512K(1M) words of 36(32/18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system¢s burst sequence and are controlled by the burst
address advance(ADV) input.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
FAST ACCESS TIMES
The K7B163625A and K7B161825A are fabricated using SAM-
SUNG¢s high performance CMOS technology and is available
in a 100pin TQFP package. Multiple power and ground pins are
utilized to minimize ground bounce.
PARAMETER
Cycle Time
Symbol -75
-85
10
Unit
ns
tCYC
tCD
8.5
7.5
3.5
Clock Access Time
8.5
4.0
ns
Output Enable Access Time
tOE
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
512Kx36, 1Mx18
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
COUNTER
ADV
ADSC
A¢0~A¢1
ARRAY
A0~A1
A2~A18
or A2~A19
A
0
~A18
ADDRESS
REGISTER
or A0~A19
ADSP
DATA-IN
REGISTER
CS
CS
CS
1
2
2
GW
BW
OUTPUT
BUFFER
CONTROL
LOGIC
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
DQPa ~ DQPd
or DQa0 ~ DQb7
DQPa,DQPb
Nov. 2003
Rev 2.0
- 3 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
NC/DQPc
1
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc0
2
DQc1
3
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQb1
DQb0
VSS
100 Pin TQFP
VDD
N.C.
VSS
N.C.
(20mm x 14mm)
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
NC/DQPd
K7B163625A(512Kx36)
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A18
Address Inputs
32,33,34,35,36,37,42 VDD
43,44,45,46,47,48,49 VSS
50,81,82,99,100
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
ADV
ADSP
ADSC
CLK
CS1
CS2
Burst Address Advance
Address Status Processor 84
Address Status Controller 85
83
No Connect
14,16,38,39,66
N.C.
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
or NC
Clock
89
98
97
Chip Select
Chip Select
Chip Select
CS2
92
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
GW
BW
ZZ
Output Enable
86
88
87
64
31
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
VDDQ
VSSQ
Output Ground
5,10,21,26,55,60,71,76
LBO
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
Nov. 2003
Rev 2.0
- 4 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
A10
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
1
2
3
4
5
6
7
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
VDD
ZZ
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7B161825A(1Mx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A19
Address Inputs
32,33,34,35,36,37,42 VDD
43,44,45,46,47,48,49 VSS
Power Supply(+3.3V)
Ground
15,41,65,91
17,40,67,90
50 80,81,82,99,100
83
Address Status Processor 84
N.C.
No Connect
1,2,3,6,7,14,16,25,28,29,
30,38,39,51,52,53,56,57,
66,75,78,79,95,96
ADV
ADSP
ADSC
CLK
CS1
Burst Address Advance
Address Status Controller
Clock
Chip Select
85
89
98
DQa0 ~ a7
DQb0 ~ b7
DQPa, Pb
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
CS2
Chip Select
97
CS2
Chip Select
92
WEx(x=a,b) Byte Write Inputs
93,94
86
88
VDDQ
VSSQ
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
OE
Output Enable
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
87
64
31
LBO
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
Nov. 2003
Rev 2.0
- 5 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7B163625A and K7B161825A are synchronous SRAM designed to support the burst address accessing sequence of the
Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and
duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are
sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the
output pins.
Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation.
All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high
and BW is low. In K7B163625M, a 512Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and
DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd.
CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BQ TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
A0
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
Nov. 2003
Rev 2.0
- 6 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS 2 ADSP ADSC ADV WRITE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
H
L
X
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
X
X
L
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36)
GW
H
BW
H
L
WEa
X
WEb
X
WEc
X
WEd
OPERATION
READ
X
H
H
H
L
H
H
H
H
READ
H
L
L
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
H
L
H
H
L
H
L
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
GW
H
BW
H
L
WEa
X
WEb
OPERATION
X
H
H
L
READ
H
H
READ
H
L
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
H
L
L
L
L
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
Nov. 2003
Rev 2.0
- 7 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
H
L
OE
X
I/O STATUS
Notes
Sleep Mode
High-Z
DQ
1. X means "Don¢t Care".
2. ZZ pin is pulled down internally
L
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
Deselected
L
X
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
VDD
UNIT
V
VDDQ
VIN
V
-0.3 to VDD+0.3
-0.3 to VDDQ+0.3
1.6
V
VIO
V
PD
W
Storage Temperature
TSTG
TOPR
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
°C
Commercial
Industrial
Operating Temperature
-40 to 85
-10 to 85
Storage Temperature Range Under Bias
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.465
3.465
0
UNIT
VDD
V
V
V
VDDQ
VSS
* The above parameters are also guaranteed at industrial temperature range.
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.465
2.9
UNIT
VDD
V
V
V
VDDQ
VSS
0
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
SYMBOL
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
Input Capacitance
CIN
-
-
5
7
pF
pF
Output Capacitance
COUT
VOUT=0V
*Note : Sampled not 100% tested.
Nov. 2003
Rev 2.0
- 8 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
mA
Notes
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
VDD=Max ; VIN=VSS to V DD
-2
-2
-
+2
IOL
Output Disabled, Vout=VSS to VDDQ
+2
mA
Device Selected, IOUT=0mA,
-75
-85
-75
250
230
90
Operating Current
ICC
mA
1,2
ZZ£VIL , Cycle Time ³ tCYC Min
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max, All Inputs£0.2V or
³ VDD-0.2V
-
ISB
mA
-85
-
80
Device deselected, IOUT=0mA,
ZZ£0.2V, f=0,
Standby Current
ISB1
ISB2
-
70
mA
mA
All Inputs=fixed (VDD-0.2V or
Device deselected, IOUT=0mA,
ZZ³ VDD-0.2V, f=Max, All
Inputs£VILor ³ VIH
-
60
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
2.0
-0.3*
2.0
-0.3*
1.7
-
0.8
VIH
VIL
VDD+0.3**
0.7
3
3
VIH
VDD+0.3**
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. VIH=VDDQ +0.3V
VIH
VSS
VSS-1.0V
20% tCYC (MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ =3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
PARAMETER
VALUE
0 to 3.0V
0 to 2.5V
1.0V/ns
1.0V/ns
1.5V
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VDDQ/2
See Fig. 1
* The above parameters are also guaranteed at industrial temperature range.
Nov. 2003
Rev 2.0
- 9 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50W
Dout
VL=1.5V for 3.3V I/O
319W / 1667W
VDDQ/2 for 2.5V I/O
30pF*
Dout
Zo=50W
353W / 1538W
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
-75
-85
PARAMETER
SYMBOL
UNIT
MIN
8.5
-
MAX
MIN
10
-
MAX
Cycle Time
tCYC
tCD
-
-
ns
ns
Clock Access Time
7.5
8.5
Output Enable to Data Valid
tOE
-
3.5
-
4.0
ns
Clock High to Output Low-Z
tLZC
tOH
2.5
2.5
0
-
2.5
2.5
0
-
ns
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
-
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
ns
-
3.5
-
4.0
ns
-
4.0
-
5.0
ns
Clock High Pulse Width
2.5
2.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
3.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
Clock Low Pulse Width
tCL
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
ns
tSS
ns
tDS
ns
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tWS
ns
tADVS
tCSS
tAH
ns
ns
ns
tSH
ns
tDH
ns
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
ns
ns
ns
cycle
cycle
ZZ Low to Power Up
2
2
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSPis sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
Nov. 2003
- 10 -
Rev 2.0
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
Nov. 2003
- 11 -
Rev 2.0
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
Nov. 2003
- 12 -
Rev 2.0
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
Nov. 2003
- 13 -
Rev 2.0
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
Nov. 2003
- 14 -
Rev 2.0
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
Nov. 2003
- 15 -
Rev 2.0
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
Nov. 2003
- 16 -
Rev 2.0
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 512Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
I/O[0:71]
Data
Address
A[0:19]
A[19]
A[0:18]
A[19]
A[0:18]
Address Data
CS2
Address Data
CS2
CLK
CS2
CS2
CLK
ADSC
WEx
OE
512Kx36
SB
SRAM
CLK
ADSC
WEx
OE
512Kx36
SB
SRAM
Microprocessor
Address
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
CLOCK
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected byCS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth ,
15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
Don¢t Care
Undefined
Nov. 2003
Rev 2.0
- 17 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 1Mx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.
I/O[0:71]
A[20]
Data
Address
A[20]
A[0:20]
A[0:19]
A[0:19]
Address Data
Address Data
CS2
CLK
CS2
CS2
CLK
ADSC
WEx
OE
CS2
CLK
ADSC
WEx
OE
Microprocessor
1Mx18
SB
SRAM
1Mx18
SB
SRAM
Address
CLK
(Bank 0)
(Bank 1)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
CLOCK
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected byCS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*Notes : n = 14 32K depth ,
15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
20 2M depth
Don¢t Care
Undefined
Nov. 2003
Rev 2.0
- 18 -
K7B163625A
K7B161825A
512Kx36 & 1Mx18 Synchronous SRAM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units ; millimeters/Inches
22.00 ±0.30
20.00 ±0.20
0~8°
0.127 + 0.10
- 0.05
16.00 ± 0.30
0.10 MAX
14.00± 0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ± 0.10
1.60 MAX
0.05 MIN
0.50 ± 0.10
Nov. 2003
Rev 2.0
- 19 -
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