K7B201825B-QI65 [SAMSUNG]
Cache SRAM, 128KX18, 6.5ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100;
| 型号： | K7B201825B-QI65 |
| 厂家： | 
SAMSUNG |
| 描述： | Cache SRAM, 128KX18, 6.5ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
Document Title
64Kx36/x32 & 128Kx18-Bit Synchronous Burst SRAM
Revision History
Remark
Rev. No.
History
Draft Date
Preliminary
0.0
1. Initial draft
Jan. 17. 2002
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
2Mb SB/SPB Synchronous SRAM Ordering Information
Speed
Org.
Part Number
Mode
VDD
FT ; Access Time(ns)
PKG
Temp
Pipelined ; Cycle Time(MHz)
K7B201825B-QC(I)65/75/80
SB
SPB(2E1D)
SB
3.3
3.3
3.3
3.3
3.3
3.3
6.5/7.5/8.0 ns
250/225/200/167/138 MHz
6.5/7.5/8.0 ns
128Kx18
64Kx32
64Kx36
C
K7A201800B-QC(I)25/22/20/16/14
K7B203225B-QC(I)65/75/80
(Commercial
Temperature
Range)
Q
(100TQFP)
K7A203200B-QC(I)25/22/20/16/14
K7B203625B-QC(I)65/75/80
SPB(2E1D)
SB
250/225/200/167/138 MHz
6.5/7.5/8.0 ns
I:
(Industrial
Temperature
K7A203600B-QC(I)25/22/20/16/14
SPB(2E1D)
250/225/200/167/138 MHz
- 2 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
64Kx36/x32 & 128Kx18-Bit Synchronous Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
The K7B203625B, K7B203225B and K7B201825B are
2,359,296 bits Synchronous Static Random Access Memory
designed to support zero wait state performance for advanced
Pentium/Power PC based system. And with CS1 high, ADSP is
blocked to control signals.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.
It can be organized as 64K(128K) words of 36(32/18) bits. And
it integrates address and control registers, a 2-bit burst address
counter and high output drive circuitry onto a single integrated
circuit for reduced components counts implementation of high
performance cache RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system¢s burst sequence and are controlled by the burst
address advance(ADV) input.
FAST ACCESS TIMES
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B203625B, K7B203225B and K7B201825B are imple-
mented with SAMSUNG¢s high performance CMOS technology
and is available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
PARAMETER
Cycle Time
Symbol -65 -75 -80 Unit
tCYC
tCD
7.5 8.5 10 ns
6.5 7.5 8.0 ns
3.5 3.5 4.0 ns
Clock Access Time
Output Enable Access Time
tOE
LOGIC BLOCK DIAGRAM
CLK
LBO
64Kx36/32 , 128Kx18
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
MEMORY
ARRAY
ADV
ADSC
A¢0~A¢1
A0~A1
A2~A15
or A2~A16
ADDRESS
REGISTER
A0~A15
or A0~A16
ADSP
DATA-IN
REGISTER
CS1
CS2
CS2
GW
BW
OUTPUT
BUFFER
CONTROL
LOGIC
WEx
(x=a,b,c,d or a,b)
OE
ZZ
36/32 or 18
DQa0 ~ DQd7
DQPa ~ DQPd
or DQa0 ~ DQb7
DQPa ~ DQPb
- 3 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
DQPc/NC
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
VDD
ZZ
VDD
N.C.
VSS
K7B203625B(64Kx36)
K7B203225B(64Kx32)
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd/NC
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A15
Address Inputs
32,33,34,35,36,37
44,45,46,47,48,49
81,82,99,100
83
VDD
VSS
Power Supply(+3.3V)
Ground
15,41,65,91
17,40,67,90
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
(x=a,b,c,d)
OE
Burst Address Advance
Address Status Processor 84
Address Status Controller 85
No Connect
14,16,38,39,42,43,50,66
N.C.
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
/NC
Clock
89
98
97
92
Chip Select
Chip Select
Chip Select
Byte Write Inputs
93,94,95,96
Output Enable
86
88
87
64
31
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
VDDQ
VSSQ
GW
BW
ZZ
LBO
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
- 4 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
N.C.
VDD
ZZ
(20mm x 14mm)
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7B201825B(128Kx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A16
Address Inputs
32,33,34,35,36,37,
44,45,46,47,48,49,
80,81,82,99,100
83
VDD
VSS
N.C.
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
No Connect
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,43,50,51,52,
53,56,57,66,75,78,79,95,
96
ADV
ADSP
ADSC
CLK
CS1
Burst Address Advance
Address Status Processor 84
Address Status Controller
Clock
Chip Select
85
89
98
97
DQa0~a7
DQb0~b7
DQPa, Pb
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
CS2
CS2
Chip Select
Chip Select
92
WEx
(x=a,b)
OE
GW
BW
Byte Write Inputs
93,94
VDDQ
VSSQ
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Output Enable
86
88
87
64
31
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
ZZ
LBO
- 5 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7B2036/3225B and K7B201825B are synchronous SRAM designed to support the burst address accessing sequence of the
Pentium and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges.
The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are
sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the
output pins.
Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation.
All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high
and BW is low. In K7B203625B, a 64Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and
DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd.
CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to high or low, and floating state must not be allowed.
BURST SEQUENCE TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to high or low, and floating state must not be allowed.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ
H
L
OE
X
I/O STATUS
High-Z
Notes
1. X means "Don't Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffersmust
be disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current
does not depend on cycle time.
Sleep Mode
L
DQ
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
5. Deselected means power down state of which stand-by current
depends on cycle time.
Deselected
L
X
- 6 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS2 ADSP ADSC ADV WRITE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36/32)
GW
H
BW
H
L
WEa
X
WEb
X
WEc
X
WEd
X
OPERATION
READ
H
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
GW
H
BW
H
L
WEa
X
WEb
X
OPERATION
READ
H
H
H
READ
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
L
L
L
L
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
- 7 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
VDD
RATING
-0.3 to 4.6
VDD
UNIT
V
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
VDDQ
VIN
V
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
-0.3 to VDD+0.3
-0.3 to VDDQ+0.3
1.4
V
VIO
V
PD
W
Storage Temperature
TSTG
TOPR
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
°C
Commercial
Industrial
Operating Temperature
-40 to 85
-10 to 85
Storage Temperature Range Under Bias
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0°C£ TA£70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.6
3.6
0
UNIT
VDD
V
V
V
VDDQ
VSS
* The above parameters are also guaranteed at industrial temperature range.
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.6
2.9
0
UNIT
V
V
V
VDDQ
VSS
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
SYMBOL
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
CIN
-
-
4
6
pF
pF
Output Capacitance
COUT
VOUT=0V
*Note : Sampled not 100% tested.
- 8 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
+2
UNI
mA
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
VDD=Max , VIN=VSS to VDD
-2
-2
-
Output Disabled, VOUT=VSS to VDDQ
mA
IOL
+2
-65
-75
-80
-65
-75
-80
250
230
210
130
120
110
Device Selected, IOUT=0mA,
ZZ£VIL, All Inputs=VIL or VIH
Cycle Time ³ tCYC min
Operating Current
Standby Current
ICC
ISB
-
mA
mA
-
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max,
All Inputs£0.2V or ³ VDD-0.2V
-
-
mA
mA
Device deselected, IOUT=0mA, ZZ£0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V)
ISB1
ISB2
-
-
80
50
Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,
f=Max, All Inputs£VIL or ³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL = 8.0mA
IOH = -4.0mA
IOL = 1.0mA
IOH = -1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.5*
2.0
-0.3*
1.7
0.8
VIH
VIL
VDD+03**
0.7
VIH
VDD+0.3**
The above parameters are also guaranteed at industrial temperature range.
*
VIL(Min)=-2.0(Pulse Width £ tCYC/2)
** VIH(Max)=4.6(Pulse Width £ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
PARAMETER
VALUE
0 to 3V
0 to 2.5V
1ns
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
1ns
1.5V
VDDQ/2
See Fig. 1
* The above parameters are also guaranteed at industrial temperature range.
- 9 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
Output Load(A)
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
Dout
RL=50W
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
319W / 1667W
30pF*
Dout
Z0=50W
353W / 1538W
5pF*
* Capacitive Load consists of all components of
the test environment.
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
-65
-75
-80
PARAMETER
Symbol
UNIT
Min
7.5
-
Max
Min
8.5
-
Max
Min
10
-
Max
Cycle Time
tCYC
tCD
-
-
-
ns
ns
Clock Access Time
6.5
7.5
8.0
Output Enable to Data Valid
tOE
-
3.5
-
3.5
-
4.0
ns
Clock High to Output Low-Z
tLZC
tOH
0
-
0
-
0
-
ns
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
2.5
0
-
2.5
0
-
2.5
0
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
-
ns
ns
-
3.5
-
3.5
-
4.0
2
3.5
-
2
3.5
-
2
3.5
-
ns
Clock High Pulse Width
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3
4
ns
Clock Low Pulse Width
tCL
-
3
-
4
-
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
-
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
-
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
-
ns
tSS
-
-
-
ns
tDS
-
-
-
ns
Write Setup to Clock High(GW, BW, WEx)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tWS
-
-
-
ns
tADVS
tCSS
tAH
-
-
-
ns
-
-
-
ns
-
-
-
ns
tSH
-
-
-
ns
tDH
-
-
-
ns
Write Hold from Clock High(GW, BW, WEx)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
-
-
-
ns
-
-
-
ns
-
-
-
ns
-
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
2
-
Notes : 1 The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
5. At any given voltage and temperature, tHZC is less than tLZC.
- 10 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
- 11 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
- 12 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
- 13 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
- 14 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
- 15 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
- 16 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 64Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 64K depth to 128K depth without extra logic.
I/O[0:71]
Data
Address
A[0:16]
A[16]
A[0:15]
A[16]
A[0:15]
Address Data
Address Data
CS
CS
CLK
CS2
2
2
CS2
64-bits
Microprocessor
64Kx36
SB
SRAM
CLK
ADSC
WEx
OE
64Kx36
SB
SRAM
CLK
ADSC
WEx
OE
Address
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HiGH)
CLOCK
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
Don¢t Care
*NOTES n = 14 32K depth, 15 64K depth, 16 128K depth
Undefined
- 17 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 128Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
I/O[0:71]
Data
Address
A[0:17]
A[17]
A[0:16]
A[17]
A[0:16]
Address Data
CS
Address Data
CS
CS
CLK
2
2
2
CS2
64-bits
Microprocessor
128Kx18
SB
SRAM
CLK
ADSC
WEx
OE
128Kx18
SB
SRAM
CLK
ADSC
WEx
OE
Address
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HiGH)
CLOCK
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
Don¢t Care
*NOTES n = 14 32K depth, 15 64K depth, 16 128K depth
Undefined
- 18 -
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units:millimeters/inches
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
0.10 MAX
14.00 ±0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
- 19 -
Jan 2002
Rev 0.0
相关型号：
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