K7D161888M-HC25 [SAMSUNG]
DDR SRAM, 1MX18, 0.1ns, CMOS, PBGA153, 14 X 22 MM, FCBGA-153;
| 型号： | K7D161888M-HC25 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR SRAM, 1MX18, 0.1ns, CMOS, PBGA153, 14 X 22 MM, FCBGA-153 时钟 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
Document Title
16M DDR SYNCHRONOUS SRAM
Revision History
RevNo.
History
DraftData
Remark
Rev. 0.0
Initial document.
October. 2000
Advance
Rev. 0.1
Rev. 0.2
Rev. 1.0
Add-HC37 part(Part Number, Idd, AC Characteristics)
Timing Waveform Information Changed
April. 2001
May. 2001
Sep. 2001
Advance
Advance
Final
Package thermal characteristics add.
Final specification release.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
Rev 1.0
- 1 -
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Flip Chip Ball Grid Array Package(14mmx22mm)
FEATURES
• 512Kx36 or 1Mx18 Organizations.
• Maximum Frequency : 370MHz (Data Rate : 740Mbps)
• 1.8V VDD/1.5V VDDQ (1.9V max VDDQ).
• HSTL Input and Outputs.
Maximum Access
Organization
Part Number
Frequency
Time
• Single Differential HSTL Clock.
K7D163688M-HC37 370MHz
K7D163688M-HC33 333MHz
K7D163688M-HC30 300MHz
K7D163688M-HC25 250MHz
K7D161888M-HC37 370MHz
K7D161888M-HC33 333MHz
K7D161888M-HC30 300MHz
K7D161888M-HC25 250MHz
1.7*
1.8*
1.9*
2.1*
1.7*
1.8*
1.9*
2.1*
• Synchronous Pipeline Mode of Operation with Self-Timed Late Write.
• Free Running Active High and Active Low Echo Clock Output Pin.
• Asynchronous Output Enable.
• Registered Addresses, Burst Control and Data Inputs.
• Registered Outputs.
• Single and Double Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleved and Linear Burst mode support
• Bypass Operation Support
512Kx36
1Mx18
• Programmable Impedance Output Drivers.
NOTE : *Access time equals tKXCH/tKXCL
FUNCTIONAL BLOCK DIAGRAM
SA[0:18]( or SA[0:19])
Address
Memory Array
512Kx36
or
19(or 20)
17(or 18)
Register
2:1
MUX
Dec.
(Burst Address)
CE
(1Mx18)
Clock
Buffer
Data Out
K,K
Data In
Burst
Counter
36(or 18)x2
S/A Array
36(or18)x2
Comparator
19(or 20)
W/D
Advance
Control
Array
(Burst Write
Address)
B1
B3
Write
Address
Register
SD/DD
36(or 18)x2
36(or18)x2
Write Buffer
17(or 18)
(2 stage)
2 : 1 MUX
CE
Synchronous
Select
CE
Strobe_out
&
B2
Echo Clock
Output
Output
Buffer
Data In
Register
(2 stage)
R/W
R/W control
Data Output Strobe
Data Output Enable
State Machine
LD
Internal
Clock
36(or 18)
DQ
Generator
XDIN
CQ,CQ
G
PIN DESCRIPTION
Pin Name
Pin Description
Pin Name
ZQ
Pin Description
K, K
SA
Differential Clocks
Output Driver Impedance Control Input
JTAG Test Clock
Synchronous Address Input
Synchronous Burst Address Input (SA0 = LSB)
Synchronous Data I/O
TCK
TMS
TDI
SA0, SA1
DQ
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
CQ, CQ
B1
Differential Output Echo Clocks
Load External Address
TDO
VREF
VDD
B2
Burst R/W Enable
B3
Single/Double Data Selection
Asynchronous Output Enable
Linear Burst Order
VDDQ
VSS
Output Power Supply
GND
G
LBO
NC
No Connection
Rev 1.0
Sep. 2001
- 2 -
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7D163688M(512Kx36)
1
2
3
4
5
ZQ
B1
6
SA
7
8
9
A
B
C
D
E
F
VSS
VDDQ
DQC9
VDDQ
DQC7
VDDQ
CQ1
SA
SA
SA
VDDQ
DQB9
VDDQ
DQB7
VDDQ
CQ2
VSS
DQC8
VSS
SA
VSS
SA
VSS
SA
SA
DQB8
VSS
SA
G
SA
DQC4
VSS
SA
VSS
VDD
VDD
VSS
VDD
VDD
VSS
LBO
VDD
VDD
VSS
SA
VDD
VREF
VDD
K
VSS
VDD
VDD
VSS
VDD
VDD
VSS
MODE
VDD
VDD
VSS
SA
SA
DQB6
VSS
VSS
DQC5
VSS
DQC6
VSS
DQD6
VSS
DQD5
VSS
NC
VSS
DQB5
VSS
DQB3
VSS
DQA3
VSS
DQA5
VSS
SA
DQC3
VSS
DQB4
VSS
G
H
J
VDDQ
DQC2
VDDQ
DQD2
VDDQ
CQ1
VDDQ
DQB2
VDDQ
DQA2
VDDQ
CQ2
DQC1
VSS
K
DQB1
VSS
VDD
B2
K
L
DQD1
VSS
DQA1
VSS
B3
M
N
P
R
T
DQD3
VSS
VDD
VREF
VDD
SA1
SA0
TCK
DQA4
VSS
VDDQ
DQD7
VDDQ
DQD9
VDDQ
VDDQ
DQA7
VDDQ
DQA9
VDDQ
DQD4
VSS
DQA6
VSS
VDD
SA
VDD
SA
DQD8
VSS
VSS
TDI
VSS
TDO
DQA8
VSS
U
TMS
NC
* Mode Pin(6L) is a internally NC.
K7D161888M(1Mx18)
1
2
3
SA
4
5
ZQ
B1
6
SA
7
SA
8
9
A
B
C
D
E
F
VSS
NC
VDDQ
DQB9
VDDQ
NC
SA
VDDQ
NC
VSS
DQA8
VSS
NC
SA
VSS
SA
VSS
SA
SA
VSS
DQB4
VSS
NC
SA
G
SA
VDDQ
DQA7
VDDQ
NC
SA
VSS
VDD
VDD
VSS
VDD
VDD
VSS
LBO
VDD
VDD
VSS
SA
VDD
VREF
VDD
K
VSS
VDD
VDD
VSS
VDD
VDD
VSS
MODE
VDD
VDD
VSS
SA
SA
VDDQ
CQ1
VDDQ
NC
VSS
NC
VSS
DQA5
VSS
NC
VSS
DQA4
VSS
NC
G
H
J
VSS
DQB1
VSS
NC
VSS
DQB6
VSS
NC
VDDQ
DQA2
VDDQ
NC
K
VDDQ
DQB2
VDDQ
NC
VDD
B2
VSS
DQA3
VSS
NC
VSS
DQA1
VSS
NC
K
L
VSS
DQB3
VSS
NC
VSS
DQB5
VSS
SA
B3
VDDQ
CQ1
VDDQ
NC
M
N
P
R
T
VDD
VREF
VDD
SA1
SA0
TCK
VDDQ
DQB7
VDDQ
NC
VSS
SA
VSS
DQ6
VSS
NC
VSS
DQB8
VSS
VDD
SA
VDD
SA
VDDQ
DQA9
VDDQ
VSS
TDI
VSS
TDO
U
VDDQ
TMS
NC
VSS
* Mode Pin(6L)is a internally NC.
Rev 1.0
Sep. 2001
- 3 -
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
FUNCTION DESCRIPTION
The K7D163688M and K7D161888M are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
524,288 words by 36 bits for K7D163688M and 1,048,576 words by 18 bits for K7D161888M, fabricated using Samsung's advanced
CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations, and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access
time for all SDR and DDR operations.
The chip is operated with a single +1.8V power supply and is compatible with Extended HSTL input and output. The package is
9x17(153) Ball Grid Array balls on a 1.27mm pitch.
Read Operation(Single and Double)
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least one NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM
array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and
are equal to RQ/5. For example, 250W resistor will give an output impedance of 50W. Output driver impedance tolerance is 15% by
test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates
occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In
all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior
in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is
selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 contin-
uous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are
no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs
1024 non-read cycles.
Rev 1.0
- 4 -
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
TRUTH TABLE
K
L
•
G
X
X
L
B1
X
H
L
B2
X
L
B3
X
X
H
L
DQ
Hi-Z
Hi-Z
DOUT
DOUT
DIN
Operation
Clock Stop
No Operation, Pipeline High-Z
Load Address, Single Read
Load Address, Double Read
Load Address, Single Write
Load Address, Double Write
Increment Address, Continue
•
H
H
L
•
L
L
•
X
X
X
L
H
L
•
L
L
DIN
•
H
H
X
B
NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".
- K & K are complementary.
BURST SEQUENCE TABLE
4 Burst Operation for Interleaved Burst (LBO = VDDQ)
Interleaved Burst
Case 1
Case 2
Case 3
Case 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 1.9V.
4 Burst Operation for Linear Burst (LBO = VSS)
Case 1
Case 2
Case 3
Case 4
Linear Burst Mode
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Rev 1.0
- 5 -
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
BUS CYCLE STATE DIAGRAM
LOAD
NEW ADDRESS
READ
SDR
WRITE
SDR
READ
DDR
WRITE
DDR
INCREMENT
ADDRESS
INCREMENT
ADDRESS
INCREMENT
ADDRESS
INCREMENT
ADDRESS
POWER
UP
NO OP
NOTE :
1. State transitions ; B1 =(Load Address), B1=(Increment Address, Continue)
B2 =(Read), B2 =(Write)
B3 =(Single Data Rate), B3 =(Double Data Rate)
Rev 1.0
- 6 -
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Core Supply Voltage Relative to VSS
Output Supply Voltage Relative to VSS
Voltage on any pin Relative to VSS
Output Short-Circuit Current(per I/O)
Storage Temperature
Symbol
VDD
Value
-0.5 to 2.3
-0.5 to 2.3
-0.5 to VDDQ+0.5
25
Unit
V
VDDQ
VIN
V
V
IOUT
mA
°C
TSTR
-55 to 125
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level Voltage
Input Low Level Voltage
Input Reference Voltage
Symbol
Min
Typ
1.8
1.5
-
Max
1.9
Unit
V
Note
VDD
1.7
VDDQ
VIH
1.4
1.9
V
VREF+0.1
-0.3
VDDQ+0.3
VREF-0.1
1.0
V
1, 2
1, 3
VIL
-
V
VREF
0.68
0.75
V
NOTE :1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width £ 20% of cycle time).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width £ 20% of cycle time).
DC CHARACTERISTICS
Min
Max
Parameter
Symbol
Unit
Note
IDD37
800
750
670
600
Average Power Supply Operating Current(x36)
(Cycle time = tKHKH min)
IDD33
IDD30
IDD25
-
mA
1,2
IDD37
IDD33
IDD30
IDD25
750
700
620
550
Average Power Supply Operating Current(x18)
(Cycle time = tKHKH min)
-
mA
1,2
1
Stop Clock Standby Current
(VIN=VDD-0.2V or 0.2V fixed, K=Low, K=High)
ISB1
ILI
-
150
1
mA
mA
mA
Input Leakage Current
(VIN=VSS or VDDQ)
-1
-1
Output Leakage Current
(VOUT=VSS or VDDQ)
ILO
1
Output High Voltage(Programmable Impedance Mode)
Output Low Voltage(Programmable Impedance Mode)
Output High Voltage(IOH=-0.1mA)
VOH1
VOL1
VOH2
VOL2
VDDQ/2
VSS
VDDQ
VDDQ/2
VDDQ
0.2
V
V
V
V
3
4
5
5
VDDQ-0.2
VSS
Output Low Voltage(IOL=0.1mA)
NOTE :1. Minimum cycle. IOUT=0mA.
2. 50% read cycles.
3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175W £ RQ £ 350W.
4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175W £ RQ £ 350W.
5. Minimum Impedance Mode when ZQ pin is connected to VSS.
Rev 1.0
- 7 -
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
PIN CAPACITANCE
Parameter
Input Capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
4
Unit
pF
-
-
Data Output Capacitance
COUT
VOUT=0V
5
pF
NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=1MHz)
AC TEST CONDITIONS(TA=0 to 70°C, VDD=1.7 - 1.9V, VDDQ=1.5V)
Parameter
Input High/Low Level
Symbol
VIH/VIL
VREF
Value
1.25/0.25
0.75
Unit
Note
V
V
-
-
-
-
-
-
Input Reference Level
Input Rise/Fall Time
TR/TF
0.5/0.5
0.75
ns
V
Output Timing Reference Level
Clock Input Timing Reference Level
Output Load
Cross Point
See Below
V
AC TEST OUTPUT LOAD
50W
0.75V
0.75V
50W
5pF
25W
DQ
0.75V
50W
50W
5pF
AC CHARACTERISTICS(TA=0 to 70°C, VDD=1.7 - 1.9V, VDDQ=1.5V)
-37
-33
-30
-25
Parameter
Symbol
Unit Note
Min
2.7
1.3
1.3
Max
Min
3.0
1.3
1.3
Max
Min
3.3
1.5
1.5
Max
Min
4.0
1.7
1.7
Max
Clock Cycle Time
tKHKH
tKHKL
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
Clock High Pulse Width
Clock Low Pulse Width
CQ High Pulse Width
tKLKH
tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1 tKHKL-0.2 tKHKL+0.2 tKHKL-0.3 tKHKL+0.3
tCHCL
tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1 tKLKH-0.2 tKLKH+0.2 tKLKH-0.3 tKLKH+0.3
CQ Low Pulse Width
tCLCH
1
Clock to Echo Clock(CQ) High
Clock to Echo Clock(CQ) Low
Echo Clock to Output Valid
Echo Clock to Output Hold
Echo Clock to Output High-Z
G Low to Output Low-Z
G High to Output High-Z
G Low to Output Valid
Address Setup Time
tKXCH
0.5
0.5
-
1.7
0.5
0.5
-
1.8
0.5
0.5
-
1.9
0.5
0.5
-
2.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKXCL
1.7
1.8
1.9
2.1
1,2
1
tCHQV/tCLQV
tCHQX/tCLQX
tCHQZ/tCLQZ
tGLQX
0.1
0.1
0.1
0.1
-0.2
-
-0.25
-
-0.3
-
-0.4
-
1
0.1
0.1
0.1
0.1
1
0.5
-
-
0.5
-
-
0.5
-
-
0.5
-
-
1
tGHQZ
1.7
1.8
1.9
2.1
1
tGLQV
-
1.7
-
1.8
-
1.9
-
2.1
tAVKH
0.4
0.4
0.4
0.3
0.25
0.25
-
-
-
-
-
-
0.4
0.4
0.4
0.3
0.25
0.25
-
-
-
-
-
-
0.4
0.4
0.4
0.3
0.3
0.3
-
-
-
-
-
-
0.5
0.5
0.5
0.5
0.4
0.4
-
-
-
-
-
-
Address Hold Time
tKHAX
Burst Control Setup Time
Burst Control Hold Time
Data Setup Time
tBVKH
tKHBX
tDVKH
Data Hold Time
tKHDX
NOTE : 1. See AC Test Output Load figure
2. Design target is 0ns
Rev 1.0
- 8 -
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
READ
CONTINUE READ
READ
CONTINUE READ
(burst of 2)
WRITE
CONTINUE
READ
CONTINUE
NOP
READ
(burst of 4)
NOP
NOP
WRITE
READ
(burst of 4)
(burst of 4)
(burst of 4)
9
5
1
2
4
7
6
8
10
12
11
3
K
K
tKHKH
B1
B2
tBVKH
tKHBX
B3
SA
G
A0
A5
A1
A
2
A3
tAVKH
t
KHAX
t
KHDX
t
GHQZ
t
GLQV
tGHQX
tDVKH
tGLQX
DQ
Q01
Q02
Q03
Q04
Q51
Q52
Q53
Q54
Q11
Q12
D21
D22
D23
D24
Q31
QX2
tCHQV
tCHQX
tKXCH
tCHQZ
tCHLZ
CQ
CQ
DON’T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
Rev 1.0
- 9 -
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES
(Burst Length=4, 2, 1)
READ
READ
READ
WRITE
CONTINUE
READ
CONTINUE
NOP
READ
CONTINUE CONTINUE CONTINUE READ
NOP
NOP
WRITE
(burst of 2)
READ
(burst of 2)
(burst of 4)
(burst of 1)
1
2
3
4
5
6
7
8
9
10
11
12
K
tKHKL
tKLKH
tKHKH
K
B1
B2
B3
t
BVKH
tKHBX
A0
A1
A2
A3
SA
G
tDVKH
t
AVKH
tKHAX
tKHDX
t
GHQZ
GHQX
t
GLQV
tGLQX
t
DQ
Q01
Q02
Q03
Q04
Q11
QX1
D21
D22
Q31
tKXCH
t
CHQV
t
CHQX
tCHLZ
tCHQZ
CQ
CQ
DON’T CARE
UNDEFINED
NOTE :
1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further
Continue assertions constitute invalid operations.
4. This device will have an address wraparound if further Continues are applied.
Rev 1.0
- 10
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-
ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-
ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must
be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the
application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be
left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
Notes
IR2 IR1 IR0 Instruction
TDO Output
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
IDCODE
Boundary Scan Register
Identification Register
1
2
1
3
4
3
3
3
0
0
SAMPLE-Z Boundary Scan Register
0
BYPASS
SAMPLE
BYPASS
BYPASS
BYPASS
Bypass Register
Boundary Scan Register
Bypass Register
Bypass Register
Bypass Register
1
SRAM
CORE
1
1
SA
SA
1
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
3. Bypass register is initiated to VSS when BYPASS instruction is
TDI
BYPASS Reg.
TDO
Identification Reg.
Instruction Reg.
invoked.
The Bypass Register also holds serially loaded TDI when exiting
the Shift DR states.
4. SAMPLE instruction does not places DQs in Hi-Z.
Control Signals
TAP Controller
TMS
TCK
TAP Controller State Diagram
Test Logic Reset
0
1
0
1
1
1
0
Run Test Idle
Select DR
Select IR
0
0
1
1
1
1
Capture IR
Capture DR
0
0
0
Shift IR
Shift DR
1
1
Exit1 IR
0
Exit1 DR
0
Pause DR
Pause IR
1
0
0
0
0
1
Exit2 DR
Exit2 IR
1
1
1
0
Update DR
Update IR
0
1
Rev 1.0
- 11
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
1 bits
ID Register
32 bits
Boundary Scan
68 bits
512Kx36
1M x 18
3 bits
3 bits
1 bits
32 bits
49 bits
ID REGISTER DEFINITION
Revision Number
Part Configuration
Vendor Definition
(17:12)
Samsung JEDEC Code
(11: 1)
Start Bit
(0)
Part
(31:28)
(27:18)
512Kx36
1M x 18
0000
0000
00111 00100
01000 00011
XXXXXX
XXXXXX
00001001110
00001001110
1
1
BOUNDARY SCAN EXIT ORDER(x36)
BOUNDARY SCAN EXIT ORDER(x18)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
4A
4C
3A
3B
3C
3D
2B
1B
2D
3F
1D
2F
1F
3H
2H
1H
5A
5B
5K
5L
SA
SA
SA
SA
SA
SA
DQ
DQ
DQ
DQ
DQ
CQ
DQ
DQ
DQ
DQ
ZQ
B1
SA
SA
SA
SA
SA
SA
DQ
DQ
DQ
DQ
DQ
CQ
DQ
DQ
DQ
DQ
G
6A
6C
7A
7B
7C
7D
8B
9B
8D
7F
9D
8F
9F
7H
8H
9H
5C
5G
5H
6L
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
26
27
28
29
30
31
32
4A
4C
3A
3B
3C
3D
2B
SA
SA
SA
SA
SA
SA
DQ
SA
SA
SA
SA
SA
SA
6A
6C
7A
7B
7C
7D
25
24
23
22
21
20
DQ
DQ
DQ
9B
8D
7F
19
18
17
33
34
1D
2F
DQ
CQ
DQ
DQ
9F
8H
16
15
35
3H
DQ
36
37
38
39
40
41
1H
5A
5B
5K
5L
4L
DQ
ZQ
B1
G
K
5C
5G
5H
6L
14
13
12
11
10
K
B2
K
B2
K
B3
MODE
DQ
DQ
DQ
DQ
CQ
DQ
DQ
DQ
DQ
DQ
SA
SA
SA
SA
SA
B3
MODE
DQ
4L
LBO
DQ
DQ
DQ
DQ
CQ
DQ
DQ
DQ
DQ
DQ
SA
SA
9K
8K
7K
9M
8M
9P
7M
8P
9T
8T
7P
7T
6R
5T
5R
LBO
9K
1K
2K
3K
1M
2M
1P
3M
2P
1T
2T
3T
4R
42
43
2K
DQ
DQ
DQ
7K
9
1M
CQ
DQ
8M
9P
8
7
8
44
45
46
3M
2P
1T
DQ
DQ
DQ
7
6
DQ
SA
SA
SA
SA
SA
8T
7P
7T
6R
5T
5R
6
5
4
3
2
1
5
4
47
48
49
3P
3T
4R
SA
SA
SA
3
2
1
* Reserved for Mode Pin
* Reserved for Mode Pin
Rev 1.0
- 12
Sep. 2001
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Symbol
Min
1.7
Typ
Max
1.9
Unit
V
Note
VDD
VIH
1.8
Input High Level
1.5
-
-
-
-
VDD+0.3
0.7
V
Input Low Level
VIL
-0.3
1.5
V
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
VOH
VOL
VDD
V
VSS
0.2
V
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level
Symbol
VIH/VIL
TR/TF
Min
1.8/0.0
1.0/1.0
0.9
Unit
V
Note
Input Rise/Fall Time
ns
V
Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 5.
1
JTAG AC Characteristics
Parameter
TCK Cycle Time
Symbol
Min
50
20
20
5
Max
Unit
Note
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
Clock Low to Output Valid
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tCHDX
TMS
TDI
tDVCH
tCLQV
TDO
Rev 1.0
Sep. 2001
- 13
K7D163688M
K7D161888M
512Kx36 & 1Mx18 SRAM
PACKAGE DIMENSIONS
153-FCBGA-1422
Units:millimeters/Inches
Æ
0.300 MAX M
1.27x8=10.160
R1.250
5.750
CHIP BACK SIDE
#A1 INDEX
9
8 7 6 5 4 3 2 1
CHIP AREA
1.270
153-Æ0.750±0.150
0.200 MAX
14.000
BOTTOM VIEW
TOP VIEW
UNDERFILL
153 BGA PACKAGE THERMAL CHARACTERISTICS
Parameter
Junction to Ambient(at still air)
Junction to Case
Symbol
Theta_JA
Theta_JC
Theta_JB
Thermal Resistance
Unit
°C/W
°C/W
°C/W
Note
22.8
0.6
1W Heating
Junction to Board
4.2
2W Heating
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA.
Rev 1.0
Sep. 2001
- 14
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