K7D323674A-HC45 [SAMSUNG]
DDR SRAM, 1MX36, 2.5ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153;
| 型号： | K7D323674A-HC45 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR SRAM, 1MX36, 2.5ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153 时钟 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
Document Title
32M DDR SYNCHRONOUS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 0.1
History
DraftData
Dec. 2002
Jan. 2003
Remark
Advance
Advance
Initial document.
Remove /G operation thru the Spec.
- Remove /G from PUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURA-
TION, TRUTH TABLE and TIMING WAVEFORMs
Add 300MHz Speed bin.
- Add Part ID at ORDERING INFORMATION & IDD30at DC CHARACTERIS-
TICS
Change ILI and ILo at DC CHARCATERISTICS
- ILI : MIN -1 -> -3, MAX 1 -> 3, ILo : MIN -1 -> -5, MAX 1 -> 5
Change the comment of Programmable Impedance Output Driver.
Change RECOMMENDED DC OPERATING CONDITIONS.
- VREF : Min 0.68 -> 0.65, Max 1.0 -> 0.85
PRE- PUBLICATION DRAFT
Change PIN CAPACITANCE : CIN : 3 -> 3.1
SUBJECT TO CHANGE WITHOUT NOTICE
Change AC TEST CONDITIONS : TR/RF: 0.4/0.4 -> 0.5/0.5
Change AC TIMING CHARACTERISTICS
- tCHCL : tKHKL -0.1 -> tKHKL -0.2 , tCLCH : tKLKH -0.1 -> tKLKH -0.2
- tCXCV : 2.10 -> 2.30
Rev 0.2
Feb. 2003
Advance
Change VDDQ RANGE
- In FEATURES : 1.5V VDDQ -> 1.5~.1.8V VDDQ
- In RECOMENDED DC OPERATING CONDITIONS : Max VDDQ : 1.6 -> 1.9
Change TRUTH TABLE : Remove Clock Stop
Change DC CHARACTERISTICS
- x36 IDD :
IDD50 : 950 -> 1050, IDD45 : 850 -> 950, IDD40: 800 -> 860, IDD30: 750 -> 760
- x18 IDD:
IDD50 : 850 -> 1000, IDD45 : 800 -> 900, IDD40: 750 -> 810, IDD30: 700 -> 710
- ISB1 : 150 -> 200
Change PIN CAPACITANCE : CIN : 3.1 -> 3.2, COUT : 4 -> 4.2
Change AC TIMING CHARACTERISTICS
- MIN tKHKL, tKHKL : -40 : 1.1 -> 1.2, -30 : 1.1 -> 1.4
- MIN tAVKH, tBVKH, tKHAX, tKHBX : -45 : 0.25 -> 0.27
- tKXCV MIN/MAX : 0.8/2.3 -> 1.0/2.5
Change PACKAGE THERMAL CHARACTERISTICS
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
Rev 0.4
- 1 -
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
Revision History
Rev No.
History
DraftData
Remark
Rev 0.3
Change DC CHARACTERISTICS
May. 2003
Advance
- x36 IDD :
IDD50 : 1050 -> 1150 , IDD45 : 950 -> 1050, IDD40: 860 -> 960, IDD30: 760 ->
860
- x18 IDD:
IDD50 : 1000 -> 1100, IDD45 : 900 -> 1000, IDD40: 810 -> 910, IDD30: 710 ->
810
- ISB1 : 200 -> 300
Rev 0.4
Change 300Mhz speed bin to 333Mhz
Jun. 2003
Advance
Rev 0.4
Jun. 2003
- 2 -
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
FEATURES
• 1Mx36 or 2Mx18 Organizations.
• Registered Outputs.
• Double and Single Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleved and Linear Burst mode support
• 1.8~2.5V VDD/1.5V ~1.8VDDQ.
• HSTL Input and Outputs.
• Single Differential HSTL Clock.
• Synchronous Pipeline Mode of Operation with Self-Timed
Late Write.
• Bypass Operation Support
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Flip Chip Ball Grid Array Package(14mmx22mm)
• Free Running Active High and Active Low Echo Clock Output
Pin.
• Registered Addresses, Burst Control and Data Inputs.
GENERAL DESCRIPTION
The K7D323674A and K7D321874A are 37,748,736 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
1,048,576 words by 36 bits for K7D323674A and 2,097,152 words by 18 bits for K7D321874A, fabricated using Samsung's
advanced CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representative of data output access
time for all SDR and DDR operations.
The chip is operated with 1.8~2.5V power supply and is compatible with HSTL input and output. The package is 9x17(153) Ball Grid
Array balls on a 1.27mm pitch.
ORDERING INFORMATION
Maximum
Part Number
Organization
Frequency
K7D323674A-HC50
K7D323674A-HC45
K7D323674A-HC40
K7D323674A-HC33
K7D321874A-HC50
K7D321874A-HC45
K7D321874A-HC40
K7D321874A-HC33
500MHz
450MHz
400MHz
333MHz
500MHz
450MHz
400MHz
333MHz
1Mx36
2Mx18
Rev 0.4
- 3 -
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
FUNCTIONAL BLOCK DIAGRAM
SA[0:20]( or SA[0:21])
Address
Memory Array
1Mx36
20(or 21)
18(or 19)
2:1
MUX
Register
Dec.
or
(Burst Address)
CE
(2Mx18)
Clock
Buffer
Data Out
K,K
Data In
Burst
36(or 18)x2
S/A Array
36(or18)x2
Counter
Comparator
W/D
Array
Advance
B1
(Burst Write
Address)
Control
SD/DD
Write
Address
Register
(2 stage)
B3
B2
36(or 18)x2
36(or18)x2
Write Buffer
20(or 21)
18(or 19)
2 : 1 MUX
CE
Synchronous
Select
CE
Strobe_out
&
Echo Clock
Output
Output
Buffer
R/W
Data In
R/W control
Register
Data Output Strobe
Data Output Enable
State Machine
(2 stage)
LD
Internal
Clock
Generator
36(or 18)
DQ
XDIN
CQ,CQ
PIN DESCRIPTION
Pin Name
Pin Description
Differential Clocks
Synchronous Address Input
Pin Name
TCK
Pin Description
K, K
SA
JTAG Test Clock
TMS
TDI
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
SA0, SA1
DQ
Synchronous Burst Address Input (SA0 = LSB)
Synchronous Data I/O
TDO
VREF
VDD
CQ, CQ
B1
Differential Output Echo Clocks
Load External Address
B2
Burst R/W Enable
VDDQ
VSS
Output Power Supply
GND
B3
Single/Double Data Selection
Linear Burst Order
LBO
ZQ
NC
No Connection
Output Driver Impedance Control Input
Rev 0.4
- 4 -
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7D323674A(1Mx36)
1
2
3
SA
4
SA
5
ZQ
6
SA
7
SA
8
9
A
B
C
D
E
F
VSS
VDDQ
DQ19
VDDQ
DQ28
VDDQ
CQ
VDDQ
DQ16
VDDQ
DQ7
VDDQ
CQ
VSS
DQ20
VSS
SA
VSS
SA
B1
VSS
SA
DQ15
VSS
SA
SA
SA
SA
DQ30
VSS
SA
Vss(5)
VDD
VDD
VSS
VDD
VDD
VSS
LBO(7)
VDD
VDD
VSS
SA
VDD
VREF
VDD
K
Vss(6)
VDD
VDD
VSS
SA
DQ5
VSS
VSS
DQ18
VSS
DQ27
VSS
DQ26
VSS
DQ35
VSS
NC*
VDD(4)
SA
VSS
DQ17
VSS
DQ8
VSS
DQ9
VSS
DQ0
VSS
SA
DQ21
VSS
DQ14
VSS
G
H
J
VDDQ
DQ29
VDDQ
DQ24
VDDQ
CQ
VDDQ
DQ6
VDDQ
DQ11
VDDQ
CQ
DQ31
VSS
K
VDD
VDD
VSS
DQ4
VSS
VDD
B2
K
L
DQ22
VSS
DQ13
VSS
B3
MODE(9)
VDD
VDD
VSS
M
N
P
R
T
DQ32
VSS
VDD
VREF
VDD(2)
SA1
SA0
TCK
DQ3
VSS
VDDQ
DQ25
VDDQ
DQ34
VDDQ
VDDQ
DQ10
VDDQ
DQ1
VDDQ
DQ23
VSS
DQ12
VSS
SA
VDD(3)
SA
DQ33
VSS
VSS
TDI
VSS
DQ2
VSS
U
TMS
TDO
NC(8)
K7D321874A(2Mx18)
1
2
3
SA
4
SA
5
ZQ
6
SA
7
SA
8
9
A
B
C
D
E
F
VSS
NC
VDDQ
DQ10
VDDQ
NC
VDDQ
NC
VSS
DQ5
VSS
NC
SA
VSS
SA
B1
VSS
SA
VSS
DQ11
VSS
NC
SA
SA
SA
SA
VDDQ
DQ7
VDDQ
NC
SA
Vss(5)
VDD
VDD
VSS
VDD
VDD
VSS
LBO(7)
VDD
VDD
VSS
SA
VDD
VREF
VDD
K
Vss(6)
VDD
SA
VDDQ
CQ
VSS
NC
VSS
DQ8
VSS
NC
VSS
DQ4
VSS
NC
VDD
G
H
J
VSS
DQ12
VSS
NC
VDDQ
NC
VSS
DQ9
VSS
NC
VSS
VDDQ
DQ6
VDDQ
NC
K
VDD
VDDQ
DQ15
VDDQ
NC
VDD
B2
VDD
VSS
DQ0
VSS
NC
VSS
DQ3
VSS
NC
K
L
VSS
VSS
DQ13
VSS
NC
VSS
DQ17
VSS
SA
B3
MODE(9)
VDD
VDDQ
CQ
M
N
P
R
T
VDD
VREF
VDD(2)
SA1
SA0
TCK
VDDQ
DQ16
VDDQ
NC
VDD
VSS
SA
VDDQ
NC
VSS
DQ2
VSS
NC
VSS
VSS
DQ14
VSS
VDD(4)
SA
SA
VDD(3)
SA
VDDQ
DQ1
VDDQ
VSS
TDI
VSS
U
VDDQ
TMS
TDO
NC(8)
VSS
(1) Variable address see "Variable address assignment table"
(2) Variable address see "Variable address assignment table"
(3) Variable address see "Variable address assignment table"
(4) Variable address see "Variable address assignment table"
(5) Variable address see "Variable address assignment table"
(6) Variable address see "Variable address assignment table"
(7) LBO for DDR1, M2 for DDR3
(8) NC for DDR1, ZT for DDR3
(9) Internally NC since DDR2 is not supported
Rev 0.4
Jun. 2003
- 5 -
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
VARIABLE ADDRESS ASSIGNMENT TABLE
Ball 5C
(1)
Ball 5P
(2)
Ball 7R
(3)
Ball 3R
(4)
Ball 4D
(5)
Ball 6D
(6)
Density
32 Mb
64 Mb
SA
SA
NC
SA
NC
SA
VDD
SA
SA
SA
SA
SA
VDD
VDD
SA
VDD
VDD
SA
Vss
Vss
Vss
Vss
SA
SA
Vss
Vss
Vss
Vss
SA
144 Mb
288 Mb
576 Mb
1152 Mb
SA
SA
SA
SA
SA
SA
SA
NOTE : - SRAM density definition beyond 144Mb will include the parity bits.
Rev 0.4
Jun. 2003
- 6 -
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
Read Operation(Single and Double)
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least one NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM
array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and
are equal to RQ/5. For example, 250W resistor will give an output impedance of 50W. Output driver impedance tolerance is 15% by
test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Output driver imped-
ance is updated every 64 clock cycles of Non-Read operation (Write or NOP) but since the echo clock drivers are in operation even
during Non-Read operation, the impedance is update only the drivers are not in operation. Therefore impedance updates for "0s" or
pull down drivers occur whenever the echo clock driver is driving "1s" or vice versa. Furthermore, to guarantee optimum output
driver impedance after power up, the SRAM need 2048 deselect (or write) cycles.
Rev 0.4
- 7 -
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
TRUTH TABLE
K
•
B1
H
L
B2
L
B3
X
DQ
Hi-Z
DOUT
DOUT
DIN
Operation
No Operation, Pipeline High-Z
Load Address, Single Read
Load Address, Double Read
Load Address, Single Write
Load Address, Double Write
Increment Address, Continue
•
H
H
L
H
L
•
L
•
L
H
L
•
L
L
DIN
•
H
H
X
B
NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".
- K & K are complementary.
BURST SEQUENCE TABLE
4 Burst Operation for Interleaved Burst (LBO = VDDQ)
Interleaved Burst
Case 1
Case 2
Case 3
Case 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
NOTE : - For Interleave BurstLBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V.
4 Burst Operation for Linear Burst (LBO = VSS)
Case 1
Case 2
Case 3
Case 4
Linear Burst Mode
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Rev 0.4
- 8 -
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
BUS CYCLE STATE DIAGRAM
LOAD
NEW ADDRESS
READ
SDR
WRITE
SDR
READ
DDR
WRITE
DDR
INCREMENT
ADDRESS
INCREMENT
ADDRESS
INCREMENT
ADDRESS
INCREMENT
ADDRESS
POWER
UP
NO OP
NOTE :
1. State transitions ; B1 =(Load Address), B1=(Increment Address, Continue)
B2 =(Read), B2 =(Write)
B3 =(Single Data Rate),B3 =(Double Data Rate)
Rev 0.4
- 9 -
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
ABSOLUTE MAXIMUM RATINGS
Parameter
Core Supply Voltage Relative to VSS
Output Supply Voltage Relative to V SS
Voltage on any pin Relative to VSS
Output Short-Circuit Current(per I/O)
Storage Temperature
Symbol
VDD
VDDQ
VIN
Value
Unit
V
-0.5 to 3.13
-0.5 to 2.3
V
-0.5 to VDDQ +0.5 (2.3V MAX)
V
IOUT
TSTR
TJ
25
-55 to 125
110
mA
°C
°C
W
Maxmum Junction Temperature
Maxmum Power Dissipation
PD
3.0
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stressrating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level Voltage
Input Low Level Voltage
Input Reference Voltage
Symbol
VDD
Min
1.7
Typ
2.5
1.5
-
Max
2.6
Unit
V
Note
VDDQ
VIH
1.4
1.9
V
VREF+0.1
-0.3
VDDQ+0.3
VREF-0.1
1.0
V
1, 2
1, 3
VIL
-
V
VREF
0.68
0.75
V
NOTE :1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width£ 20% of cycle time).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width £ 20% of cycle time).
DC CHARACTERISTICS
Min
Max
Parameter
Symbol
Unit
Note
IDD50
IDD45
IDD40
IDD33
1150
1050
960
Average Power Supply Operating Current(x36)
(Cycle time = tKHKH min)
-
mA
1,2
900
IDD50
IDD45
IDD40
1100
1000
910
Average Power Supply Operating Current(x18)
(Cycle time = tKHKH min)
-
mA
1,2
1
850
IDD33
Stop Clock Standby Current
ISB1
-
300
3
mA
mA
mA
(VIN=VDD-0.2V or 0.2V fixed, K=Low, K=High)
Input Leakage Current
(VIN=VSS or VDDQ)
ILI
-3
-5
Output Leakage Current
(VOUT=VSS or VDDQ)
ILO
5
Output High Voltage(Programmable Impedance Mode)
Output Low Voltage(Programmable Impedance Mode)
Output High Voltage(IOH=-0.1mA)
VOH1
VOL1
VOH2
VOL2
VDDQ /2
VSS
VDDQ
VDDQ/2
VDDQ
0.2
V
V
V
V
3
4
VDDQ-0.2
VSS
Output Low Voltage(IOL=0.1mA)
NOTE :1. Minimum cycle. IOUT=0mA.
2. 50% read cycles.
3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ /2 for 175W £ RQ £ 300W.
4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ /2 for 175W £ RQ £ 300W.
Rev 0.4
- 10
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
PIN CAPACITANCE
Parameter
Input Capacitance
Symbol
CIN
Test Condition
VIN=0V
TYP
Max
3.2
Unit
pF
-
-
Data Output Capacitance
COUT
VOUT=0V
4.2
pF
NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=500MHz)
AC TEST CONDITIONS(TA=0 to 70°C, VDD=2.37 -2.63V, VDDQ=1.5V)
Parameter
Input High/Low Level
Symbol
VIH/VIL
VREF
Value
Unit
Note
1.25/0.25
0.75
V
V
-
-
-
-
-
-
Input Reference Level
Input Rise/Fall Time
TR/TF
0.5/0.5
ns
V
Output Timing Reference Level
Clock Input Timing Reference Level
Output Load
0.75
Cross Point
See Below
V
AC TEST OUTPUT LOAD
50W
50W
0.75V
5pF
25W
DQ
0.75V
50W
0.75V
50W
5pF
Rev 0.4
Jun. 2003
- 11
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
AC TIMING CHARACTERISTICS
-50
-45
-40
-33
PARAMETER
SYMBOL
UNITS NOTES
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock Cycle Time
tKHKH
tKHKL
tKLKH
2.00
0.90
0.90
4.00
2.20
1.00
1.00
4.40
2.50
1.20
1.20
5.00
3.00
1.40
1.40
6.00
ns
ns
ns
1
Clock High Pulse Width
Clock Low Pulse Width
Setup Times
Address Setup Time
Control(B1,B2,B3) Setup Time
Data Setup Time
tAVKH
tBVKH
tDVKX
0.25
0.25
0.17
0.27
0.27
0.20
0.30
0.30
0.20
0.30
0.30
0.20
ns
ns
ns
2
2
Hold Times
Address Hold Time
tKHAX
tKHBX
tKXDX
0.25
0.25
0.17
0.27
0.27
0.20
0.30
0.30
0.20
0.30
0.30
0.20
ns
ns
ns
Control(B1,B2,B3) Hold Time
Data Hold Time
Output Times
Echo Clock High Pulse Width
Echo Clock Low Pulse Width
Clock to Echo Clock Valid
Data Output Tracking
tCHCL
tCLCH
tKXCV
tQTRK
tKHKL-0.2 tKHKL +0.2 tKHKL-0.2 tKHKL +0.2 tKHKL-0.2 tKHKL +0.2 tKHKL-0.2 tKHKL+0.2
tKLKH -0.2 tKLKH +0.2 tKLKH -0.2 tKLKH +0.2 tKLKH-0.2 tKLKH +0.2 tKLKH-0.2 tKLKH +0.2
ns
ns
ns
ns
2
2
1.00
2.50
0.20
1.00
2.50
0.20
1.00
2.50
0.20
1.00
2.50
0.20
-0.20
-0.20
-0.20
-0.20
2,3
Notes: 1. The maximum cycle time must be limited to guarantee AC timing specification.
2. This parameter is guaranteed by design, and may not be tested at values shown in the table.
3. This parameter refers to CQ and CQ rising and falling edges.
4. This parameter is only for 32Mb density
5. K and K Clocks must be used differencitally to meet AC timing specifications.
Rev 0.4
- 12
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
READ
CONTINUE READ
READ
CONTINUE READ
(burst of 2)
WRITE
CONTINUE
READ
NOP
READ
(burst of 4)
CONTINUE
NOP
NOP
WRITE
(burst of 4)
READ
(burst of 4)
(burst of 4)
9
1
2
4
5
7
3
6
8
10
11
12
K
K
tKHKH
B1
B2
tBVKH
tKHBX
B3
SA
A2
A0
A5
A1
A3
tAVKH
tKHAX
tKHDX
tDVKH
D21
DQ QX2
Q01
Q02
Q03
Q04
Q51
Q52
Q53
Q54 Q11
Q12
D22
D23
D24
Q31
tCHQV
tCHLZ
tCHQX
tKXCH
tCHQZ
CQ
CQ
DON’T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
Rev 0.4
- 13
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES
(Burst Length=4, 2, 1)
READ
READ
READ
WRITE
CONTINUE
READ
CONTINUE
NOP
READ
(burst of 4)
CONTINUE CONTINUE CONTINUE READ
NOP
NOP
WRITE
(burst of 2)
READ
(burst of 2)
(burst of 1)
1
2
3
4
5
6
7
8
9
10
11
12
K
tKHKL
tKLKH
tKHKH
K
B1
B2
B3
tBVKH
tKHBX
A2
A0
A1
A3
SA
tDVKH
tAVKH
tKHAX
tKHDX
DQ
Q01
Q02
Q03
Q04
Q11
QX1
D21
D22
Q31
tKXCH
tCHQV
tCHQX
tCHLZ
tCHQZ
CQ
CQ
DON’T CARE
UNDEFINED
NOTE :
1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further
Continue assertions constitute invalid operations.
4. This device will have an address wraparound if further Continues are applied.
Rev 0.4
- 14
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-
ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-
ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must
be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the
application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be
left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
Notes
IR2 IR1 IR0 Instruction
TDO Output
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
IDCODE
Boundary Scan Register
Identification Register
1
2
SAMPLE-Z Boundary Scan Register
PRIVATE3 Bypass Register
1
3,5
4
SAMPLE
Boundary Scan Register
SRAM
CORE
PRIVATE2 Bypass Register
PRIVATE1 Bypass Register
3,5
3,5
3
SA
SA
BYPASS
Bypass Register
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. Input terminators are switched off.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
3. Bypass register is initiated to VSS when BYPASS instruction is
invoked.
The Bypass Register also holds serially loaded TDI when exiting the
Shift DR states.
TDI
BYPASS Reg.
TDO
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
4. SAMPLE instruction dose not places DQs in Hi-Z.
TMS
TCK
5. PRIVATE1 and PRIVATE2 are reserved for the exclusive use of SAM-
SUNG. This instruction should not be used.
TAP Controller State Diagram
Test Logic Reset
0
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
1
1
1
1
Capture DR
Capture IR
0
0
0
0
Shift IR
Shift DR
1
1
Exit1 IR
Exit1 DR
0
0
Pause DR
0
0
Pause IR
0
0
1
1
Exit2 DR
Exit2 IR
1
Update DR
0
1
Update IR
1
1
0
Rev 0.4
- 15
Jun. 2003
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
BOUNDARY SCAN EXIT ORDER(x36)
BOUNDARY SCAN EXIT ORDER(x18)
1
5P
5R
5T
VDD(2)
SA1
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
5C
4A
4C
4D
3A
3B
3C
3D
2B
1B
2D
3F
1D
2F
1F
3H
2H
1H
5A
5B
5K
5L
4L
1K
2K
3K
1M
2M
1P
3M
2P
1T
2T
3R
3T
4R
7U
SA
SA
1
2
3
4
5
6
7
8
5P
5R
5T
6R
7T
7R
7P
8T
VDD(2)
SA1
SA0
SA
28
29
30
31
32
33
34
35
36
5C
4A
4C
4D
3A
3B
3C
3D
2B
SA
SA
2
3
SA0
SA
SA
4
6R
7T
SA
VSS(2
SA
VSS(2)
SA
5
SA
SA
6
7R
7P
8T
VDD(2)
SA
SA
VDD(2)
SA
SA
7
SA
SA
8
DQ1
DQ2
DQ10
DQ0
DQ12
CQ(3)
DQ3
DQ9
DQ11
DQ13
MODE
K
SA
DQ1
SA
9
9T
DQ19
DQ20
DQ28
DQ18
DQ30
CQ(3)
DQ21
DQ27
DQ29
DQ31
ZQ(1)
B1
DQ10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
8P
7M
9P
8M
9M
7K
8K
9K
6L
9
9P
DQ2
10
8M
CQ(3)
37
38
1D
2F
DQ11
CQ(3)
11
7K
DQ0
39
3H
DQ9
12
13
14
15
9K
6L
DQ3
MODE
K
40
41
42
43
44
45
1H
5A
5B
5K
5L
4L
DQ12
ZQ(1)
B1
5H
5G
9H
8H
7H
9F
5H
5G
K
K
DQ4
DQ6
DQ8
DQ14
CQ(3)
DQ5
DQ17
DQ7
DQ15
DQ16
SA
B2
B2
B3
16
17
8H
9F
DQ6
DQ4
B3
LBO
LBO
DQ22
DQ24
DQ26
DQ32
CQ(3)
DQ23
DQ35
DQ25
DQ33
DQ34
VDD(2)
SA
8F
46
47
2K
DQ15
DQ13
9D
7F
18
19
20
7F
8D
9B
DQ8
DQ7
DQ5
1M
8D
9B
8B
7D
7C
7B
7A
6D
6C
6A
48
49
50
51
52
53
54
55
3M
2P
1T
DQ17
DQ16
DQ14
SA
21
22
23
24
25
26
27
7D
7C
7B
7A
6D
6C
6A
SA
SA
SA
SA
SA
3P
3R
3T
SA
SA
VDD(2)
SA
VSS(2)
SA
VSS(2)
SA
SA
4R
7U
SA
NC
SA
SA
NC
* Reserved for Mode Pin
* Reserved for Mode Pin
NOTE :
1. If pin is connected as they should, TDO will be low. If pin is open, TDO will be high
2. This pin is place holder for higher density. TDO will be low for VSS and high for VDD
3. CQ and CQ are outputs during boundary scan. CQ reflects the input to K and CQ outputs the inverted value of K. It is prohibited to force CQ and CQ.
And TDO is ’ X’ .(Don’ t Care)
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
1 bits
ID Register
32 bits
Boundary Scan
74 bits
1M x 36
2M x 18
3 bits
3 bits
1 bits
32 bits
55 bits
Rev 0.4
Jun. 2003
- 16
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
ID REGISTER DEFINITION
Revision Number
Part Configuration
(27:18)
Vendor Definition
(17:12)
Samsung JEDEC Code
(11: 1)
Start Bit
(0)
Part
(31:28)
1M x 36
2M x 18
0000
0000
01000 00100
01001 00011
XXXXXX
XXXXXX
00001001110
00001001110
1
1
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Symbol
Min
1.7
Typ
Max
2.6
Unit
V
Note
VDD
VIH
2.5
Input High Level
0.65*VDD
-0.3
-
-
-
-
VDD+0.3
0.35*VDD
VDD
V
Input Low Level
VIL
V
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
VOH
VOL
0.75*VDD
VSS
V
0.25*VDD
V
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level
Symbol
VIH/VIL
TR/TF
Min
Unit
V
Note
VDD/0.0
1.0/1.0
VDD/2
Input Rise/Fall Time
ns
V
Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 5.
1
JTAG AC Characteristics
Parameter
TCK Cycle Time
Symbol
Min
50
20
20
5
Max
Unit
Note
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
Clock Low to Output Valid
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tCHDX
TMS
TDI
tDVCH
tCLQV
TDO
Rev 0.4
Jun. 2003
- 17
Advance
1Mx36 & 2Mx18 SRAM
K7D323674A
K7D321874A
PACKAGE DIMENSIONS
153-FCBGA-14.00x22.00 LID
Units:millimeters/Inches
A
14.000
1.27x8=10.160
Æ0.300 MAX M
METAL LID
#A1 INDEX
7.000
#A1
5.080
UNDERFILL
(Datum A)
9 8 7 6 5 4 3 2 1
B
(Datum B)
1.270 BSC
153-Æ0.760±0.150
0.750 MIN
12.000
0.150 MAX
14.000
TOP VIEW
BOTTOM VIEW
UNDERFILL
153 BGA PACKAGE THERMAL CHARACTERISTICS
Parameter
Symbol
qJC
Thermal Resistance
Unit
°C/W
°C/W
°C/W
°C/W
Note
Junction to Case
Junction to Board
0.9
6.9
qJB
Junction to Ambient(at air flow of 1m/sec)
Junction to Ambient(at still air)
qJA
16.1
19.5
qJA
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x qJA or TJ = TC + PD xqJC
2. Strongly recommends using a heat sink because it greatly improves the ambient temperature requirement
Rev 0.4
Jun. 2003
- 18
相关型号：
K7D323674C-GC370
DDR SRAM, 1MX36, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, BGA-153
SAMSUNG
K7D323674C-GC400
DDR SRAM, 1MX36, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, BGA-153
SAMSUNG
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