K7D401871M-HC22T_技术文档

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

Document Title

4M DDR SYNCHRONOUS SRAM

Revision History

Rev.No.

History

DraftData

Remark

Rev. 0.0

Rev.0.5

Rev.1.0

Initial document.

Aug. 1998

July. 1999

Nov. 1999

Advance

Correction on the miss print and the package size.

Added 4ns cycle time (500Mbps).

Preliminary

Final

Rev 1.0

Nov. 1999

1

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

FEATURES

• 128Kx36 or 256Kx18 Organizations.

• 2.5V Core/1.5V Output Power Supply.

• HSTL Input and HSTL Outputs.

• Programmable Impedance Output Drivers.

Cycle

Time

Access

Time

Organization

Part Number

• Single Differential HSTL Clock.

• Synchronous Pipeline Mode of Operation with Self-Timed

Late Write.

• Free Running Active High and Active Low Echo Clock Output

Pin.

• Asynchronous Output Enable.

• Registered Addresses, Burst Control Inputs and Data Inputs.

• Registered Outputs.

• Single and Double Data Rate Burst Read and Write.

• 4 Count Burst Operation

• JTAG 1149.1 Compatible Test Access port.

• 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).

K7D403671M-H25

K7D403671M-H22

K7D403671M-H20

K7D403671M-H16

K7D401871M-H25

K7D401871M-H22

K7D401871M-H20

K7D401871M-H16

4

44

5

2.4

2.7

3.3

2.4

2.7

3.3

128Kx36

6

4

44

5

256Kx18

6

FUNCTIONAL BLOCK DIAGRAM

SA[0:16]( or SA[0:17])

Address

Memory Array

128Kx36

or

17(or 18)

15(or 16)

2:1

Register

Dec.

MUX

(Burst Address)

CE

(256Kx18)

Clock

Buffer

Data Out

K,K

Data In

Burst

36(or 18)x2

S/A Array

Counter

Comparator

17(or 18)

W/D

Array

Advance

Control

(Burst Write

Address)

B1

B3

Write

Address

SD/DD

36(or 18)x2

Register

(2 stage)

CE

36(or 18)x2

15(or 16)

2 : 1 MUX

Write Buffer

Synchronous

Select

CE

Strobe_out

&

B2

Echo Clock

Output

Buffer

Data In

Register

(2 stage)

R/W

R/W control

Data Output Strobe

LD

Data Output Enable

State Machine

Internal

Clock

36(or 18)

DATA

Generator

XDIN

KQ,KQ

G

PIN DESCRIPTION

Pin Name

Pin Description

Pin Name

G

Pin Description

K, K

SA

Differential Clocks

Asynchronous Output Enable

JTAG Test Clock

Synchronous Address Input

Synchronous Burst Address Input

Synchronous Data I/O

TCK

TMS

TDI

SA0, SA1

DQ

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

VDD

Core Power Supply

TDO

ZQ

VDDQ

VREF

B1

Output Power Supply

Output Driver Impedance Control Input

Linear Burst Order

No Connect (Reserved)

GND

HSTL Input Reference Voltage

Load External Address

LBO

MODE

VSS

B2

Burst R/W Enable

B3

Single/Double Data Selection

Differential Output Echo Clocks

NC

No Connection

KQ, KQ

Rev 1.0

Nov. 1999

2

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7D403671(128Kx36)

1

2

3

4

5

ZQ

B1

6

SA

7

8

9

A

B

C

D

E

F

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

VDDQ

DQ

SA

VDDQ

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

SA

VSS

SA

VSS

SA

VDDQ

DQ

SA

G

SA

VDDQ

DQ

N.C

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

NC

VDD

SA

VSS

VDD

VSS

VDD

VSS

LBO

VDD

VSS

SA

VDD

VREF

VDD

K

VSS

VDD

VSS

VDD

VSS

MODE

VDD

VSS

SA

NC

VSS

DQ

VSS

DQ

VSS

DQ

VSS

DQ

VSS

SA

VDDQ

KQ

VDDQ

KQ

G

H

J

VDDQ

DQ

VDDQ

DQ

K

VDDQ

DQ

VDD

B2

VDDQ

DQ

K

L

VDDQ

KQ

B3

VDDQ

KQ

M

N

P

R

T

VDD

VREF

VDD

SA1

SA0

TCK

VDDQ

DQ

VDDQ

DQ

VDDQ

DQ

VDD

SA

VDDQ

DQ

VSS

TDI

VSS

TDO

U

VDDQ

TMS

NC

VDDQ

K7D401871(256Kx18)

1

2

3

4

5

ZQ

B1

6

SA

7

8

9

A

B

C

D

E

F

VSS

NC

VSS

DQ

VSS

NC

VSS

DQ

VSS

NC

VSS

DQ

VSS

NC

VSS

DQ

VSS

VDDQ

DQ

SA

VDDQ

NC

VSS

DQ

VSS

NC

VSS

DQ

VSS

NC

VSS

DQ

VSS

NC

VSS

DQ

VSS

NC

VSS

SA

VSS

SA

VSS

SA

VDDQ

NC

SA

G

SA

VDDQ

DQ

NC

VSS

NC

VSS

DQ

VSS

NC

VSS

DQ

VSS

SA

VSS

VDD

VSS

VDD

VSS

LBO

VDD

VSS

SA

VDD

VREF

VDD

K

VSS

VDD

VSS

VDD

VSS

MODE

VDD

VSS

SA

NC

VSS

DQ

VSS

NC

VSS

DQ

VSS

NC

VSS

SA

VDDQ

KQ

VDDQ

NC

G

H

J

VDDQ

NC

VDDQ

DQ

K

VDDQ

DQ

VDD

B2

VDDQ

NC

K

L

VDDQ

NC

B3

VDDQ

KQ

M

N

P

R

T

VDD

VREF

VDD

SA1

SA0

TCK

VDDQ

DQ

VDDQ

NC

VDDQ

NC

VDD

SA

VDD

SA

VDDQ

DQ

VSS

TDI

VSS

TDO

U

VDDQ

TMS

NC

VDDQ

Rev 1.0

Nov. 1999

3

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

FUNCTION DESCRIPTION

The K7D403671M and K7D401871M are 4,718,592 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as

131,072 words by 36 bits for K7D403671M and 262,144 words by 18 bits for K7D401871M, fabricated using Samsung's advanced

CMOS technology.

Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the

rising edge of K clock, all addresses and burst control inputs are registered internally. And data inputs are registered at rising edges

of K clock for a single data controlled mode, or at rising and falling edges of K clock for a dual data controlled mode, in the following

cycle after write addresses are asserted.

An internal write data buffer allows write data to be stored before loaded into memory core in the next write cycles. Data outputs are

updated from output registers on the rising edges of K clock for a single data controlled mode, or on the rising and falling edges of

the K clock for a dual data controlled mode. Read data is referenced to Echo clock outputs. The chip is operated with a single +2.5V

power supply and is compatible with HSTL input and HSTL output. The package is 9x17(153) Ball Grid Array balls on a 1.27mm

pitch.

Read Operation(Single and Double)

During single read operation, the address is registered during the first clock edge, the internal array is read between this first edge

and second edge, it is read again in the following cycle from the address increased by burst counter, and data is captured in the out-

put register driven to the CPU during the second clock high edge and third clock high edge. During double read operation, the

address is registered during the first clock edge, the internal array is read twice as much as wider than external bits, transfered to

dout buffer sequentially by burst order and the following cycle the same operation occur from address increased by burst counter,

and data is captured in the output register driven to the CPU at active high clock edge and active low clock edge.

During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This

characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-

ple SRAM cycles to perform a single read operation.

Write(Store) Operation

All addresses and R/W are sampled with B1 and B2 on the clock rising edge. B1 and B2 are low on the rising clock. Write address is

sampled on the rising clock, one cycle after write address and Din have been sampled by the SRAM during 2 consecutive cycles at

each active high and low clock edge and stored to write buffer for next real writing array. Actual write is done by using write data

buffer on the SRAM that capture the write addresses on one address write cycles, and write the array on the next address write

cycles. The "next address write cycles" can actually be many cycles away, broken by a series of read cycles. The SRAM is able to

write 72 bits per cycle with 2-prefetched write buffer. This alleviates timing penalty of read after write cycle.

Echo clock operation

To assure the output tracibility, the SRAM provides the output Echo clock, pair of complement clock, which is synchronized with inter-

nal data output.

During read and write cycle, the Echo clock is triggered by internal output clock signal, and transfered to external through same struc-

tures as output driver in read cycle.

Bypass Read Operation

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to

be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address

is the same as the contents of the stored write address latch. If the contents match, the read data must be supplied from the stored

write data latch with standard read timing. If there is no match, the read data comes from the SRAM array.

PROGRAMMABLE IMPEDANCE OUTPUT BUFFER OPERATION

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).

The value of RQ is five times the output impedance desired. For example, 250W resistor will give an output impedance of 50W. The

allowable range of RQ is between 175W and 350W. Impedance updates occur early in cycles that do not activate the outputs, such

as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance updates are transparent to the user

and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Periodic readjustment is necessary as the

impedance is greatly affected by drifts in supply voltage and temperature. Impedance updates occur no more often than every 32

clock cycles. Clock cycles are counted whether the SRAM is selected or not and proceed regardless of the type of cycle being exe-

cuted. Therefore, the user can be assured that after 33 continuous read cycles have occurred, an impedance update will occur the

next time G are high at a rising edge of the K clock. There are no power up requirements for the SRAM. However, to guarantee opti-

mum output driver impedance after power up, the SRAM needs 1024 non-read cycles.

Rev 1.0

Nov. 1999

4

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

TRUTH TABLE

K

L

•

G

H

L

B1

X

H

L

B2

X

L

B3

X

H

L

DQ

Hi-Z

DOUT

DIN

Operation

Clock Stop

No Operation, Pipeline High-Z

Load Address, Single Read

Load Address, Double Read

Load Address, Single Write

Load Address, Double Write

Increment Address, Continue

•

H

L

•

L

•

H

L

H

L

•

L

DIN

•

H

X

B

NOTE : B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".

BURST SEQUENCE TABLE

4 Burst Operation for Interleaved Burst (LBO = High)

Interleaved Burst

Case 1

Case 2

Case 3

Case 4

A1

A0

A1

A0

A1

A0

A1

A0

First Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

4 Burst Operation for Linear Burst (LBO = Low)

Case 1

Case 2

Case 3

Case 4

Interleaved Burst

A1

A0

A1

A0

A1

A0

A1

A0

First Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Rev 1.0

Nov. 1999

5

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

BUS CYCLE STATE DIAGRAM

LOAD

NEW ADDRESS

READ

SDR

WRITE

SDR

READ

DDR

WRITE

DDR

INCREMENT

ADDRESS

INCREMENT

ADDRESS

INCREMENT

ADDRESS

INCREMENT

ADDRESS

B1

POWER

UP

NO OP

NOTE :

1. State transitions ; B¹=(Load Address), B1=(Increment Address, Continue)

B2 =(Read), B2 =(Write)

B3 =(Single Data Rate), B3 =(Double Data Rate)

Rev 1.0

Nov. 1999

6

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

ABSOLUTE MAXIMUM RATINGS

Parameter

Core Supply Voltage Relative to VSS

Output Supply Voltage Relative to VSS

Voltage on any pin Relative to VSS

Maximum Power Dissipation

Symbol

VDD

Value

-0.5 to 3.5

-0.5 to VDD+0.5

-

Unit

V

VDDQ

VIN

V

PD

W

Output Short-Circuit Current(per I/O)

Storage Temperature

IOUT

TSTR

25

mA

°C

-55 to 125

NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.

Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

Parameter

Core Power Supply Voltage

Output Power Supply Voltage

Input High Level Voltage

Symbol

Min

2.4

Typ

2.5

1.5

-

Max

2.6

Unit

V

Note

VDD

VDDQ

VIH

1.4

1.6

V

VREF+0.1

-0.3

VDD + 0.3

VREF-0.1

1.0

V

1, 2

1, 3

Input Low Level Voltage

VIL

-

V

Input Reference Voltage

VREF

TJ

0.6

0.75

-

V

Operating Junction Temperature

20

110

°C

4

NOTE :1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring

timing parameters.

2. VIH (Max)DC=VDD+0.3, VIH (Max)AC=VDD+1.5V(pulse width £ 5ns).

3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width £ 5ns).

4. Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and

mounting site thermal impedance. TJ=TA + PD x THETA_JA

DC CHARACTERISTICS

Min

Max

Parameter

Symbol

Unit

Note

IDD4

IDD44

IDD5

IDD6

700

650

600

550

Average Power Supply Operating Current(x36)

(Cycle time = tKHKH min)

-

mA

1,2

IDD4

IDD44

IDD5

IDD6

650

600

550

500

Average Power Supply Operating Current(x18)

(Cycle time = tKHKH min)

-

mA

1,2

1

Stop Clock Standby Current

(VIN=VDD-0.2V or 0.2V fixed, Clock=Low)

ISB1

50

Input Leakage Current

(VIN=VSS or VDD)

ILI

-1

1

mA

Output Leakage Current

(VOUT=VSS or VDDQ except KQx,KQx)

ILO

Output High Voltage(Programmable Impedance Mode)

Output Low Voltage(Programmable Impedance Mode)

Output High Voltage(IOH=-0.1mA )

VOH1

VOL1

VOH3

VOL3

VDDQ/2

VSS

VDDQ

VDDQ/2

VDDQ

0.2

V

3

4

5

VDDQ-0.2

VSS

Output Low Voltage(IOL=0.1mA)

NOTE :1. Minimum cycle. IOUT=0mA.

2. 50% read cycles.

3. |IOH|=(VDDQ/2)/(RQ/5)±10% @VOH=VDDQ/2 for 175W £ RQ £ 350W.

4. |IOL|=(VDDQ/2)/(RQ/5)±10% @VOL=VDDQ/2 for 175W £ RQ £ 350W.

5. Minimum Impedance Mode when ZQ pin is connected to VDD.

Rev 1.0

Nov. 1999

7

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

PIN CAPACITANCE

Parameter

Symbol

CIN

Typ.

Max

Unit

pF

Input Pin Capacitance

I/O Pin Capacitance

Clock Pin Capacitance

-

6

7

CI/O

pF

CCLK

pF

*NOTE : Periodically Sampled and not 100% tested. (dV=0V, f=1MHz)

AC TEST CONDITIONS(TJ=20 to 110°C, VDD=2.4 -2.6V, VDDQ=1.4 - 1.6V)

Parameter

Input High/Low Level

Symbol

VIH/VIL

VREF

Value

Unit

V

Note

1.25/0.25

0.75

-

Input Reference Level

Input Rise/Fall Time

V

TR/TF

1.0/1.0

ns

V

Output Timing Reference Level

Clock Input Timing Reference Level

Output Load

0.75

Cross Point

See Below

V

AC TEST OUTPUT LOAD

Output Load(A)

0.75V

Output Load(B)

0.75V

(for tKQLZ, tKQHZ, tGLQZ & tGHQZ)

VREF

Dout

ZQ

Z0=50W

DEVICE

UNDER

TEST

DEVICE

UNDER

TEST

50W

0.75V

5pF*

250W

ZQ

*Capacitive load consists of all components

of the tester environment

AC CHARACTERISTICS

-25

-22

-20

-16

Parameter

Symbol

Unit

Note

Min

4.0

1.6

-

Max

Min

4.4

1.8

-

Max

Min

5.0

2.0

-

Max

Min

6.0

2.4

-

Max

Clock Cycle Time

tKHKH

tKHKL

tKLKH

tKHKE

tKEQV

tKEQX

tKQLZ

tKQHZ

tGLQX

tGHQZ

tGLQV

tGHQX

tAVKH

tKHAX

tBVKH

tKHBX

tDVKH

tKHDX

-

ns

-

Clock High Pulse Width

Clock Low Pulse Width

Clock to Echo Clock(KQ, KQ)

Echo Clock to Output Valid

Echo Clock to Output Hold

Echo Clock to Output Low-Z

Echo Clock to Output High-Z

G Low to Output Low-Z

G High to Output High-Z

G Low to Output Valid

G High to Output Hold

Address Setup Time

-

2.2

2.5

3.0

1

1,2

1

-

0.2

-

0.2

-

0.2

-

0.3

-0.5

-

-0.5

-

-0.5

-

-0.6

-

1

0.2

1

0.5

-

0.5

-

0.5

-

0.5

-

ns

1

2.2

2.7

3.3

1

-

2.2

-

2.2

-

2.7

-

3.3

1

0.5

-

0.5

-

0.5

-

0.5

0.7

-

Address Hold Time

Burst Control Setup Time

Burst Control Hold Time

Data Setup Time

Data Hold Time

NOTE : 1. See AC Test Output Load figure

2. Design target is 0ns

Rev 1.0

Nov. 1999

8

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES

(Burst Length=4)

READ

CONTINUE

(burst of 2)

READ

CONTINUE

(burst of 2)

WRITE

CONTINUE

(burst of 2)

READ

CONTINUE

(burst of 2)

READ

(burst of 2)

NOP

READ

NOP

WRITE

READ

(burst of 2)

9

5

1

2

4

7

6

8

10

12

3

11

K

t

KHKL

t

KLKH

tKHKH

B1

B2

t

BVKH

t

KHBX

B3

SA

G

A

2

A5

A1

A3

A0

t

AVKH

KHAX

t

KHDX

DVKH

t

GHQZ

tGLQV

tGLQX

t

GHQX

t

DQ

Q01

Q02

Q03

Q04

Q51

Q52

Q53

Q54

Q11

Q12

D21

D22

D23

D24

Q31

QX2

t

KHKE

CEQV

tKEQX

t

KQHZ

t

KQLZ

KQ

DON¢T CARE

UNDEFINED

NOTE

1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disabled(High-Z) one clock cycle after NOP detected.

3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.

4. The second NOP cycle is not necessary for correct device operation.

However, at high clock frequencies it may be required to prevent bus contention.

Rev 1.0

Nov. 1999

9

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES

(Burst Length=4)

READ

WRITE

CONTINUE

(burst of 2)

READ

CONTINUE

(burst of 2)

CONTINUE CONTINUE CONTINUE

(burst of 2) (burst of 2) (burst of 2)

NOP

READ

NOP

WRITE

READ

(burst of 2)

1

2

3

4

5

6

7

8

9

10

11

12

K

t

KHKL

tKLKH

t

KHKH

B1

B2

t

BVKH

t

KHBX

B3

SA

A2

A1

A3

A0

t

DVKH

t

AVKH

t

KHAX

G

t

KHDX

t

GHQZ

GHQX

tGLQV

tGLQX

t

DQ

Q01

Q02

Q03

Q04

Q11

QX1

D21

D22

Q31

t

KHKE

t

KEQV

t

KEQX

t

KQLZ

t

KQHZ

KQ

DON¢T CARE

UNDEFINED

NOTE :

1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disabled(High-Z) one clock cycle after NOP detected

3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation.

4. This device will have an address to wrap around if further Continues are applied.

5. The second NOP cycle is not necessary for correct device operation.

however, at high clock frequencies it may be required to prevent bus contention.

Rev 1.0

Nov. 1999

10

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Teat Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction

Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM. TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

JTAG Instruction Coding

JTAG Block Diagram

IR2 IR1 IR0 Instruction

TDO Output

Note

0

1

0

1

0

1

0

1

0

1

0

1

SAMPLE-Z Boundary Scan Register

IDCODE Identification Register

SAMPLE-Z Boundary Scan Register

1

2

1

3

4

3

0

BYPASS

SAMPLE

BYPASS

Bypass Register

Boundary Scan Register

Bypass Register

1

SRAM

CORE

1

SA(4R)

TDI

SA(5R)

TDO

1

NOTE :

1. Places DQs,KQx,KQx in Hi-Z in order to sample all input data regard-

less of other SRAM inputs.

BYPASS Reg.

2. TDI is sampled as an input to the first ID register to allow for the serial

shift of the external TDI data.

3. Bypass register is initiated to VSS when BYPASS instruction is

invoked. The Bypass Register also holds serially loaded TDI when

exiting the Shift DR states.

Identification Reg.

Instruction Reg.

4. SAMPLE instruction dose not places DQs,KQx,KQx in Hi-Z.

Control Signals

TAP Controller

TMS

TCK

TAP Controller State Diagram

Test Logic Reset

0

1

Run Test Idle

Select DR

Select IR

0

Capture IR

0

1

Capture DR

0

Shift IR

1

Shift DR

1

Exit1 IR

0

Exit1 DR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update IR

1

0

Update DR

0

Rev 1.0

Nov. 1999

11

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

1 bits

ID Register

32 bits

Boundary Scan

68 bits

128Kx36

256Kx18

3 bits

1 bits

32 bits

49 bits

ID REGISTER DEFINITION

Revision Number

Part Configuration

Vendor Definition

(17:12)

Samsung JEDEC Code

(11: 1)

Start Bit

(0)

Part

(31:28)

(27:18)

128Kx36

256Kx18

0000

00101 00100

00110 00011

XXXXXX

00001001110

1

BOUNDARY SCAN EXIT ORDER(x36)

BOUNDARY SCAN EXIT ORDER(x18)

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

4A

4C

3A

3B

3C

3D

2B

1B

2D

3F

1D

2F

1F

3H

2H

1H

5A

5B

5K

5L

SA

6A

6C

7A

7B

7C

7D

8B

9B

8D

7F

9D

8F

9F

7H

8H

9H

5C

5G

5H

6L

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

26

27

28

29

30

31

32

4A

4C

3A

3B

3C

3D

2B

SA

6A

6C

7A

7B

7C

7D

25

24

23

22

21

20

NC¹

DQ

NC¹

DQ

NC¹

DQ

NC¹

DQ

KQ

DQ

ZQ

B1

DQ

KQ

DQ

G

DQ

9B

8D

7F

19

18

17

33

34

1D

2F

DQ

KQ

DQ

9F

8H

16

15

35

3H

DQ

36

37

38

39

40

41

1H

5A

5B

5K

5L

4L

DQ

ZQ

B1

G

K

5C

5G

5H

6L

14

13

12

11

10

K

B2

K

B2

2

B3

MODE

DQ

MODE

DQ

4L

LBO

DQ

KQ

DQ

SA

9K

8K

7K

9M

8M

9P

7M

8P

9T

8T

7P

7T

6R

5T

5R

LBO

9K

1K

2K

3K

1M

2M

1P

3M

2P

1T

2T

3T

4R

DQ

KQ

DQ

SA

42

43

2K

DQ

7K

9

1M

KQ

DQ

8M

9P

8

7

8

44

45

46

47

48

49

3M

2P

1T

3P

3T

4R

DQ

SA

7

6

DQ

SA

8T

7P

7T

6R

5T

5R

6

5

4

3

2

1

5

SA

4

SA

3

SA

SA0

SA1

2

SA0

SA1

1

NOTE :

1. Pins 7D/3D are no connection pins to internal chip and place holders for 8M/16M parts. The scanned data are fixed to “1” for this 4M part.

2. Mode pin 6L is no connection pin to internal chip. The scanned data is fixed to “1”.

Rev 1.0

Nov. 1999

12

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

JTAG DC OPERATING CONDITIONS

Parameter

Power Supply Voltage

Symbol

Min

2.4

Typ

Max

2.6

Unit

V

Note

VDD

VIH

2.5

Input High Level

1.7

-

VDD+0.3

0.7

V

Input Low Level

VIL

-0.3

2.0

V

Output High Voltage(IOH=-2mA)

Output Low Voltage(IOL=2mA)

VOH

VOL

VDD

V

VSS

0.4

V

NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.

JTAG AC TEST CONDITIONS

Parameter

Symbol

Min

Unit

V

Note

Input High/Low Level

Input Rise/Fall Time

VIH/VIL

2.5/0.0

1.0/1.0

1.25

TR/TF

ns

V

Input and Output Timing Reference Level

1

NOTE : 1. See SRAM AC test output load on page 7.

JTAG AC Characteristics

Parameter

TCK Cycle Time

Symbol

Min

50

20

5

Max

Unit

ns

Note

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tDVCH

tCHDX

tSVCH

tCHSX

tCLQV

-

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

-

5

-

5

-

5

-

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

5

-

5

-

0

10

JTAG TIMING DIAGRAM

TCK

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tCHDX

TMS

TDI

tDVCH

tSVCH

tCHSX

PI

(SRAM)

tCLQV

TDO

Rev 1.0

Nov. 1999

13

K7D403671M

K7D401871M

128Kx36 & 256Kx18 SRAM

153 BGA PACKAGE DIMENSIONS

1.27

0.050

0.60 ±0.10

0.024 ±0.004

9

8 7 6 5 4 3 2 1

0.56 ±0.04

0.022 ±0.002

12.50 ±0.10

0.492 ±0.004

0.75 ±0.15

0.90 ±0.10

0.035 ±0.004

2.21

MAX

0.087

153-

^Æ0.030 ±0.006

Æ

0.3/0.012MAX

14.00 ±0.10

0.551 ±0.004

0.15

MAX

0.006

BOTTOM VIEW

TOP VIEW

NOTE :

1. All Dimensions are in Millimeters.

2. Solder Ball to PCS Offset : 0.10 MAX.

3. PCB to Cavity Offset : 0.10 MAX.

Rev 1.0

Nov. 1999

14


型号：	K7D401871M-HC22T
厂家：	SAMSUNG
描述：	Standard SRAM, 256KX18, CMOS, PBGA153 时钟静态存储器内存集成电路
文件：	总14页 (文件大小：327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7D401871M-HC22T [SAMSUNG]

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